經濟部智慧財產局員工消費合作社印製 1249210 A7 _B7_ 五、發明說明（） 本發明係與晶片構裝有關，更詳而言之是指一種晶片 構裝結構。 請參閱笫一圖，係為一種習用之積體電路晶片之構裝 (1)，該構裝（1)大體上包含有一承載體(2)、一晶片（3)及一 5 遮蓋（4);其中該承載體(2)具有一開口向上之容室（2a)，該 容室（2a)之底部佈設有呈預定數目及態樣之銲墊（圖未 示），該晶片（3)則係黏著於該容室（2a)底部中央位置上，並 藉由銲線（5)與各該銲墊電性連接，而該遮蓋（3)係用以封 抵該承載體(2)之開口，使位於該容室（2a)中之晶片（3)可與 10 外界隔離者。 惟，上述之承載體(2)僅能供容置單一晶片（3)，如笫二 圖所示，如欲於一外界電路板（6)上裝配多數晶片（3)時， 則必須以並連方式裝配多數個承載體(2)，方能供以容置多 數個晶片（3)，但此方式將使得多晶片之整體構裝體積加 15 大，對於現今電子產品之「體積小型化」而言，非但不適 用，且會造成製造成本上之增加，對產業界而實為一項不 利之處； 因此逐有業者研發一種晶片之構裝結構，其與上述習 知構裝差異在於；該承載體更具有一位於該容室反側之笫 20 二容室，而可於該笫二容室内置設一笫二晶片，並於該笫 二容室之底部佈設有多數呈預定數量及態樣之銲墊，而可 藉由多數之銲線將該銲墊與該晶片呈電性連接；但，以此 種構裝之方式雖可同時獲得二個晶片之處理速度，但由於 該容室與該笫二容室之底部，必須供銲線置設及供打線器 3- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂i 線— ♦!----------------- 經濟部智慧財產局員工消費合作社印製 1249210 A7 厂 _B7___ 五、發明說明（） 活動，以致其容室容積無法縮小，相對使得整體之構裝亦 無法因應現今潮流所需而減小其面積，此對現今科技業者 而言仍係一項必須面對而解決之重要課題。 有鑑於上述之種種缺失，本案發明人乃經詳思細索， 5 並累積多年從事晶片構裝製造及研冗開發之經驗，終而有 本發明之產生。 亦即本發明之主要目的乃在提供一種之晶片構裝結 構，係可以單一承載體容置一個以上之晶片，並縮小其整 體構裝之體積者。 10 緣此，本發明所提供一種晶片構裝結構，包含有··一 座體，該座體具有一頂面及一底面；且該頂面向下凹陷形 成有一笫一容室，該底面則向上凹陷形成有一笫二容室； 至少二晶片，該各晶片係分別設置於該笫一、二容室中， 並藉由多數之銲線與該座體電性連接，且至少一晶片上之 15 銲線係連接於該座體之頂面上者。 為使審查委員能詳細瞭解本發明之實際構造及特點， 兹列舉以下實施例並配合圖示詳細說明如后，其中： 笫一圖係一種習用晶片構裝之剖視圖； 笫二圖係一種習用多晶片之模組構裝剖視圖； 20 笫三圖係本發明笫一較佳實施例之剖視圖； 笫四圖係本發明笫一較佳實施例之使用狀態剖視圖； 笫五圖係本發明笫二較佳實施例之剖視圖； 笫六圖係本發明笫三較佳實施例之剖視圖； 笫七圖係本發明笫四較佳實施例之剖視圖； (請先閱讀f*面之•注意事項再填寫本頁) 訂---------線丨 -4_Printed by the Ministry of Economic Affairs, Intellectual Property Office, Staff Consumer Cooperatives 1249210 A7 _B7_ V. INSTRUCTION DESCRIPTION () The present invention relates to wafer fabrication, and more particularly to a wafer construction structure. Please refer to the first figure, which is a conventional integrated circuit chip assembly (1), the structure (1) generally comprises a carrier (2), a wafer (3) and a 5 cover (4); The carrier (2) has an opening-up chamber (2a), and a bottom of the chamber (2a) is provided with a predetermined number and shape of pads (not shown), and the wafer (3) is Adhered to the central position of the bottom of the chamber (2a), and electrically connected to each of the pads by a bonding wire (5), and the cover (3) is used to seal the opening of the carrier (2). The wafer (3) located in the chamber (2a) can be isolated from the outside of the room. However, the above-mentioned carrier (2) can only accommodate a single wafer (3). As shown in FIG. 2, if a large number of wafers (3) are to be mounted on an external circuit board (6), A plurality of carriers (2) can be assembled in a continuous manner to accommodate a plurality of wafers (3). However, this method will increase the overall package size of the multi-chip by 15 times, and is "volume miniaturization" for today's electronic products. In fact, it is not applicable, and it will cause an increase in manufacturing cost, which is a disadvantage for the industry; therefore, the manufacturer has developed a wafer structure, which differs from the above-mentioned conventional structure in that; The carrier further has a second chamber located on the opposite side of the chamber, and a second wafer can be built in the second chamber, and a majority of the predetermined number is disposed at the bottom of the second chamber. a solder pad of the aspect, wherein the solder pad can be electrically connected to the wafer by a plurality of bonding wires; however, although the processing speed of the two wafers can be simultaneously obtained by such a configuration, the capacity is The bottom of the chamber and the second chamber must be provided with wire bonding and wire feeders 3- This paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm) (please read the notes on the back and fill out this page). Order i-line ♦!------------ ----- Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printed 1249210 A7 factory _B7___ five, invention description () activities, so that its volume can not be reduced, so that the overall structure can not meet the needs of today's current Reducing its area is still an important issue that must be addressed and solved for today's technology industry. In view of the above various shortcomings, the inventor of the present invention has been carefully thought out, 5 and accumulated years of experience in wafer fabrication and research and development, and finally produced the present invention. That is, the main object of the present invention is to provide a wafer structure which can accommodate more than one wafer by a single carrier and reduce the volume of the entire package. Therefore, the present invention provides a wafer structure comprising a body having a top surface and a bottom surface; and the top surface is recessed downward to form a chamber, and the bottom surface is recessed upward. Forming a second chamber; at least two wafers, the wafers are respectively disposed in the first and second chambers, and electrically connected to the holder by a plurality of bonding wires, and at least one of the wafers are soldered The wire is attached to the top surface of the seat. In order to enable the reviewing committee to have a detailed understanding of the actual structure and features of the present invention, the following embodiments are illustrated and described in detail with reference to the drawings, wherein: FIG. 1 is a cross-sectional view of a conventional wafer assembly; 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 6 is a cross-sectional view of a preferred embodiment of the present invention; FIG. 7 is a cross-sectional view of a preferred embodiment of the present invention; (please read the f* surface first; Page) Order --------- Line 丨-4_
1249210 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 笫八圖係本發明笫五較佳實施例之剖視圖。 請先參閱笫三及笫四圖’係本發明笫一較佳實施例所 提供之晶片構裝結構（10)，主要包含有； 一座體（11)，該座體（11)係可為塑膠、強化塑膠、玻璃 5 纖維或陶瓷··等材質所一體製成之電路板；其具有一頂面 (111)及一底面（112)，且由該頂面Oil)向下凹陷形成有一 開口向上之第一容室（113)，並由該底面（112)向上凹陷形 成有一開口向下之第二容室（I14)，且於該頂面（111)及該 底面（112)上分別佈設有多數之銲墊（圖未示）及於該銲墊周 10 緣設有貫穿其頂底面（111)(112)之貫孔（115); 二晶片（12a)(12b)，係藉由環氣樹脂、矽樹脂、雙面膠 帶…等黏性材料（圖中未示）而分別黏著固定於該座體（11) 之第一容室（113)及第二容室（114)中，並利用打線技術， 藉由金屬銲線（121)分別與該座體（11)頂面（111)及底面（112) 15 之銲墊連接； 一遮蓋（13)，係可為不透明之塑膠、金屬或透明之破 璃、塑膠等材質所製成，用以封閉住該第一容室（113)之開 口，以保護置於該第一容室（113)内之晶片（12a)不受外力 破壞或雜物污染； 2〇 於此，當該構裝（10)欲組裝於一外界之電路板（14)上 時，如笫四圖所示，可藉由一銲錫（141)銜接於該座體（11) 之底面（112)上，並連通該座體（11)之貫孔（115)而可將該二 晶片（12a)(12b)藉由銲墊與該貫孔（115)電性連通於外部 者，使該電路板（14)上佈設之線路（圖未示）可與該二晶片 -5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） —訂------ is---------------------- (請先閱讀t面之注意事項再填寫本頁) A7 經濟部智慧財產局員工消費合作社印製 1249210 _____B7_____ 五、發明說明（） (l2a)(l2b)呈電性導通，而達成擁有二晶片（12a)(12b)運算 速度之功效，而僅需以該座體（11)分別位於上、下方之第 一、二容室（113)(114)容置該二晶片（12a)(12b)，即可進而 使該構裝（10)以佔有該電路板（14)上一座體（11)之面積，便 5 可達到擁有二晶片（12a)(12b)之運算處理速度，讓現今現 今高科技產業之訴求在此獲得解決之方法，且由於該笫一 晶片（12a)與該笫二晶片（12b)所連接之銲線（121)可以近乎 水平之方式而分別連接於該頂、底面（111)(112)上之銲 墊，使得該笫一、二容室（113)(114)内可不用供銲線(21)置 1〇 設或供打線器活動，而可將其容積相對縮減至與該笫一、 二晶片（12a)(12b)同寬及同高，而將整體構裝之面積及高 度均降低’並使得體積縮幅至最小。 請參閱笫五圖，係本發明笫二較佳實施例所提供之晶 片構裝結構（20)，主要包含有一座體（21)、二晶片 15 (22a)(22b)及一遮蓋（23);除了晶片構裝結構(20)外，笫五 圖中更揭露有一電路板(24);其與上述實施例之主要差異 在於： 該座體(21)之笫一容室（211)底部（212)，置設有較小體 積之晶片（22a)，因此使位於該笫一容室（211)中較小之晶 20片（22a)可以藉由金屬銲線（221)直接連接於該底部（212) 上’雖然’笫一容室（211)中之晶片（22&)之封裝體積並無 以縮減’但該笫二容室（222)中晶片（22b)之封裝體積仍能 縮減，而使整體封裝體仍為減小。 -6- (210 X 297 公釐） I — — — — — — — — — · 11 —11 --------I— — — — — — — —-- (請先閱讀t·面之•注意事項再填寫本頁) · - 1249210 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 請參閱笫六圖，係本發明笫三較佳實施例所提供之晶 片構裝結構（30)，主要包含有一座體（31)、二晶片 (32a)(32b)及一遮蓋（33);除了晶片構裝結構(30)外，笫六 圖中更揭露有一電路板（34);其與上述實施例之主要差異 5 在於： 該座體（31)笫一容室（311)之周緣，更形成有一階梯部 (312)，該階梯部（312)形成有一頂面（313)，該頂面（313)上 佈設有多數呈預定數量及態樣之銲墊（圖未示），使位於該 笫一容室（311)中之晶片（32a)可以藉由金屬銲線（321)電性 1〇連接於該頂面（313)上，且藉由各該貫孔（314)而與外部呈 電性連接。 藉由上述笫二、三較佳實施例之說明，本發明之重點 設計在於笫二容室之面積應以較大晶片之面積之設計基 準，並採用銲線與座體頂面連接之方式而縮減體積，至於 1 5 弟一谷▲中之晶片’可因晶片之大小而採取與座體頂面、 底面或階梯部之連接方式而不拘，甚至若晶片夠小，亦可 容納兩組晶片，如笫七圖所示笫四較佳實施例之晶片構裝 結構（50)，換言之，本發明僅需選擇其中一容室中之晶片 採銲線頂面連接，即可達成縮小體積之需求者；另外，必 20 需加以說明的是’本發明與電路板之連結可為笫一容室或 笫二容室者。 請參閱笫八圖，係本發明笫五較佳實施例所提供之晶 片構裝結構（40)，主要包含有一座體（41)、二晶片 (42a)(42b)以及一遮蓋(43)，除了晶片構裝結構(4〇)外，笫 (請先閱讀背面之一注意事項再填寫本頁) 適 度 尺 張 紙 本 釐 公 97 2 X ο 21 /V 格 規 4 )A S) N (C 準 標 家 國 國 I--l·---訂------— II 線—％----------------------- A7 1249210 B7____ 五、發明說明（） 八圖中更揭露有一電路板(44);其與上述實施例之主要差 異在於： 該晶片（42a)係為影像用晶片； 該遮蓋（43)具有一頂面（431)、一底面（432)以及一貫穿 5 該頂底面（431)(432)之穿孔（433)，該穿孔（433)中封設有至 少一鏡片（434)，藉此光線可透過該鏡片（434)照射於該晶 片（42a)上，使得此構裝之晶片（42a)可電性連接另一晶片 (42b)而獲得更多更怏之處理速度及容量。 另，為避免貴審查委員對本發明中晶片藉由銲線與座 1〇 體上所佈設之銲墊導通之方式產生疑慮，在此特別說明如 下； 一般當將該晶片置入於該容室内，並藉由銲線連接於 該座體上所佈設之銲墊後，會採用有二種方式將其晶片封 閉； I5 其一種係在該容室中鋪設一封膠而該晶片完全封閉， 而僅藉由銲線與容室外之座體銲墊連接，並再由一外界之 電路板或封蓋將銲線與銲墊直接壓合，而可將該晶片藉由 銲線與銲塾之連接而電性導通於外，並可封閉該容室以避 免容室内之晶片受到污染或破壞； 20 另一種則係在該容室之開口外連結一薄板或薄膜，並 使該薄板將該銲線壓合於該座體之銲墊上，並再藉由一鍚 骨（或鎮球)將該座體上之銲蟄連接於一外部之電路板或封 蓋上’而可間接藉由鍚膏將該晶片藉由銲線而電性導通於 該座體或外界之電路板上，並可封閉該容室以避免容室内 -8- 本紙張尺度適用中國國豕標準（CNS)A4規格（210 X 297公釐了 '"" " (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -·1111111-t-r口，a — — — — — — —— — — — — — — — — — — — — — — — — — — — — — — — A71249210 Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperative Printed A7 B7 V. Inventive Note (8) Figure 8 is a cross-sectional view of a preferred embodiment of the present invention. Please refer to FIG. 3 and FIG. 4 for a wafer structure (10) according to a preferred embodiment of the present invention, which mainly includes: a body (11), which can be plastic a circuit board integrally formed of a material such as plastic, glass 5 fiber or ceramics; and having a top surface (111) and a bottom surface (112), and the top surface of the top surface is recessed downward to form an opening upward The first chamber (113) is recessed upwardly from the bottom surface (112) to form a second chamber (I14) having an opening downward, and is disposed on the top surface (111) and the bottom surface (112), respectively. A plurality of pads (not shown) and a through hole (115) penetrating through the top bottom surface (111) (112) of the periphery of the pad 10; the second wafer (12a) (12b) is made of a ring gas a viscous material (not shown) such as a resin, a resin, a double-sided tape, or the like is adhered and fixed to the first chamber (113) and the second chamber (114) of the seat body (11), respectively, and utilized. The wire bonding technique is respectively connected to the pads of the top surface (111) and the bottom surface (112) 15 of the base body (11) by a metal bonding wire (121); a cover (13) can be opaque Made of plastic, metal or transparent glass, plastic, etc., to close the opening of the first chamber (113) to protect the wafer (12a) placed in the first chamber (113) Damaged by external force or contamination; 2. Here, when the structure (10) is to be assembled on an external circuit board (14), as shown in Fig. 4, it can be connected by a solder (141). The bottom surface (112) of the base body (11) communicates with the through hole (115) of the base body (11) to pass the two wafers (12a) (12b) through the bonding pad and the through hole (115). Electrically connected to the outside, so that the circuit (not shown) on the board (14) can be used with the two-chip-5-paper scale to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) —订------ is---------------------- (Please read the notes on t-face and then fill out this page) A7 Ministry of Economics Intellectual Property Bureau employee consumption cooperative printing 1249210 _____B7_____ V. Invention description () (l2a) (l2b) is electrically conductive, and achieves the effect of having the speed of the second chip (12a) (12b), and only needs to use the body (11 ) are located above and below The first and second chambers (113) (114) accommodate the two wafers (12a) (12b), so that the structure (10) can occupy the area of the body (11) on the circuit board (14). 5 can achieve the processing speed of having two chips (12a) (12b), so that the current high-tech industry's appeal can be solved here, and because the first chip (12a) and the second chip (12b) The connected bonding wires (121) can be connected to the pads on the top and bottom surfaces (111) (112) in a nearly horizontal manner, so that the first and second chambers (113) (114) are not provided. The wire (21) is set or provided for the action of the wire cutter, and the volume thereof can be relatively reduced to the same width and height as the first and second chips (12a) (12b), and the overall structure area and The height is reduced by 'and the volume is reduced to a minimum. Referring to FIG. 5, a wafer structure (20) according to a second preferred embodiment of the present invention mainly includes a body (21), two wafers 15 (22a) (22b) and a cover (23). In addition to the wafer structure (20), a circuit board (24) is further disclosed in the fifth drawing; the main difference from the above embodiment is: the bottom of the chamber (211) of the body (21) ( 212), a smaller volume of the wafer (22a) is disposed, so that the smaller 20 pieces (22a) located in the first chamber (211) can be directly connected to the bottom by the metal bonding wire (221). (212) The package volume of the wafer (22&) in the 'well' chamber (211) is not reduced, but the package volume of the wafer (22b) in the second chamber (222) can still be reduced. The overall package is still reduced. -6- (210 X 297 mm) I — — — — — — — — 11 —11 --------I — — — — — — — — — (Please read t·面 first • Note: Please fill out this page) · - 1249210 A7 B7 Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperative Printed 5, Invention Description () Please refer to Figure 6 for the wafer structure provided by the third preferred embodiment of the present invention. The mounting structure (30) mainly comprises a body (31), two chips (32a) (32b) and a cover (33); in addition to the wafer structure (30), a circuit board is further disclosed in the sixth figure ( 34); the main difference between the embodiment and the above embodiment is that: the seat body (31) is formed on a periphery of the chamber (311), and further has a step portion (312) formed with a top surface (312) 313), the top surface (313) is provided with a plurality of pads (not shown) of a predetermined number and state, so that the wafer (32a) located in the first chamber (311) can be made of metal bonding wires. (321) The electrical one is connected to the top surface (313), and is electrically connected to the outside through each of the through holes (314). With the above description of the second and third preferred embodiments, the key design of the present invention is that the area of the second chamber should be based on the design of the area of the larger wafer, and the bonding line is connected to the top surface of the housing. Reducing the volume, as for the wafer in the 1st 一 谷 谷 ▲ can be connected to the top, bottom or step of the seat due to the size of the wafer, even if the wafer is small enough to accommodate two sets of wafers, The wafer structure (50) of the fourth preferred embodiment is shown in FIG. 7, in other words, the invention only needs to select the top surface of the wafer bonding wire in one of the chambers to achieve the required volume reduction. In addition, it must be noted that 'the connection between the present invention and the circuit board can be a room or a second room. Referring to FIG. 8, a wafer structure (40) according to a fifth preferred embodiment of the present invention mainly includes a body (41), two chips (42a) (42b), and a cover (43). In addition to the wafer structure (4〇), 笫 (please read one of the notes on the back and fill out this page). Moderate ruler paper PCT 97 2 X ο 21 /V Grid 4) AS) N (C Standard Country I--l·---订———— II Line—%----------------------- A7 1249210 B7____ V. Description of the Invention (8) A circuit board (44) is further disclosed in FIG. 8; the main difference from the above embodiment is that the wafer (42a) is an image wafer; the cover (43) has a top surface (431). a bottom surface (432) and a through hole (433) penetrating through the top surface (431) (432), wherein the through hole (433) is sealed with at least one lens (434) through which light is transmitted ( 434) illuminating the wafer (42a) so that the wafer (42a) of the package can be electrically connected to another wafer (42b) to obtain more processing speed and capacity. In the invention, the wafer is bonded by wire bonding The method of turning on the solder pads disposed on the body is suspected, and is specifically described below. Generally, when the wafer is placed in the chamber and connected to the pads disposed on the body by bonding wires, There will be two ways to close the wafer; I5 one of them is to lay a glue in the chamber and the wafer is completely closed, but only by the wire bonding with the seat pad of the outdoor chamber, and then An external circuit board or cover directly presses the bonding wire and the bonding pad, and the wafer can be electrically connected to the outside by the connection of the bonding wire and the bonding wire, and the cavity can be closed to avoid the interior of the cavity. The wafer is contaminated or destroyed; 20 the other is to connect a thin plate or film outside the opening of the chamber, and the thin plate is pressed against the soldering pad of the base body, and then by a tibia ( Or ball ball) connecting the solder bump on the body to an external circuit board or cover', and indirectly electrically connecting the wafer to the circuit or the external circuit by means of a bonding wire by using a solder paste On the board, and can close the chamber to avoid the room -8- The paper size is applicable to China豕Standard (CNS) A4 specification (210 X 297 mm '""" (Please read the note on the back and fill out this page) Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing -1111111-tr , a — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
1249210 五、發明說明（） 之晶片受到污染或破壞者，且由於該鎖膏之高度係高於該 薄板之咼度，而不致影響或干涉整體構裝時之品質。 综上所述，本發明之晶片構裝結構，確實具有在電路 板上佔用最小之面積而達到多晶片之處理效果優點，實具 5其進步實用性，且在使用上之方便，又，本發明於申請前 並無相同物品見於刊物或公開使用，是以，本發明實已具 備發明專利要件，為保障發明人之苦思，爰依法提出申 請。 惟，以上所述者，僅為本發明之較佳可行實施例而 1〇 已，故舉凡應用本發明說明書及申請專利範圍所為之等效 結構變化，理應包含在本發明之專利範圍内。 ----1!!!""· 1!^· I! I ---訂----線 I (請先閱讀f·面之注意事項再填寫本I·} 經濟部智慧財產局員工消費合作社印製 冬 本紙張尺度適用中家標準（CNS)A4規格（210 X 297公釐） — -s〜1249210 5. The wafer of the invention () is contaminated or destroyed, and since the height of the lock is higher than the thickness of the sheet, it does not affect or interfere with the quality of the overall assembly. In summary, the wafer structure of the present invention does have the advantage of occupying the smallest area on the circuit board to achieve the processing effect of the multi-chip, and the utility model has the advantages of progress and practicality, and is convenient in use, and The invention does not have the same items in the publication or public use before the application. Therefore, the invention has the invention patent requirements, and in order to protect the inventor's hard thinking, the application is made according to law. However, the above-mentioned embodiments are only the preferred embodiments of the present invention, and the equivalent structural changes of the present invention and the scope of the claims are intended to be included in the scope of the present invention. ----1!!!""· 1!^· I! I ---Book----Line I (Please read the precautions of f·face and then fill in this I·} Ministry of Economics intellectual property Bureau employee consumption cooperative printed winter paper size applicable to the National Standard (CNS) A4 specification (210 X 297 mm) — -s~
I 1249210 A7 B7 五、發明說明（ 簡單圖示說明： 笫一圖係一種習用晶片構裝之剖視圖。 笫二圖係一種習用多晶片之模組構裝剖視圖。 笫三圖係本發明笫一較佳實施例之剖視圖。 笫四圖係本發明笫一較佳實施例之使用狀態剖視圖 笫五圖係本發明笫二較佳實施例之剖視圖。 笫六圖係本發明笫三較佳實施例之剖視圖。 笫七圖係本發明笫四較佳實施例之剖視圖。 笫八圖係本發明笫五較佳實施例之剖視圖。 10 請 先 閱 讀 背. 面 之 注 意 事 項 再 填 i I Ψ 頁 15 圖號說明： 「笫一較佳實施例 晶片構裝結構（10) 頂面（111) 第一容室（113) 晶片（12a)(12b) 遮蓋（13) 銲鍚（141) 座體（11) 底面（112) 第二容室（114) 金屬銲線（121) 外界電路板（14) 貫孔（115) 訂 經濟部智慧財產局員工消費合作社印製 20 「笫二較佳實施例 晶片構裝結構(20) 座體(21) 遮蓋(23) 底部（212) 晶片（22a)(22b) 笫一容室(211) 金屬銲線(221) 10- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1249210 A7 B7 五、發明說明（） 電路板(24) 笫二容室(222) 「笫三較佳實施例 晶片構裝結構(30) 晶片（32a)(32b) 笫一容室（311) 頂面（313) 電路板(34) 座體(31) 遮蓋（33) 階梯部（312) 金屬銲線(321) 貫孔（314) 10 「笫四較佳實施例 晶片構裝結構(50) 「笫五較佳實施例 晶片構裝結構(40) 15 晶片（42a)(42b) 頂面（431) 穿孔(433) 電路板(44) 座體(41) 遮蓋(43) 底面（432) 鏡片（434) --------^---------^ I (請先閱讀f*面之·注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）I 1249210 A7 B7 V. BRIEF DESCRIPTION OF THE INVENTION (Simplified illustration: Figure 1 is a cross-sectional view of a conventional wafer assembly. Figure 2 is a cross-sectional view of a conventional multi-chip module assembly. Figure 3 is a comparison of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 4 is a cross-sectional view showing a preferred embodiment of the present invention. FIG. 5 is a cross-sectional view of a preferred embodiment of the present invention. FIG. 6 is a third preferred embodiment of the present invention. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 No. Description: "The preferred embodiment wafer structure (10) top surface (111) first chamber (113) wafer (12a) (12b) cover (13) solder (141) body (11) Bottom surface (112) Second chamber (114) Metal wire (121) External circuit board (14) Through hole (115) Printed by Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed 20 "Second embodiment of the preferred wafer assembly Structure (20) Seat (21) Cover (23) Bottom (212) Wafer 22a)(22b) 笫一室(211) Metal wire (221) 10- This paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm) 1249210 A7 B7 V. Invention description () Circuit board (24) 笫二容室(222) "笫三优选实施例 wafer structuring structure (30) wafer (32a) (32b) 笫 a chamber (311) top surface (313) circuit board (34) (31) Cover (33) Step (312) Metal bond wire (321) Through hole (314) 10 "Four preferred embodiment wafer structure (50) "Five preferred embodiment wafer structure ( 40) 15 Wafer (42a) (42b) Top surface (431) Perforation (433) Circuit board (44) Seat (41) Cover (43) Bottom (432) Lens (434) --------^ ---------^ I (Please read the f* surface and precautions and fill out this page.) Ministry of Economic Affairs, Intellectual Property Bureau, Staff and Consumer Cooperatives, Printed Paper Scale Applicable to China National Standard (CNS) A4 Specification ( 210 X 297 mm)