396571 A7 五、發明說明（ 上方’並藉由焊線耦合到基板導線上。第二晶圓 物貼合在第一晶圓的下層表面。第一與第二晶圓 體電路、微處理器或晶片中之一，第二晶圓藉由接 以電子耦合到基板上的基板導線。第一晶圓與基 使用封膠封住，散熱片能選擇性地裝設於封膠中 圓所產生的熱，另一封膠填滿於穿孔並覆蓋在第 接合焊線上，複數個的焊接錫珠（s〇lder balls)以電 刷電路板（PCB)，並固定在基板上。更佳地，焊接錫 balls)以矩陣型式配置，焊接錫珠（s〇lder balls)以 到印刷電路板（PCB)，以便構成熱與電性的連接。 以環氧化 可以為積 合焊線， 板的部分 以散開晶 一晶圓、 性連接印 珠（solder 電性連接 本發明的 經濟部智慧財產局員工消費合作社印製 另一個例子亦可使用一傳導平板，如在第一與第二晶圓間 | 5 加一金屬板，此傳導平板由銅所組成。 根據本發明的第三實施例，本發明包含一多層 除最上一層外，孔洞分別地形成在基板層中，並從 的下一層擴展到最低層。孔洞的形成組合成一模穴 導線（conductive traces)則形成在多層基板的表面上 晶圓貼合在多層基板的最高一層的上表面，並使用 線連接基板導線。第二晶圓被接收在模穴中，並貼 板的最高層的表面底部，同樣地，第二晶圓使用接 連接在基板上的基板導線。封膠覆蓋第一晶圓與基板的 部分，以防止晶圓與接合焊線因水氣或外力之影響 熱片可以選擇地設置在多層基板的上方以達到散 能’ 一罩蓋貼合在多層基板的表面下方。另外，封 模穴，焊接錫珠（solder balls)被配置在多層基板的 訂 第一 接合焊 合在基 合焊線 一散 熱的功 膠填滿 最下表 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 396571 A7 B7 五、發明說明（） 面，用以傳遞外部單元 圖式ffi簞說明： 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述： 第1圖為傳統球腳格狀陣列（baU gri(i array)封裝之截 面圖。 第2圖為另一傳統球腳格狀陣列（baU grid array)封裝 之截面圖。 第3圖為依據本發明之第一實施例之球腳格狀陣列 (ball grid array)封裝之截面圖。 第4圖為依據本發明之第二實施例之球腳格狀陣列 (ball grid array)封裝之截面圖。 第5圖為依據本發明之第三實施例之球腳格狀陣列 (ball grid array)封裝之截面圖。 (請先閱讀背面之注意事項再填寫本頁) 0 經濟部智慧財產局員工消費合作社印製 發明详細說明： 本發明之實施例，現將以參考圖式作詳盡的描述。 根據第3圖到第5圖的說明，本發明之特色是在於能 夠承載多個半導體晶圓於元件上。第3圖為依據:發明: 第一實施例之封裝300之戴面圖。半導體封裝3〇〇包含一 基板302，在基板302中心部分附近形成—穿孔3〇4。基板 302有第一主要的表面3〇2a與第二主要的表面3〇2b，第一 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 線 396571 A7 --- B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 主要的表面302a指的是基板上表面，第二主要的表面302b 指的是基板下表面。基板以傳統的製程製造，基板302所 使用的材質像 polyimide，triazine，phenolic resin 或 bismaleimidetriazine(BT)，當然任何適合的材質皆可用於 製作基板302。 請參閱第3圖，第一半導體晶圓306固定在晶圓承載 區域，使用非傳導貼合材質3 0 8，像膠帶、黏膠之類的材 質，貼合於基板3 00之上表面（第一主要的表面）3 02a。第一 晶圓為一積體電路（1C)、微處理器或晶片，更佳地，第一 半導體晶圓306精確地覆蓋在穿孔304上方，使用傳統的 焊線接合技術，第一半導體晶圓306的正面經由傳導線（接 合焊線）310耦合到基板302上的基板導線（圖未顯示），此 外，接合焊線3 1 0以金或合金製成較佳。基板導線典型地 形成在基板302的頂端或底部，以提供外部信號電性連接 路徑。另外，在很多例子中，基板導線形成在基板3 02中。 第二半導體晶圓3 1 2以環氧化物3 1 4貼合在第一半導體晶 圓306之下表面，使第二半導體晶圓正面朝下。同樣地， 第二半導體晶圓312亦可從積體電路（1C)、微處理器或晶 片中擇一。第二半導體晶圓312的正面經由接合焊線310 透過穿孔304耦合到基板302上的基板導線，值得一提的 是第二晶圓3 1 2被接收在基板3 0 2上的穿孔3 0 4。 第一晶圓306與基板302的第一主要表面302a的部 分，利用封膠3 1 6封住以保護晶圓3 0 6。散熱片3 1 8可以 選擇性地放置於封膠3 1 6中以散開晶圓所產生的熱，散熱 請 先 閱 讀 背 © 之 注 意 事 項 再 填:: 寫乂 本 頁 訂 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 五、發明說明（） = 318的表面上方可以暴露以增加散熱效率。另外液態封 膠320亦填滿穿孔304並霜甚笛一 θ I復盍第一晶圓312與接合焊線 3Η)，液態封膠320所佔用的區域依在基板3〇2的第二主要 表面302b(表面的底部）上之液態封膠堤（dam)32i所決定， 複數個焊接錫珠（或焊接錫塊）322以電性連接至—印刷電 路板（在圖中未顯示），並固定在基板3()2的第二主要表面 3 02b &佳地，知接錫珠以矩陣的形式配置，典型地，焊 接錫珠322連接一印刷電路板，以便配置熱與電性的連 接。晶BM吏用接合焊、線3 10《其他熟知的搞合方式，如翻 轉aa片的方法，以電子耦合基板導線，亦即，接合焊線3 ^ 〇 的一端連接到晶圓，接合焊線3 1〇的另一端經由基板導線 連接到基板的焊接錫珠322。例如，焊接錫珠322能以球 腳格狀陣列（BGA)技術形成，焊接錫珠322的組成，可以適 當地選擇共熔的焊錫，包含37%的鉛與63%的錫。 第4圖為本發明的另一實施例示意圖，亦可在第一晶 圓306與第二晶圓3 12間使用一傳導平板，如金屬或合金 平板’較佳地，傳導平板4〇2是以銅製成，詳細地說，傳 導平板402以膠帶或黏膠黏附在基板3〇2的第一主要表面 3 02a ,並配置在穿孔304上。第一晶圓306與第二晶圓312 各分別地固定在傳導平板402的二面，其餘的構件與要素 與第一實施例相似，因此，省略詳細描述。 第5圖為依據本發明之第三實施例，此元件為一多晶 圓模組，包含一多層基板5〇〇，多層基板5 00的每一層， 除了最高一層以外，在中心部分附近形成一孔洞，這些孔 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 396571 A7 B7 五、發明說明（ 洞刀別地形成於基板500的各層，並從最高一層的下方到 最低一層逐漸擴大，並洞組合成一模穴5〇2。基板導線（圖 未顯示）形成在多層基板500的表面，第一晶圓5〇4以膠帶 或黏膠黏附在多層基板500最高一層表面的上方，並用接 合焊線506以電性連接基板導線。所有本發明的實施例更 包含在基板表面的接觸墊，並以電性直接連接或經由導通 孔到基板導線。第二晶圓5 0 8被承載在模穴5 〇 2中，並以 膠帶或黏膠黏附在基板500最低一層表面的底部，同樣 地’第一晶圓508的正面亦使用接合焊線506,透過模穴 5 02 ’以電性連接在基板上的基板導線。接合焊線5〇6以金 線製成為較佳，封膠510覆蓋第一晶圓502與基板5〇()的 一部分，以防止晶圓502與接合焊線506因水氣或外力之 影響。散熱片5 1 2可選擇性地配置在多層基板5 〇 〇的頂端 以達到散熱的效果，罩蓋5 1 4像金屬或類似之結構貼合在 多層基板500表面的下方，罩蓋514，基板500與第二晶 圓5 0 8間以另一封膠5 1 6填滿模穴5 0 6中，焊接錫珠5 1 8 被配置在多層基板500的最下表面，以傳遞外部單元。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。 請 先 閱 讀 背 之 注 項 再 填 寫 本 頁 經濟部智慧財產局員工消費合作社印製 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 396571 调396571 A7 5. Description of the invention (above 'and coupled to the substrate wires by bonding wires. The second wafer is attached to the lower surface of the first wafer. The first and second wafer body circuits, microprocessors or One of the wafers, the second wafer is electronically coupled to the substrate wires on the substrate. The first wafer and the substrate are sealed with a sealant, and the heat sink can be selectively installed in the sealant. Heat, another sealant fills the perforation and covers the bonding wire, and a plurality of solder balls are brushed on the circuit board (PCB) and fixed on the substrate. Better, solder Tin balls) are arranged in a matrix type, and solder balls are soldered to a printed circuit board (PCB) to form a thermal and electrical connection. The epoxidation can be used as an integrated welding wire, and the part of the board is printed with a wafer and a sexual connection printed on the beads (solder is electrically connected to the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economics of the invention. A flat plate, such as a metal plate between the first and second wafers, and the conductive plate is made of copper. According to a third embodiment of the present invention, the present invention includes a plurality of layers except for the top layer, the holes are separately It is formed in the substrate layer and extends from the next layer to the lowest layer. The formation of holes forms a conductive traces formed on the surface of the multilayer substrate. The wafer is bonded to the upper surface of the highest layer of the multilayer substrate. The second wafer is received in the cavity, and the top surface of the board is attached to the bottom. Similarly, the second wafer uses the substrate wire connected to the substrate. The sealant covers the first The part of the wafer and the substrate to prevent the wafer and the bonding wire from being affected by moisture or external forces. The heat piece can be optionally placed above the multilayer substrate to achieve the dissipation of energy. Below the surface of the multi-layer substrate. In addition, the mold cavity and solder balls are arranged on the multi-layer substrate. The first joint is welded to the base bond wire. Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 396571 A7 B7 V. Description of the invention () Surface, used to communicate the external unit diagram Description: The preferred embodiment of the present invention will be in the future The description is supplemented by the following figures for a more detailed explanation: Figure 1 is a cross-sectional view of a traditional ball-foot grid array (baU gri (i array) package. Figure 2 is another traditional ball-foot grid array (baU grid) cross-sectional view of an array) package. FIG. 3 is a cross-sectional view of a ball grid array package according to a first embodiment of the present invention. FIG. 4 is a ball-foot array according to a second embodiment of the present invention. Sectional view of a ball grid array package. Figure 5 is a sectional view of a ball grid array package according to a third embodiment of the present invention. (Please read the precautions on the back before reading (Fill in this page) 0 Ministry of Economic Affairs Intellectual Property Detailed description of the invention printed by the Bureau ’s consumer cooperative: The embodiments of the present invention will now be described in detail with reference to the drawings. According to the description of Figures 3 to 5, the invention is characterized by being capable of carrying multiple semiconductors The wafer is on the element. The third figure is based on: Invention: The top view of the package 300 of the first embodiment. The semiconductor package 300 includes a substrate 302 formed near the center portion of the substrate 302—a through hole 304. The substrate 302 has the first major surface 3202a and the second major surface 3202b. The first paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Line 396571 A7 --- B7 Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperatives V. Invention Description (The main surface 302a refers to the upper surface of the substrate, and the second main surface 302b refers to the lower surface of the substrate. The substrate is manufactured using a conventional manufacturing process. The material used for the substrate 302 is polyimide, triazine, phenolic resin, or bismaleimidetriazine (BT). Of course, any suitable material can be used to make the substrate 302. Referring to FIG. 3, the first semiconductor wafer 306 is fixed in the wafer carrying area, and a non-conductive bonding material 3 0 8 is used, and a material such as tape or adhesive is bonded to the upper surface of the substrate 3 (the A major surface) 3 02a. The first wafer is an integrated circuit (1C), a microprocessor, or a wafer. More preferably, the first semiconductor wafer 306 is accurately covered over the through hole 304. Using conventional wire bonding technology, the first semiconductor wafer The front side of 306 is coupled to a substrate wire (not shown) on the substrate 302 via a conductive wire (bonding wire) 310. In addition, the bonding wire 3 10 is preferably made of gold or an alloy. The substrate wires are typically formed on the top or bottom of the substrate 302 to provide an external signal electrical connection path. In addition, in many examples, a substrate wire is formed in the substrate 302. The second semiconductor wafer 3 1 2 is bonded to the lower surface of the first semiconductor wafer 306 with an epoxide 3 1 4 so that the front surface of the second semiconductor wafer faces downward. Similarly, the second semiconductor wafer 312 may be selected from an integrated circuit (1C), a microprocessor, or a wafer. The front side of the second semiconductor wafer 312 is coupled to the substrate wire on the substrate 302 through the through-hole 304 through the bonding wire 310. It is worth mentioning that the second wafer 3 1 2 is received in the through-hole 3 0 2 on the substrate 3 0 2 . The first wafer 306 and the portion of the first main surface 302a of the substrate 302 are sealed with a sealant 3 1 6 to protect the wafer 3 06. The heat sink 3 1 8 can be selectively placed in the sealant 3 1 6 to dissipate the heat generated by the wafer. Please read the precautions of the back © before filling it. Standard (CNS) A4 specification (210 X 297 mm) 5. Description of the invention () = 318 can be exposed above the surface to increase heat dissipation efficiency. In addition, the liquid sealant 320 also fills the perforations 304 and frosts θ I (the first wafer 312 and the bonding wire 3Η). The area occupied by the liquid sealant 320 depends on the second major surface of the substrate 30 The liquid sealing dam 32i on 302b (bottom of the surface) determines that a plurality of solder beads (or solder blocks) 322 are electrically connected to a printed circuit board (not shown in the figure) and fixed On the second main surface 3 02b of the substrate 3 () 2, it is known that the solder balls are arranged in a matrix form. Typically, the solder balls 322 are connected to a printed circuit board in order to configure a thermal and electrical connection. Crystal BM uses bond bonding, wire 3 10 "Other well-known methods, such as flipping the aa chip, to electronically couple the substrate wires, that is, one end of the bonding bond wire 3 ^ 〇 is connected to the wafer, bonding bond wire The other end of 3 10 is connected to a solder ball 322 of the substrate via a substrate wire. For example, the solder balls 322 can be formed by ball-to-pin grid array (BGA) technology. The composition of the solder balls 322 can be selected by eutectic solder, which contains 37% lead and 63% tin. FIG. 4 is a schematic diagram of another embodiment of the present invention. A conductive plate, such as a metal or alloy plate, may also be used between the first wafer 306 and the second wafer 312. Preferably, the conductive plate 402 is It is made of copper. In detail, the conductive flat plate 402 is adhered to the first main surface 302a of the substrate 302 with tape or adhesive, and is disposed on the perforation 304. The first wafer 306 and the second wafer 312 are respectively fixed on the two sides of the conductive flat plate 402, and the remaining components and elements are similar to those of the first embodiment, and thus detailed descriptions are omitted. FIG. 5 is a third embodiment of the present invention. This component is a multi-wafer module including a multi-layer substrate 500, and each layer of the multi-layer substrate 500 is formed near the center portion except the highest layer. One hole, these holes are in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm) 396571 A7 B7 V. Description of the invention (holes are formed in each layer of the substrate 500 separately from the bottom of the highest layer to The lowest layer is gradually enlarged, and the holes are combined into a cavity 50. The substrate wire (not shown) is formed on the surface of the multilayer substrate 500. The first wafer 504 is adhered to the surface of the highest layer of the multilayer substrate 500 with tape or adhesive. And the bonding wires 506 are used to electrically connect the substrate wires. All the embodiments of the present invention further include contact pads on the substrate surface, and are directly connected to the substrate wires electrically or via the vias. The second wafer 50 0 8 is carried in the cavity 502, and is adhered to the bottom of the lowest layer surface of the substrate 500 with tape or adhesive. Similarly, 'the front side of the first wafer 508 also uses the bonding wire 506 and passes through the cavity 5 02' A substrate wire electrically connected to the substrate. The bonding wire 506 is preferably made of a gold wire, and the sealant 510 covers a portion of the first wafer 502 and the substrate 50 () to prevent the wafer 502 from bonding. The bonding wire 506 is affected by water vapor or external force. The heat sink 5 1 2 can be selectively arranged on the top of the multilayer substrate 5000 to achieve the effect of heat dissipation. The cover 5 1 4 is bonded to the multilayer like a metal or similar structure. Below the surface of the substrate 500, a cover 514, the substrate 500 and the second wafer 508 are filled with another sealant 5 1 6 in the mold cavity 5 06, and solder beads 5 1 8 are arranged on the multilayer substrate 500 The lowermost surface is used to pass the external unit. The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other things that are completed without departing from the spirit disclosed by the present invention Changes or modifications should be included in the scope of patent application below. Please read the note below and fill in this page. Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economy. (210 X 297 mm) 396571 Tune
多晶圓半導《封裝 發明摘要： 本封裝包含具有一穿孔的基板，第一個晶圓固定在基 板的上表面，第二個晶圓靠環氧化物貼合在第一個晶圓的 下表面，第一個晶圓以封膠封住，複數個焊接錫珠（s〇lder balls)固定在基板以配置熱與電性的連接，亦可在第一與第 二個晶圓中使用一傳導性的金屬板，另外一實施例，包含 一多層基板。孔洞分別地形成在基板層，並從最高層的下 方擴展到最低層。第一晶圓貼合在多層基板的最高一層的 上表面，並使用接合焊線連接基板導線。第二晶圓貼合在 多層基板的最低一層的下表面，封膠覆蓋在第一晶圓，並 且罩蓋貼合在多層基板的最下表面，焊接錫珠（solder balls) 被配置在多層基板的最下表面，以傳遞外部單元。 英文發明摘要（發明之名稱： — -τι; Ή裝丨 (請先閲讀背面之注意事項再填寫本頁各欄) 線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（2!〇χ297公釐） 5 6 9 3Multi-Wafer Semiconductor Package Abstract: This package contains a substrate with a perforation. The first wafer is fixed on the top surface of the substrate, and the second wafer is bonded to the bottom of the first wafer by epoxy. On the surface, the first wafer is sealed with a sealant, and a plurality of solder balls are fixed on the substrate to configure thermal and electrical connections. One can also be used in the first and second wafers. A conductive metal plate, in another embodiment, includes a multilayer substrate. The holes are formed in the substrate layer, respectively, and extend from below the highest layer to the lowest layer. The first wafer is bonded to the upper surface of the highest layer of the multilayer substrate, and the bonding wires are used to connect the substrate wires. The second wafer is bonded to the lower surface of the lowest layer of the multilayer substrate, the sealant covers the first wafer, and the cover is bonded to the lower surface of the multilayer substrate. Solder balls are arranged on the multilayer substrate. The lowermost surface to pass the external unit. Abstract of the invention in English (Name of the invention: — -τι; Ή 装 丨 (Please read the notes on the back before filling out the columns on this page) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Online Economics ) Α4 size (2! 〇χ297 mm) 5 6 9 3
A8SS 六 中 圍園範範專專 請复 (請先閱讀背面之注意事項再填寫本頁) 1 · 一種半導體封裝之結構，該結構至少包含： 基板’該基板具有第一與第二表面，並有一穿孔形成於 其中； 第一半導體晶圓’該第一半導體晶圓形成在基板的該第一 表面，並位於該穿孔上方； 第二半導體晶圓，該第二半導體晶圓貼附在該第一半導體 晶圓之下表面，使該第二半導體晶圓正面朝下，並位於該 穿孔中； 焊接錫塊，經由多數的接合焊線耦合到該第一半導體晶圓 的正面與透過該穿孔耦合到該第二半導體晶圓的正面，並 配置在該基板的該第二表面；及 第一遮蓋物，覆蓋在該基板的該第一表面，用以保護該第 一半導體晶圓；以及 第二遮蓋物’覆蓋在該基板的該第二表面，用以保護該第 二半導體晶圓。 2.如申請專利範圍第1項之結構，其中上述之第一半導體 晶圓係使用膠帶或黏膠，以形成在基板上。 經濟部智慧財產局員工消費合作社印製 3·如申請專利範圍第1項之結構，更包含一散熱片，形成 在上述之基板的第一表面，以達到散熱功效。 4·如申請專利範圍第1項之結構，其中上述之第二半導體 晶圓使用環氧化物以貼合在第一半導體晶圓表面的下方。 5·如申請專利範圍第1項之結構，其中上述之第一遮蓋物 包含一封膠。 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）A8SS Liuzhong Fanyuan Fanfan specifically (please read the precautions on the back before filling out this page) 1 · A semiconductor package structure, the structure includes at least: the substrate 'the substrate has first and second surfaces, and A through hole is formed in the first semiconductor wafer. The first semiconductor wafer is formed on the first surface of the substrate and is located above the through hole. The second semiconductor wafer is attached to the first semiconductor wafer. A lower surface of a semiconductor wafer, with the second semiconductor wafer facing down and located in the through hole; a solder bump is coupled to the front surface of the first semiconductor wafer through a plurality of bonding wires and is coupled through the through hole To the front surface of the second semiconductor wafer and disposed on the second surface of the substrate; and a first cover covering the first surface of the substrate to protect the first semiconductor wafer; and a second A cover 'covers the second surface of the substrate to protect the second semiconductor wafer. 2. The structure according to item 1 of the scope of patent application, wherein the first semiconductor wafer described above is formed on a substrate using tape or adhesive. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 3. If the structure in the scope of patent application No. 1 includes a heat sink, it is formed on the first surface of the substrate to achieve heat dissipation. 4. The structure according to item 1 of the scope of patent application, wherein the second semiconductor wafer described above uses an epoxide to adhere below the surface of the first semiconductor wafer. 5. The structure according to item 1 of the scope of the patent application, wherein the above-mentioned first covering includes a piece of glue. 9 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)