TW504809B - Chip package with reduced stress - Google Patents

Chip package with reduced stress Download PDF

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Publication number
TW504809B
TW504809B TW090124246A TW90124246A TW504809B TW 504809 B TW504809 B TW 504809B TW 090124246 A TW090124246 A TW 090124246A TW 90124246 A TW90124246 A TW 90124246A TW 504809 B TW504809 B TW 504809B
Authority
TW
Taiwan
Prior art keywords
wafer
stress
patent application
scope
reduced
Prior art date
Application number
TW090124246A
Other languages
Chinese (zh)
Inventor
Cheng-Jiau Wu
Original Assignee
Taiwan Electronic Packaging Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Electronic Packaging Co filed Critical Taiwan Electronic Packaging Co
Priority to TW090124246A priority Critical patent/TW504809B/en
Application granted granted Critical
Publication of TW504809B publication Critical patent/TW504809B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

A chip package with reduce stress is provided, which comprises: an accommodation body; a substrate, adhered with the accommodation body and formed as a chamber with an upward opening between the accommodation body and the substrate; a chip adhered on the substrate and electrically connected to the accommodation body by a plurality of welding lines, in which the thermal expansion coefficient of the substrate is close to that of the chip; and, a mask which is covered on the accommodation body and against to the opening of the chamber, so as to prevent the damage by the external force or the pollution by the articles on the chip in the chamber.

Description

504809 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（） 本發明係與晶片構裝有關，更詳而言之是指一種可減 低應力之晶片構裝。 一般習知之晶片構裝（1)，如笫一圖所示，其具有一載 體（2)，該載體（2)具有一頂面（2a)及一底面（2b)，且自該頂 5 面（2a)處向下凹陷而形成有一開口向上之容室（2c); —積 體電路晶片（3)，係置設於該載體（2)容室（2c)之底部（2d) 上，並藉由多數之銲線（4)將其電性傳導於該載體（2)上， 而可藉由該載體（2)與外界連接，進而將該晶片（3)之電性 導通於外界者；此外，該載體(2)之頂面（2a)上更罩設有一 1〇 封蓋（5)，係用以封閉該容室（2a)之開口，使該晶片（3)可不 受外力之破壞或污染者。 惟，該載體(2)—般係為塑膠、玻璃纖維或陶瓷等材質 中之一種所製成，而該晶片（3)則係由矽元素所製成；由於 此兩種材質之不同，將使得該載體（2)之熱膨脹係數（19 X 15 10’遠高於該晶片（3)之熱膨脹係數(4 X10_6)，使該構裝（1) 在進行模壓或運作之同時，該載體(2)極易遭受周遭環境溫 度改變之影響，使得整個晶片構裝（1)產生熱脹冷縮之物理 現象，然而該晶片（3)與該載體（2)之熱膨脹係數在相差有 四倍之餘下，會有發生類似Bimetal(雙金屬）撓曲或變形之 2〇 情形，並進而將其應力導向於該晶片（3)上，使該晶片（3) 會因所承受之應力過度或受力不均，而有發生撓曲或破裂 之情事。 (請先閲讀背面之注意事嗔再填頁) •裝·504809 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention () This invention is related to wafer fabrication. More specifically, it refers to a wafer fabrication that reduces stress. Generally known wafer structure (1), as shown in the first figure, it has a carrier (2), the carrier (2) has a top surface (2a) and a bottom surface (2b), and from the top 5 surfaces (2a) is recessed downward to form a container chamber (2c) with an opening upward;-an integrated circuit wafer (3), which is arranged on the bottom (2d) of the container (2) container chamber (2c), and The majority of the bonding wires (4) are electrically conductive to the carrier (2), and the carrier (2) can be connected to the outside, thereby electrically connecting the chip (3) to the outside; In addition, a top cover (5) is provided on the top surface (2a) of the carrier (2), which is used to close the opening of the chamber (2a) so that the wafer (3) can not be damaged by external forces. Or polluters. However, the carrier (2) is generally made of one of materials such as plastic, fiberglass or ceramic, and the chip (3) is made of silicon; due to the difference between the two materials, The thermal expansion coefficient (19 X 15 10 'of the carrier (2) is much higher than the thermal expansion coefficient (4 X10_6) of the wafer (3), so that the carrier (2) is molded or operated while the carrier (2) It is very susceptible to the impact of changes in the ambient temperature, which makes the entire wafer structure (1) produce a physical phenomenon of thermal expansion and contraction. However, the thermal expansion coefficient of the wafer (3) and the carrier (2) differ by more than four times. There will be a situation similar to Bimetal's deflection or deformation, and the stress will be directed on the wafer (3), so that the wafer (3) will be overstressed or unevenly stressed due to the stress it is subjected to. However, there may be cases of deflection or cracking. (Please read the precautions on the reverse side before filling in the pages)

、1T 線 • ................................ 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 504809 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（） 有鑑於上述之種種缺失，本案發明人乃經詳思細索， 並累積多年從事晶片構裝製造及研究開發之經驗，終而有 本發明之產生。 亦即本發明之主要目的乃在提供一種可減低應力之晶 5 片構裝，係可使該晶片減低所受之應力或使其受力均勻， 而減少發生損壞之情形者。 緣此，本發明所提供一種可減低應力之晶片構裝，其 主要包含有：一容置體；一載板，係與該容置體黏結，並 使該容置體與該載板間形成有一開口向上之容室；一晶 10 片，係黏著於該載板上，並藉由多數之銲線與該容置體電 性連接者，且該載板與該晶片之熱膨脹係數係相近者；一 罩體，該罩體係罩設於該容置體上，並封抵住該容室之開 口，以避免該容室中之晶片受外力之破壞或雜物污染者。 為使審查委員能更詳細瞭解本發明之實際構造及特 15 點，茲列舉以下實施例並配合圖示詳細說明如后，其中·· 笫一圖係一種習用晶片構裝結構之剖視示意圖； 笫二圖係本發明笫一較佳實施例之剖視圖； 笫三圖係本發明笫二較佳實施例之剖視圖； 笫四圖係本發明笫三較佳實施例之剖視圖； 20 笫五圖係本發明笫四較佳實施例之剖視圖； 請參閱笫二圖，係本發明笫一較佳實施例所提供一種 可減低應力之晶片構裝（10)，其主要包含有一容置體 (20)、一載板（30)、一晶片（40)、多數之銲線（50)及一罩體 (60);其中； -4- (請先閱讀背面之^一意泉項再) -裝·, 1T line .............. This paper size applies to China National Standard (CNS) Α4 specification (210 × 297 (Mm) 504809 Printed by A7 B7, Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention () In view of the above-mentioned shortcomings, the inventor of this case has carefully considered and accumulated many years of experience in wafer fabrication and research and development This experience has resulted in the invention. That is, the main purpose of the present invention is to provide a five-crystal structure capable of reducing stress, which can reduce the stress on the wafer or make the stress uniform, and reduce the occurrence of damage. For this reason, the present invention provides a wafer structure capable of reducing stress, which mainly includes: a receiving body; and a carrier plate, which is bonded to the receiving body and forms a space between the receiving body and the carrier plate. There is a container chamber with an opening upwards; 10 crystals are adhered to the carrier board, and are electrically connected to the container body by most bonding wires, and the thermal expansion coefficient of the carrier board and the wafer are similar A cover body, the cover system cover is arranged on the containing body, and seals against the opening of the containing room, so as to prevent the wafer in the containing room from being damaged by external forces or contaminated by debris. In order to enable the reviewing committee to understand the actual structure and features of the present invention in more detail, the following examples are given in conjunction with the illustrations to explain in detail as follows, where the first picture is a schematic cross-sectional view of a conventional wafer structure; The second figure is a sectional view of the first preferred embodiment of the present invention; the third figure is a sectional view of the second preferred embodiment of the present invention; the fourth figure is a sectional view of the third preferred embodiment of the present invention; A cross-sectional view of the twenty-fourth preferred embodiment of the present invention; please refer to the second figure, which is a wafer structure (10) capable of reducing stress provided by the first preferred embodiment of the present invention, which mainly includes a containing body (20) , A carrier board (30), a chip (40), most of the welding wires (50) and a cover (60); of which; -4- (please read the ^ Yiyiquan item on the back first)-equipment ·

、1T 線- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） 504809 A7 B7 五、發明説明（ 10 15 經濟部智慧財產局員工消費合作社印製 20 該容置體（20)係可為塑膠、強化塑膠、玻璃纖維或陶 瓷··等材質所製成之電路板（Printed Circuit Board， PCB);該容置體（20)具有一頂面（21)及一位於該頂面（21) 反側之底面（22)，自該頂面（21)上向下延伸凹陷而形成有 一開口向上之容室（23)，該容室（23)形成有一底部（231)， 且該底部（231)上形成有呈預定數量及態樣之電路（圖中未 示）； 該載板（30)係為一板體，並藉由一黏結物（31)而黏結於 該容室（23)之底部（231)上，且該載板（30)與該底部（231)間 之黏結面積，係以可支撐及固定該載板（30)於該底部（231) 上之最小面積，且以該黏結物（31)不塗佈至該載板（30)之 側緣為原則，且該載板（30)係由與該晶片（40)之熱膨脹係 數相近之材質所製成（如Alloy 42或碎元素）； 該晶片（40)，係由矽（si)元素所製成，並藉由如環氣樹 脂、秒樹脂、低溶點之玻璃或雙面膠帶…等其中之一黏著 物（圖中未示），直接黏著而固定於該載板（30)上，該晶片 (4〇)之表面上具有多數之銲螯（圖中未示）； 該等銲線（50)，係由黃金或鋁等導電金屬材質所製 成，並利用打線技術將該等銲線（50)之一端與該晶片（40) 之銲墊連接，另一端則與該容置體(20)底部（231)上之電路 呈電性連接，而可藉由該容置體（2〇)作為該晶片（4〇)與外 界導通之媒介； 該罩體（60)，係由不透明之塑膠、金屬或透明之玻 璃、塑膠等材質所製成之板件，其具有一頂端（61)及一位 請 先 閲 讀 背 之 注 意 再 裝 訂 -5- 本紙張尺度適用中國國家標準（CNS〉Μ規格（210〆297公釐） 504809 A7 B7 五 、發明说明（ 10 15 經濟部智慧財產局員工消費合作社印製 20 於該頂端（61)反側之底端（62);該底端（62)係藉由一黏結物 (63)而結合於該容置體（2〇)之頂面（21)上，而可封抵住該容 室（23)之開口，以保護位在該容室（23)中之晶片（40)不受外 力之破壞或雜物之污染者。 在此需特別說明的是：由於該晶片（40)係由矽元素所 製成，其熱膨脹係數約為4 Xl(T6，而與該晶片（40)呈直接 黏結之載板（30)，其材質之熱膨脹係數與該晶片（40)之熱 膨脹係數又極為相近，不僅可使得該載板（30)發生撓曲或 變形之機率大為減低，同時亦可避免該載板（30)對該晶片 (40)產生過度之應力或應力分佈不均之不良之影響，而對 該晶片（40)產生破壞，可使該晶片（4〇)受該載板（30)之撓曲 而破壞之情形大幅減低；而且由於該載板〇〇)與該容置體 (20)間之黏結面積縮減，可減少該容置體(20)對該載板(30) 所產生之撓曲或應力較大等之不良影響。 並且由於該容置體(20)並未與該晶片（40)呈直接黏接， 而可以價格較為低廉之塑膠或陶瓷等材質製成，以減低該 構裝（1〇)在製造上之成本； 上述構裝（10)於使用時，可利用鍚銲或其它電性連接 之方式，將該容置體（20)與組裝有必要電子元件之電路板 (圖中未示）連接即可。 請參閱笫三圖，係本發明笫二較佳實施例所提供一種 可減低應力之晶片構裝（70)，其同樣包含有一容置體 (71)、一載板（72)、一晶片（73)、多數之銲線(74)及一罩體 (75);其與上述實施例之主要差異在於： 請 先 閲 讀 背 意 事 項 再 螬 頁 裝 訂 線 -6- 本紙張尺度適用中國國家標準（c Μ規格（謂χ297公襲 504809 經濟部智慧財產局員工消費合作社印製 A7 _B7__五、發明説明（） 該容置體（71)更設有一貫穿該容室（713)底部（714)至該 底面（712)之開孔（715);而該容置體（71)之頂面（711)上設 有呈預定數量及態樣之電路（圖中未示）； 該載板（72)係以其一端面之周緣藉由一黏結物（721)而 5 黏著於位在該容室（713)底部（714)之開孔（715)周緣上； 其次，該晶片（73)係黏著於載板(72)之另一端上，並藉 由該等銲線(74)將該晶片（73)分別電性連接於該容置體（71) 底部（714)及頂面（711)上之銲墊。 請參閱笫四圖，係本發明笫三較佳實施例所提供一種 ίο 可減低應力之晶片構裝（80)，其同樣包含有一容置體 (81)、一載板（82)、一晶片（83)、多數之銲線（84)及一罩體 (85);其與上述實施例之主要差異在於： 該容置體（81)係為一中空之框體，而於其中空部份形 成有一内壁面（813); 15 該載板（82)係以其側邊（821)黏著於該容置體（81)—端 之内壁面（813)上，使原來之中空部份受該載板（82)之封合 而形成一開口向上之容室（814)，且該容置體（81)之頂面 (811)上設有若干之銲墊（圖中未示），並藉由該等銲線（84) 先與該晶片（83)上之銲墊（圖中未示）連接，再以近乎水平 20 延伸之方式與該頂面（811)上之銲墊連接，且該容置體（81) 之銲墊周緣設有若干貫穿其頂、底面（811)(812)之貫孔 (815)，而可藉由銲鍚或其它連接件置於該等貫孔（815) 中，而將其電性導通於外界之電路板（圖中未示）上者。 -7- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填頁) .裝- 訂 線 504809 A7 B7 五、發明説明（ 10 1 5 請參閱笫五圖係本發明笫四較佳實施例所提供一種可 減低應力之晶片構裝(90)，其同樣包含有一容置體(91)、 一載板(92)、一晶片（93)、多數之銲線(94)及一罩體(95); 其與笫上述較佳實施例之主要差異在於： 該罩體（95)，係由不透明之塑膠、金屬所製成之板 件，其具有一通孔（951)，該通孔（951)係對應該晶片（93)之 位置，且該通孔（951)中至少封設固定有一鏡片（952)，可 使外部之光線由該鏡片（952)穿透並照射於該晶片（93)上 者； 於使用時則可藉由銲球、銲錫、鍚膏或其它電性連接 之方式，將該容置體（91)電性連接於外界之電路板上即 "5J* 〇 综上所述，本發明可減低應力之晶片構裝，確實具有 縮減對晶片產生應力之功效，實具其進步實用性，且在使 用上之方便，又，本發明於申請前並無相同物品見於刊物 或公開使用，是以，本發明實已具備發明專利要件，為保 障發明人之苦思，爰依法提出申請。 請 先 閲 讀 背 面 之 注- 意 事 項— 再 m 頁 裝 訂 經濟部智慧財產局員工消費合作社印製 -8- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 504809 A7 B7 五、發明説明（ 簡單圖示說明： 笫一圖係一種習用晶片構裝結構之剖視示意圖 笫二圖係本發明笫一較佳實施例之剖視圖。 笫三圖係本發明笫二較佳實施例之剖視圖。 笫四圖係本發明笫三較佳實施例之剖視圖。 笫五圖係本發明笫四較佳實施例之剖視圖。 經濟部智慧財產局員工消費合作社印製 圖號說明： 「笫一較佳實施例」 1〇 可減低應力之晶片構裝（10) 容置體(20) 頂面（21) 底部（231) 載板(30) 銲線(50) 罩體(60) 黏結物（63) 15 「笫二較佳實施例」 可減低應力之晶片構裝(70) 容置體（71) 頂面（711) 底部（714) 開孔（715) 晶片（73) 銲線(74) 20 「笫三較佳實施例」 可減低應力之晶片構裝（80) 容置體（81) 頂面（811) 容室（814) 貫孔（815) 晶片（83) 銲線(84) 底面（22) 黏結物（31) 頂端（61) 容室（23) 晶片（40) 底端（62) 底面（712)容室（713) 載板(72) 黏結物（721) 罩體(75) 底面（812)内壁面（813) 載板（82) 側邊（821) 罩體(85) (請先閲讀背面之法意事項再填 訂 -線‘ -9- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 504809 A7 B7 五、發明説明（） 「笫四較佳實施例」 可減低應力之晶片構裝(90) 容置體（91) 通孔（951) 鏡片（952) 載板(92) 晶片（93) 銲線(94) 罩體(95) II--------t.-- (請先閱讀背面之法意事唷再填頁)Line 1T-This paper size applies Chinese National Standard (CNS) A4 (210X 297mm) 504809 A7 B7 V. Description of the invention (10 15 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 20 The container (20) It is a printed circuit board (PCB) made of plastic, reinforced plastic, fiberglass, or ceramics. The container (20) has a top surface (21) and a top surface. (21) A bottom surface (22) on the opposite side, a recess extending downward from the top surface (21) to form a container chamber (23) with an opening upward, the container chamber (23) forming a bottom (231), and the A predetermined number of circuits are formed on the bottom (231) (not shown in the figure); the carrier board (30) is a board body, and is bonded to the container chamber (31) by an adhesive (31). 23) on the bottom (231), and the bonding area between the carrier plate (30) and the bottom (231) is the smallest area that can support and fix the carrier plate (30) on the bottom (231), The principle is that the adhesive (31) is not coated on the side edge of the carrier plate (30), and the carrier plate (30) is formed by Made of materials with similar expansion coefficients (such as Alloy 42 or broken element); The wafer (40) is made of silicon (Si) element, and is made of resin such as ring gas resin, second resin, and low melting point glass Or double-sided adhesive tape ... etc. One of the adhesives (not shown) is directly adhered and fixed on the carrier board (30). The surface of the wafer (40) has a large number of welding chelates (not shown in the figure). ); The bonding wires (50) are made of conductive metal materials such as gold or aluminum, and one end of the bonding wires (50) is connected to the pad of the chip (40) by using wire bonding technology, and the other end It is electrically connected to the circuit on the bottom (231) of the containing body (20), and the containing body (20) can be used as a medium for the chip (40) to communicate with the outside; the cover ( 60), is made of opaque plastic, metal or transparent glass, plastic and other materials, it has a top (61) and one please read the back of the note before binding -5- This paper size applies Chinese national standard (CNS> M specification (210〆297 mm) 504809 A7 B7 V. Description of invention (10 15 Economy The Intellectual Property Bureau employee consumer cooperative prints 20 the bottom end (62) on the opposite side of the top end (61); the bottom end (62) is combined with the container (20) by a glue (63) On the top surface (21), and can be sealed against the opening of the accommodating chamber (23) to protect the wafer (40) located in the accommodating chamber (23) from external forces or contaminated by debris. It should be particularly noted here that because the chip (40) is made of silicon, its thermal expansion coefficient is about 4 Xl (T6, and the carrier board (30) is directly bonded to the chip (40). The thermal expansion coefficient of the material is very similar to the thermal expansion coefficient of the wafer (40), which not only greatly reduces the chance of the carrier plate (30) from being bent or deformed, but also prevents the carrier plate (30) from affecting the wafer. (40) The excessive influence of stress or uneven distribution of stress, and the damage to the wafer (40), can cause the wafer (40) to be damaged by the flexure of the carrier board (30). Reduced; and because the bonding area between the carrier plate 〇) and the receiving body (20) is reduced, the receiving body (20) can reduce the space of the carrier plate (30). Health of deflection or adverse effects of large stress like. And because the containing body (20) is not directly adhered to the chip (40), it can be made of a relatively inexpensive plastic or ceramic material to reduce the manufacturing cost of the structure (10); When the above structure (10) is in use, it can be connected to the circuit board (not shown in the figure) with necessary electronic components by using soldering or other electrical connection methods. Please refer to FIG. 3, which is a wafer structure (70) capable of reducing stress provided by the second preferred embodiment of the present invention, which also includes a receiving body (71), a carrier board (72), and a wafer ( 73), the majority of the welding wire (74) and a cover (75); the main differences from the above embodiment are: Please read the back matter before the title page binding line-6- This paper size applies Chinese national standards ( c Μ specifications (referred to as χ297 public attack 504809 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7__ V. Description of the invention () The container (71) is further provided with a container (713) bottom (714) to The openings (715) of the bottom surface (712); and the top surface (711) of the containing body (71) is provided with a predetermined number and appearance of circuits (not shown in the figure); the carrier board (72) The peripheral edge of one end surface is adhered to the periphery of the opening (715) located at the bottom (714) of the chamber (713) by a bond (721) and 5; secondly, the wafer (73) is adhered to On the other end of the carrier board (72), and electrically connect the chip (73) to the bottom (714) of the containing body (71) through the bonding wires (74), respectively The solder pad on the top surface (711). Please refer to Fig. 24, which is a wafer structure (80) capable of reducing stress provided by the third preferred embodiment of the present invention, which also includes a containing body (81) , A carrier board (82), a wafer (83), a plurality of bonding wires (84), and a cover (85); the main differences from the above embodiments are: the containing body (81) is a hollow Frame, and an inner wall surface (813) is formed in the hollow portion; 15 the carrier plate (82) is adhered to the inner wall surface (813) of the containing body (81) with its side edge (821) The original hollow part is sealed by the carrier plate (82) to form an open-up container chamber (814), and a number of weldings are provided on the top surface (811) of the container body (81). Pads (not shown), and firstly connected to the pads (not shown) on the chip (83) by the bonding wires (84), and then extend to the top surface (about 20 horizontally) 811), and the periphery of the pad of the accommodating body (81) is provided with a plurality of through holes (815) penetrating the top and bottom surfaces (811) (812), and can be connected by welding pads or other Pieces placed in the through holes (81 5), and it is electrically connected to the external circuit board (not shown). -7- This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the back Note for refilling). Binding-Thread 504809 A7 B7 V. Description of the invention (10 1 5 Please refer to Figure 5 is a wafer structure (90) with reduced stress provided by the fourth preferred embodiment of the present invention. It also includes a receiving body (91), a carrier board (92), a wafer (93), most bonding wires (94), and a cover (95); the main differences from the above-mentioned preferred embodiments The cover (95) is a plate made of opaque plastic and metal, and has a through hole (951), the through hole (951) corresponds to the position of the wafer (93), and the through hole At least one lens (952) is sealed and fixed in the hole (951), so that external light can pass through the lens (952) and shine on the wafer (93); when in use, it can be used by solder balls, solder , Paste, or other electrical connection methods, the container (91) is electrically connected to an external circuit board, that is, " 5J * 〇 In summary The invention can reduce the stress of the wafer structure, and indeed has the effect of reducing the stress on the wafer. It has its practicality of progress, and is convenient to use. Moreover, before the application, the same article did not appear in the publication or public use. Therefore, the present invention already has the elements of an invention patent. In order to protect the inventor's painstaking efforts, he has submitted an application in accordance with the law. Please read the note on the back first-Matters to be printed on the m-page bound by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumers' Cooperatives-8-This paper size applies to China National Standard (CNS) A4 (210X297 mm) 504809 A7 B7 Explanation (Simplified illustration: (a) a diagram showing a sectional view of a conventional wafer mounting structure; (b) a diagram showing a sectional view of a preferred embodiment of the present invention; (b) a diagram showing a sectional view of a second preferred embodiment of the present invention; Figure 24 is a cross-sectional view of the third preferred embodiment of the present invention. Figure 5 is a cross-sectional view of the fourth preferred embodiment of the present invention. The number printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs explains the drawing number: Example "10 Stress-reduced wafer structure (10) Container (20) Top surface (21) Bottom (231) Carrier board (30) Welding wire (50) Cover body (60) Adhesive (63) 15 "Twenty-two preferred embodiments" Reduced stress wafer structure (70) Receiving body (71) Top surface (711) Bottom (714) Opening (715) Wafer (73) Welding wire (74) 20 " Twenty-Three Preferred Embodiments "Wafer Structure (80) Reduction for Reducing Stress (81) Top surface (811) Container (814) Through hole (815) Chip (83) Welding wire (84) Bottom surface (22) Adhesive (31) Top (61) Container (23) Wafer (40) Bottom End (62) Bottom surface (712) Receiving room (713) Carrier plate (72) Adhesive (721) Cover body (75) Bottom surface (812) Inner wall surface (813) Carrier plate (82) Side edge (821) Cover body ( 85) (Please read the French and Italian matters on the back before filling-line '-9- This paper size applies to Chinese National Standard (CNS) A4 specifications (210X 297 mm) 504809 A7 B7 V. Description of the invention () “笫 四Preferred embodiment "Wafer structure (90) with reduced stress Receiving body (91) Through hole (951) Lens (952) Carrier board (92) Wafer (93) Welding wire (94) Cover (95) II -------- t .-- (please read the legal meanings on the reverse side before filling in the page)

、1T 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）、 1T Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 specification (210X297 mm)

Claims (1)

504809 A8 B8 C8 D8 六、申請專利範圍 1 · 一種可減低應力之晶片構裝，其主要包含有： 一容置體； 一載板，係與該容置體黏結，並使該容置體與該載板 間形成有一開口向上之容室； 5 一晶片，係黏著於該載板上，並藉由多數之銲線與該 容置體電性連接者，且該載板與該晶片之熱膨脹係數係相 近者； 一罩體，該罩體係罩設於該容置體上，並封抵住該容 室之開口，以避免該容室中之晶片受外力之破壞或雜物污 10 染者。 2·依據申請專利範圍笫1項所述可減低應力之晶片構 裝，其中該載板係與該晶片同一材質者。 3·依據申請專利範圍笫1項所述可減低應力之晶片構 裝，其中該載板係為Alloy 42所製成。 15 4 ·依據申請專利範圍笫1項所述可減低應力之晶片構 裝，其中該容置體座係可為塑膠、強化塑膠、玻璃纖維或 陶瓷..等材質所製成者。 5·依據申請專利範圍笫1項所述可減低應力之晶片構 裝，其中該容置體具有一頂面及一底面，而該容室係自頂 20 面向下凹陷而形成，且該容室形成有一底部；該載板係黏 結於該底部上者。 6 ·依據申請專利範圍笫5項所述可減低應力之晶片構 裝，其中該容置體之頂面上設有多數之銲墊，而由該等銲 線與該晶片電性連接者。 -11- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再本頁) -裝. 、1T 經濟部智慧財產局員工消費合作社印製 504809 A8 B8 C8 D8六、申請專利範圍 7·依據申請專利範圍笫1項所述可減低應力之晶片構 裝，其中該容置體係為中空之框體，而形成有一内壁面； 該載板係以其側邊黏著於該内壁面上，使該容置體與該載 板間形成該容室，以供該晶片置設者。 5 8·依據申請專利範圍笫1項所述可減低應力之晶片構 裝’其中該容置體具有一頂面及一底面，而該容室係自頂 面向下凹陷而形成，且該容室形成有一底部，並該底部與 該頂面間設有一通貫之開孔；該載板係黏結於該開孔周緣 之底部上者。 10 9 ·依據申請專利範圍笫1項所述可減低應力之晶片構 裝，其中該罩體，係由不透明之塑膠、金屬所製成之板 件，其具有一通孔，該通孔係對應該晶片之位置，且該通 孔中至少封設固定有一鏡片，可使外部之光線由該鏡片穿 透並照射於該晶片上者。 15 10 ·依據申請專利範圍笫1項所述可減低應力之晶片 構裝，其中該載板與該底部容置體間之黏結面積，係以可 支撐且固定該載板於該容置體上之最小面積，且以不黏結 至該載板之側緣為原則。 (請先閲讀背面之注意事項再ipt本頁) -裝. 經濟部智慧財產局員工消費合作社印製 -12- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐)504809 A8 B8 C8 D8 6. Scope of patent application 1 · A wafer structure capable of reducing stress, which mainly includes: a container; a carrier board, which is bonded to the container, and makes the container and A cavity with an upward opening is formed between the carrier plates; 5 A chip is adhered to the carrier plate and is electrically connected to the receiving body through a plurality of bonding wires, and the carrier plate and the wafer are thermally expanded. The coefficients are similar; a cover body, the cover system cover is arranged on the containing body, and seals against the opening of the containing room, so as to prevent the wafers in the containing room from being damaged by external forces or contaminated by debris. . 2. According to the scope of the patent application (1), the wafer structure can be reduced in stress, wherein the carrier board is made of the same material as the wafer. 3. The stress-reduced wafer structure according to item 1 of the patent application scope, wherein the carrier board is made of Alloy 42. 15 4 · According to the scope of patent application (1), the wafer structure can be reduced in stress, wherein the housing body can be made of plastic, reinforced plastic, fiberglass or ceramic .. 5. According to the patented scope of the patent application (1), the wafer structure can be reduced in stress, wherein the containing body has a top surface and a bottom surface, and the containing chamber is formed by depression from the top 20 and the containing chamber A bottom is formed; the carrier board is bonded to the bottom. 6 · According to the scope of the patent application, item 5 of the wafer structure can be reduced stress, wherein the top surface of the containing body is provided with a large number of pads, and these wires are electrically connected to the wafer. -11- This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before this page)-Packing, 1T Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 504809 A8 B8 C8 D8 6. Scope of patent application 7. The stress-reduced wafer structure according to item 1 of the scope of patent application, wherein the housing system is a hollow frame and an inner wall surface is formed; The edge is adhered to the inner wall surface, so that the containing chamber is formed between the containing body and the carrier board for the chip setter. 5 8 · According to the scope of the patent application 笫 1, the stress-reduced wafer structure 'wherein the containing body has a top surface and a bottom surface, and the containing chamber is formed by depression from the top to the bottom, and the containing chamber A bottom is formed, and a through hole is provided between the bottom and the top surface; the carrier board is bonded to the bottom of the periphery of the hole. 10 9 · According to the scope of the patent application (1), the structure of the wafer can be reduced, wherein the cover is a plate made of opaque plastic and metal, which has a through hole. The through hole corresponds to The position of the wafer, and at least one lens is sealed and fixed in the through hole, so that external light can pass through the lens and shine on the wafer. 15 10 · According to the scope of the patent application (1), the wafer structure can be reduced in stress, wherein the bonding area between the carrier board and the bottom container is to support and fix the carrier board on the container. The minimum area is based on the principle of not sticking to the side edges of the carrier board. (Please read the precautions on the back before ipt this page)-Pack. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -12- This paper size applies to China National Standard (CNS) A4 (210X297 mm)
TW090124246A 2001-10-02 2001-10-02 Chip package with reduced stress TW504809B (en)

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