1243441 九、發明說明： 【發明所屬之技術領域】 本發明係種微小銲賴距封裝載板之製造方法與結構，尤指於形成 無導電線層後，於未形成防銲阻劑層之處，以浸金處理形成浸金層。 【先前技術】 由於電子產品輕薄短小之趨勢’加上功能之不斷增多，使得晶片之1/〇數 快速增加，姉的難技術也稍靖，齡在高階產品巾已錄採用覆 晶封裝（Flip Chip)的技術，封裝密度也隨之不斷地提高。 此類封裝載板通常均具有晶牌接面㈣side)和銲球面(㈣ side)， 而於晶牌接面的結合鮮墊(bump pad)，乃用以連結至少一個元件(諸如 晶片中的覆晶、被動it件中的電阻和電容、對位標乾(fiducial腦⑴、 ^«(ball pad)f ) 〇 ^Wf^E(ball pitch) , !_2 mm 小至微小間距（fine Pitch)〔意即約〇.5刪〕。 此類封裝載板的銲球_主要用以填人銲球，不過，也由於隨著銲球間距 縮小’銲球體積也必須相對地大幅減小，縮小至其直徑小於〇.3mm，因此， 右以最被廣為使用的無電鑛鎳/浸金(Electr〇less NickeiG〇id ENIG)作銲球面的表面處理，雖然可解決金層太厚導致之脆化而容易掉球 的問題，但是因採無電鍍鎳形成鎳層時，常因伴隨磷的存在，易因氧化而 形成黑塾（black pad)，進而同樣地仍會發生掉球的問題，所以，跗1(；作 1243441 表面處理仍非最佳转。就算改喊接電鍍鎳金來改善黑墊_，但卻必 須面對多餘的導電線之處理(料產生天線效應，亦料造成雜訊)以及電 鍍金不易均勻鍍薄，且又有脆化之虞。 【發明内容】 本發明之主要目的在提供—讎小銲球間距封裝載板之製造方法與結構， 藉著先形成無多餘的導輯層後，躲未形成__層之處，以浸金處 理形成浸金層，如此在不需面射餘鱗躲之處理的情訂，另利用浸 金來解決厚金脆化會掉球之問題。 本發明之[目的缺供__讎小鲜_距封裝載板之觀綠與結構， 藉著電雜來改善黑墊問題，避免如採用ENIG所造成的黑墊，進而避免掉 球的問題。 本發明之另-目的在提供-種微小銲賴距封賴板之製造方法與結構， 藉此在録球間距快速縮小至微小間距時，仍可以順利完成晶片封褒。 本發明之另-目的在提供—種微祕賴闕賴板之製造方法與結構， 可藉著由浸金處理所形成的浸金層，保護結合銲塾(Bump pad)之銅面，避 免於^'裝時的⑥溫時與共溶金屬（pre_SQlder)反應而產生氣泡。 本發明之另一目的在提供一種微小銲球間距封裝載板之製造方法與結構， 在銲球面、結合銲墊、對位靶標及被動元件區以電鍍鎳與浸金取代傳統印 刷鲜錫錯處理，解決超微距晶片無鉛銲接封裝的問題。 基於上述目的，本發明提供一種微小銲球間距封裝載板之製造方法與結 1243441 構。於載板銲球面側具有表面為介電層的已包覆載板，並於介電層上形成 薄銅層。藉著形成在_層上_案化光阻層定義出光阻層開口，而於此 光阻層開Π内已具有第二電鍍金屬層，其結構上的特徵在於，在形成一無 導電線(Bussless)載板後，亦即該載板表面除了必要線路(Traee)外，已去 除多餘之導電線(Buss)後，於未形成一防銲阻劑層之處，以一浸金 (immersion gold)處理形成一浸金層，該無導電線載板乃指，於去除該圖 案化光阻層祕露的部分該薄銅層後，峨絲刻⑴純etdUng)去除多 餘之導電線(Buss)直到曝露出該介電層；而防鮮阻劑層則依據載板設計， 至少於介電層和第二電鍍金屬層上形成。 本發明所提供的製造方法，可以提供較高之晶片封裝密度良率，針對下一 代晶圓奈米技術製作超高密度晶片晶片及封裝等結構性需求，在載板的製 作上提供一解決方案。 關於本發明之優點與精神可以藉由以下的發明詳述及所附圖式得到進一步 的瞭解。 【實施方式】 請參閱第1A〜1P圖，第1A〜1P圖為本發明微小銲球間距封裝載板之製造方 法的示意圖。此類封裝載板通常均具有晶片銲接面(die 銲球面 (ball side)。第1A〜IF圖為已包覆載板的製造方法，此部份主要屬於習 知技術，而第1G〜1P圖為本發明微小銲球間距封裝載板的主要製程方法， 其中，第1M圖標示出於晶片銲接面上的被動元件區、結合銲墊、對位標乾。 1243441 間略而s ’本發明所揭露的結構，主要是要在銲球面上如第㈣所示的社 構，而其製造方法，如第1M圖所示，先以於形成無多餘的導電線（以快逮 侧（flash etchlng)去除薄銅層15直到曝露出介電層職，如第10圖 所示，再以於未形成防銲阻觸25之處，以浸金(Wsion 處理形 成如第1P圖所示之浸金厣邓。1 曰26如此，在不舄面對多餘的導電線之處理的情 況下，另糊浸絲解決厚麵化會掉球之問題。 雖然，本發明主要的特徵在於銲球面的結構與製造方法，但是，由於一般 在製作此纖_，均會_相在⑼銲接面和銲球社製作出所需的又 結構，因此，在說明於lA〜lp圖憎球面的製作方法的同時，也會順帶說 明晶片銲接面上製作結合銲墊—pad)，至於晶片輝接面的金轉接塾， 則稍後以丨®不說明之。需特別注意的是，除非有特別提及，否則晶片 銲接面ί鋅球面均；^以相似製程步驟(些微不同之處請參閱圖示）。以下， 首先簡單說月已包覆餘的製造方法，再分別詳述如何定義出如第Μ圖所 π之被動7L件區、結合轉、對位雜，以及如何進行浸金處理而形成如 第1Ρ圖所示之浸金層26。 如第1Α〜1F圖所示，已包覆载板的製造方法，首先，提供-厚度約為〇. 8咖 的基板1，並形成厚度約為5〜12_的第-金屬層3於基板！上，如第M 圖所丁基板1的材質—般選用Bis—deTriazine(BT)或其他有機材 料’甚至為陶紐質。接著，以機械鑽孔，而貫穿第―金屬層3和基板卜 形成寬度約為議〜25G_的核心基板通孔5 (赚thn)ugh hQle)，如第 1B圖所不。然後’形成材質可為銅且厚度約為的第—電鑛金屬層 1243441 7於第-金屬層上3以及核心基板通孔5側壁上，如第所示。如第Μ 圖所示，去除部分第-電鍵金屬層7和第一金屬層3直到曝露出基板i。如 此，在第-電鍍金屬層7和第-金屬層3内，形成内層線路開口 u，未被 去除的第-電糊層7和第-金屬層3為内層線路。如第if圖所示之乾 膜9則用以形成此内層電路。於[電鍍金屬層7上形成已圖案化的乾膜 9 ’以作為去除部分第-電鑛金屬層7和第一金屬層3的光罩。接著，形成 第"電層13，1編郷-1般麟7謂她u和核心基板 通孔5’如第3F圖所示。如第1F騎示之其表面為由_ 13所包覆的， 乃為已包覆载板。 如第㈣和㈣圖所示的製造方法，乃本發明的主要製造方法，至炉 1J和部㈣_示的製造方法，縣定義_1M騎示之被動元件區 結合銲墊、對位標靶所必須的步驟。 於如第1叫和則p圖所示的製造方种，錢在已_板的介電層 13上形成厚約i _至3卿的薄銅層15，如第1G圖所示。接著，於薄銅 層15上形成圖案化光阻層17，圖案化光阻層17内至少具有光阻層開口， 第1H圖所不。然後，以全板電鑛㈤㈣p㈣呢)使光阻層開口内具有 材質為銅的第二電鑛金屬層19，如第π圖所示。如第ικ圖所示的鲜球面 上的第二電錢金屬層19上電娜成電_層23，需特別注意的是，晶片輝 接面也有形成此電_層23,不過形成的位置將因乾膜21而有不同，因此， 谷後在述。 如第1L圖所示，去除圖案化光阻層17，使縣本被圖案化光阻層㈣蓋 1243441 住的部分薄銅層15被曝露出來。緊接著，以快速侧已被曝露出的部分薄 銅層15，亦即去除多餘之導電線(Buss)，直到曝露出介電層a，如第w 圖所不。至此，已形成無導電線(Bussless)載板後，亦即此載板表面除了 必要線路(Trace)外，已去除不存在多餘之導電線(Buss)。接著，於介電層 13 #電鍍鎳層23上形成防銲阻劑層25，如第1N圖所示。然後，如第⑺ 回斤丁於絲成防銲賴層25之處，崎金(i_rsiQn gQld)處理形成如 第1P圖所示之浸金層26。 綜上所述’如第1G〜U和1K〜lp _示之本發日錄造方法，主要藉著先形 成.、、、夕餘料電線層後，再於未形成防銲_層25之處以浸金處理形成 浸金層26，如此在不需面對多餘的導魏之處理的航下，另_浸金來 解決厚金脆化她_題。再者，也随著如第ικ _形成的電鑛錄層 。來改…墊問題，避免如採用娜所造成的黑墊(形成電鋪層烈時不 而伴Ik磷的存在），進而避免掉球的問題。因此，本發明所提供的結構與製 k方法可藉此在銲球間距快速縮小至微小間距時，仍可以順利完成晶片 封裝。 為了同時製作於晶片銲接面(die side)的如第1M圖所示之被動元件區、結 合鲜塾、對位躲、線路19a，於晶片銲接面上，施以與銲球面⑽丨side) 上相同的製程步驟至全板電錢（亦即第u圖）後，於晶片鲜接面的製造方 法，百先，以乾膜21覆蓋住結合銲塾（亦即較短小者），如第^圖所示。 妾著於未被乾膜21覆蓋住的於光阻層開口内，電鍍形成電鍍鎳層四（同 步地與銲球面實施）’如第1K圖所心接著，如第1圖所示，在鲜球面去 1243441 除圖案化光阻層17的同時，去除乾膜21。另外，如第lw 曰 斯罘U圖所示，隨著於 銲球面上介電層13和電鍍鎳層23上形成防銲阻劑層25的同時，也於曰 銲接面上形成防銲阻劑層25，使得被動元件區、結合録恭、 τ對位標靶、線 路19a之間具有防銲阻劑層25，並且覆蓋住線路19。至於其他曰片鲜接面 的製程步驟仍與銲球面大致相同，請參閱第1M〜1P圖。〇 η备 一 M ，、疋，在如第10圖 所示’施崎錢赠，跡帛1N騎权結合_以域或錫錯共炼 金屬（Pre-solder)以利於結合銲墊（Bump pad)與覆晶之銲接 請參閱第2A~2K圖，第2A〜2K圖為製作金線銲接墊之示意圖。為了同時製 作於阳片鮮接面的金線銲接墊(b〇n(j figure pacj)，於晶片銲接面上扩以 與銲球面上_的製程步驟至全板紐（Panel plating)(卿第^圖） 後的製造方法’如第2A圖所示，首練晶牌接面上的第二麵金屬層Μ 分別定義成線路（Trace)19a、金線銲接墊1%和對位標乾咖。然後，以 乾膜28覆蓋住線路19a的部分，如第2B圖所示。在晶片鮮接面的未覆蓋 乾膜28上與薛球面之第二電鑛金屬層19上電鑛形成電錢鎖層23，如第沈 圖所示。接著，再以乾膜30僅覆蓋住鲜球面，如第2D圖所示。然後，於 未被乾膜30蓋住的晶片銲接面之金線銲接墊上亦即在電鑛錄層幻上電 娜成植麵27 ’如第2E圖所示。之後，去除乾賴與3()及職化光 阻層17使得原'本被覆蓋住的部分薄銅層15被曝露出來，如第π圖所示。 緊接著’將以類似於第1M圖所示’亦即均於晶將接面和銲球面上以快 速姓刻已被曝露出的部分薄銅層15，亦即去除多餘之導電線(Buss)，直到 曝露出介電層13 ’如第2G圖所示。然後，於銲球面以及於晶片銲接面的介 12434411243441 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method and structure for manufacturing a micro soldering distance packaging carrier board, especially after a non-conductive wire layer is formed, where a solder resist layer is not formed. To form a gold immersion layer by gold immersion treatment. [Previous technology] Due to the trend of thin, light and short electronic products, coupled with the increasing number of functions, the number of chips has increased rapidly, and the difficult technology has also become slightly more difficult. High-end products have been recorded using flip-chip packaging (Flip Chip) technology, packaging density has also been continuously improved. This type of package carrier board usually has a 牌 side) and a ㈣side, and a bump pad is used to connect at least one component (such as the Resistors and capacitors in passive crystals, fiducial brains, ^ «(ball pad) f) 〇 ^ Wf ^ E (ball pitch),! _2 mm as small as fine pitch (fine pitch) [ This means about 0.5 deleted]. The solder balls of this type of package carrier board are mainly used to fill the solder balls, but because the solder ball volume has also been reduced, the solder ball volume must also be relatively greatly reduced, reducing to Its diameter is less than 0.3mm. Therefore, the most widely used Electroless NickelGeoid ENIG is used for the surface treatment of solder balls, although it can solve the embrittlement caused by too thick gold layer. It is easy to drop the ball. However, when the nickel layer is formed by electroless nickel plating, the black pad is often formed by oxidation due to the presence of phosphorus, and the ball drop problem also occurs.跗 1 (; 1234441 surface treatment is still not the best turn. Even if you call electroplating nickel gold to improve the black pad_, but It is necessary to deal with the processing of redundant conductive wires (which may cause antenna effect and noise), and the plating gold is not easy to be uniformly thinned, and there is a risk of embrittlement. [Abstract] The main purpose of the present invention is to provide— 在The manufacturing method and structure of the small solder ball pitch package carrier board, by forming a non-excessive guide layer and hiding the __ layer where it is not formed, the immersion gold layer is formed by immersion gold treatment, so that the surface is not required to be irradiated. The love of the scale hiding treatment, and the use of immersion gold to solve the problem of thick gold embrittlement will drop the ball. The purpose of the present invention [the lack of supply__ 雠 小 鲜 _ the green and structure of the package carrier, by electricity To improve the problem of black pads, to avoid the black pad caused by ENIG, and to avoid the problem of dropping balls. Another object of the present invention is to provide a method and structure for manufacturing a micro soldering distance sealing board, thereby When the ball-recording pitch is quickly reduced to a minute pitch, wafer sealing can still be successfully completed. Another object of the present invention is to provide a method and structure for manufacturing a micro-secret plate, which can be formed by immersion gold processing. Gold immersion layer to protect the copper surface of the bonding pad (Bump pad), Avoiding the occurrence of air bubbles when reacting with the eutectic metal (pre_SQlder) at the time of mounting. Another object of the present invention is to provide a method and structure for manufacturing a micro-ball pitch package carrier board. In the pads, alignment targets and passive component areas, traditional nickel plating and immersion gold are used to replace the traditional printed fresh tin error treatment to solve the problem of lead-free solder packaging of ultra-macro wafers. Based on the above purpose, the present invention provides a micro-ball pitch package carrier board. The manufacturing method and structure are 1234441. On the solder ball side of the carrier board, there is a coated carrier board whose surface is a dielectric layer, and a thin copper layer is formed on the dielectric layer. A photoresist layer is defined by forming a photoresist layer on the layer, and a second electroplated metal layer is already formed in the photoresist layer. The structure is characterized by the formation of a non-conductive wire ( After the Bussless carrier board, that is, the surface of the carrier board has been removed from the excess conductive wires (Buss) in addition to the necessary circuits (Traee), and where a solder resist layer is not formed, an immersion gold ) Processing to form an immersion gold layer. The non-conductive wire carrier board refers to removing excess conductive wires (Buss) after removing a part of the thin copper layer of the patterned photoresist layer and exposing the thin copper layer. Until the dielectric layer is exposed; and the anti-friction inhibitor layer is formed at least on the dielectric layer and the second electroplated metal layer according to the carrier board design. The manufacturing method provided by the present invention can provide a high yield rate of chip packaging density, and provide a solution in the manufacture of carrier boards in response to structural requirements such as the production of ultra-high density chip wafers and packaging by next-generation wafer nanotechnology. . The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings. [Embodiment] Please refer to Figs. 1A to 1P. Figs. 1A to 1P are schematic diagrams of a method for manufacturing a micro-ball pitch package carrier board according to the present invention. This type of package carrier usually has a wafer soldering surface (die solder ball side). Figures 1A to IF show the manufacturing method of the coated carrier. This part mainly belongs to the conventional technology, and Figures 1G to 1P This is the main manufacturing method of the micro-ball pitch package carrier board of the present invention, in which the 1M icon shows the passive component area, the bonding pad, and the alignment mark on the soldering surface of the wafer. 1243441 Slightly The disclosed structure is mainly a social structure shown on the solder ball surface as shown in Fig. ，, and its manufacturing method, as shown in Fig. 1M, is to form no unnecessary conductive wires (flash etchlng) Remove the thin copper layer 15 until the dielectric layer is exposed, as shown in Figure 10, and then immerse in gold (Wsion treatment to form gold immersion as shown in Figure 1P) where no solder resist 25 is formed. Deng. 1 26: So, without the need to deal with the excess conductive wires, another dip wire is used to solve the problem that the thickened surface will drop the ball. Although the main feature of the present invention is the structure and manufacturing of the solder ball surface Method, however, since this fiber is generally made, it will be on the welding surface The solder ball company has produced the required structure. Therefore, while explaining the manufacturing method of the spherical surface in the 1A ~ lp diagram, it will also explain the production of a bonding pad (pad) on the wafer soldering surface. Gold transfer is not explained later with 丨 ®. It is important to note that unless otherwise mentioned, the wafer soldering surface and zinc sphere are all similar; ^ Similar process steps (please refer to the diagram for slight differences) ). In the following, first briefly describe the manufacturing method of the moon-covered surplus, and then describe in detail how to define the passive 7L piece area as shown in Figure M, the combination transfer, the miscellaneous impurities, and how to form by immersion gold. As shown in FIG. 1P, the immersion gold layer 26. As shown in FIGS. 1A to 1F, the manufacturing method of the coated carrier is first provided with a substrate 1 having a thickness of about 0.8 and forming a thickness of about 5 ~ 12_ of the-metal layer 3 on the substrate! Bis-deTriazine (BT) or other organic materials are used as the material of the substrate 1 in Figure M-even ceramic materials. Then, use a mechanical drill Hole, and pass through the first metal layer 3 and the substrate to form a width of about 25G_ Core substrate through-hole 5 (thn) ugh hQle), as shown in Figure 1B. Then 'form the first metal ore metal layer 1234441 7 which can be made of copper and have a thickness of about 7344 on the third metal layer and the core substrate On the side wall of the through hole 5, as shown in the figure. As shown in FIG. M, a part of the first-key metal layer 7 and the first metal layer 3 are removed until the substrate i is exposed. Thus, the --plated metal layer 7 and the- In the metal layer 3, an inner layer circuit opening u is formed, and the unremoved first electric paste layer 7 and the first metal layer 3 are inner layer circuits. The dry film 9 as shown in the if diagram is used to form this inner layer circuit. [A patterned dry film 9 ′ is formed on the electroplated metal layer 7 to serve as a photomask to remove a part of the first-metallic metal layer 7 and the first metal layer 3. Next, the "electrical layer 13,1" is formed, as shown in Fig. 3F, and the core substrate through hole 5 'is formed as shown in Fig. 3F. As shown in 1F, its surface is covered by _13, which is a covered carrier. The manufacturing method shown in Figures VII and VII is the main manufacturing method of the present invention. To the manufacturing method shown in furnace 1J and Ministry __, the county defines the passive component area of _1M riding to combine pads and alignment targets. The necessary steps. In the manufacturing method as shown in Fig. 1 and Fig. 1, a thin copper layer 15 is formed on the dielectric layer 13 of the plate, i.e., to 3 mm thick, as shown in Fig. 1G. Next, a patterned photoresist layer 17 is formed on the thin copper layer 15. The patterned photoresist layer 17 has at least a photoresist layer opening, which is not shown in FIG. 1H. Then, a full-board power ore (p㈤㈣) is used to make the photoresist layer opening with a second power ore metal layer 19 made of copper, as shown in FIG. As shown in Figure ικ, the second electro-money metal layer 19 on the fresh spherical surface is electrically formed into an electrical layer_23. It should be noted that the electrical layer_23 is also formed on the wafer's splice surface. It differs depending on the dry film 21, so it will be described later. As shown in FIG. 1L, the patterned photoresist layer 17 is removed, so that a part of the thin copper layer 15 held by the patterned photoresist layer 1243441 is exposed. Next, the part of the thin copper layer 15 that has been exposed on the fast side is removed, that is, the excess conductive lines (Buss) are removed, until the dielectric layer a is exposed, as shown in Figure w. At this point, after a Bussless carrier board has been formed, that is, the surface of the carrier board has been removed with no extra conductive wires (Buss) except for the necessary traces. Next, a solder resist layer 25 is formed on the dielectric layer 13 #plated nickel layer 23, as shown in FIG. 1N. Then, as in the second step, the wire is formed into the solder resist layer 25, and i_rsiQn gQld is processed to form the gold immersion layer 26 as shown in FIG. 1P. In summary, the method of recording the current day as shown in 1G ~ U and 1K ~ lp _ is mainly formed by forming a wire layer first, and then, and then forming a solder resist _ layer 25. The gold immersion layer 26 is formed by the gold immersion treatment, so that without the need to deal with the extra guide Wei treatment, another gold immersion to solve the problem of embrittlement of thick gold. Moreover, it also follows the formation of electrical deposits as described in section ικ_. Let's change ... pad problems, avoid using black pads caused by Na (the presence of Ik phosphorus when the electric layer is formed), and then avoid the problem of dropping balls. Therefore, the structure and the manufacturing method provided by the present invention can successfully complete the chip package even when the solder ball pitch is quickly reduced to a minute pitch. In order to simultaneously produce the passive component area shown in FIG. 1M on the die side, combined with fresh 塾, alignment avoidance, and line 19a, the wafer welding surface is applied with the solder ball surface sideside). After the same process steps to full-board electricity (that is, figure u), the manufacturing method of the fresh joint of the wafer, Baixian, covers the bonding pad (that is, the shorter one) with a dry film 21, as described in section ^ As shown. Hold on the photoresist layer opening not covered by the dry film 21, electroplating to form a nickel plating layer 4 (synchronized with the solder ball surface) 'as shown in Figure 1K. Then, as shown in Figure 1, While removing the spherical surface 1234441 to remove the patterned photoresist layer 17, the dry film 21 is removed. In addition, as shown in FIG. 1W, as the solder resist layer 25 is formed on the dielectric layer 13 and the nickel plating layer 23 on the solder ball surface, a solder resist is also formed on the solder surface. Layer 25, so that there is a solder resist layer 25 between the passive element area, the combination recording, the τ alignment target, and the line 19a, and covers the line 19. As for the manufacturing process of the other freshly welded surface, it is still about the same as that of the solder ball surface, please refer to Figures 1M ~ 1P. 〇η Prepare a M ,, 在, as shown in Figure 10 'Shi Qi money gift, track 1N riding right combination _ domain or tin co-smelting metal (Pre-solder) to facilitate the bonding pad (Bump pad Please refer to Figures 2A ~ 2K for welding with flip chip. Figures 2A ~ 2K are schematic diagrams for making gold wire bonding pads. In order to simultaneously produce gold wire bonding pads (b00n (j figure pacj) on the fresh surface of the male film), the process steps of the wafer soldering surface and the solder ball surface are expanded to Panel plating. ^ Figure) after the manufacturing method 'as shown in Figure 2A, the second metal layer Μ on the face of the first practice crystal brand is defined as Trace 19a, gold wire pad 1%, and alignment standard dry coffee. Then, the part of the circuit 19a is covered with the dry film 28, as shown in FIG. 2B. On the uncovered dry film 28 on the fresh surface of the wafer, electricity is formed on the second electric metal layer 19 on the spherical surface of the wafer to form electric money. The locking layer 23 is shown in the second figure. Next, only the fresh spherical surface is covered with the dry film 30, as shown in FIG. 2D. Then, the gold wire bonding pad of the wafer welding surface not covered by the dry film 30 is covered. That is, on the electric power recording layer, the electric power generation surface 27 ′ is shown in FIG. 2E. After that, the dry copper layer 3 and the photoresist layer 17 are removed to make the original part of the thin copper covered. Layer 15 is exposed, as shown in Figure π. Immediately after 'will be similar to that shown in Figure 1M', that is, it is exposed on both the face of the wafer and the surface of the solder ball with a rapid name. Thin copper layer portion 15, i.e., to remove excess of conductive lines (a Buss), until 13 'as shown in FIG. 2G expose the first dielectric layer. Then, the solder balls on the wafer surface and the welded surface referral 1,243,441
於鋅球面未形成防銲阻劑層25之處， 如第21圖所示。最德， ，以濘奋Where the solder resist layer 25 is not formed on the zinc spherical surface, as shown in FIG. 21. Most virtue
藉由以上較佳具體實施例之詳述， ;:月、中並非乂上述所揭硌的較佳具體實施例來對本發明之範嘴加以限 制。相反地’其目岐希雜涵蓋各觀變及油等性的安排於本發明所 係希望能更加清楚描述本發明之特徵與 欲申請之專利範圍的範嘴内。 【圖式簡單說明】 第1A〜1P圖為本發明微小銲球間距封裝覆晶載板之製造方法 的示意圖。 第2A〜2K圖為製作金線銲接墊之示意圖。 【主要元件符號說明】 1基板 3第一金屬層 5核心基板通孔 7第一電鍍金屬層 12 1243441 9、21、28、30、32 乾膜 11内層線路開口 13介電層 15薄銅層 17圖案化光阻層 19第二電鍍金屬層 19a線路 19b金線銲接墊 19c對位標靶 23電鍍鎳層 25防銲阻劑層 26浸金層 27電鍍金層With the detailed description of the above preferred embodiments, the month and month are not the preferred embodiments disclosed above to limit the scope of the present invention. On the contrary, its arrangement of various aspects including various observations and oil is within the scope of the present invention. It is hoped that the features of the present invention and the scope of patents to be applied for can be more clearly described. [Brief description of the drawings] Figures 1A ~ 1P are schematic diagrams of a method for manufacturing a chip-on-chip carrier board with a small solder ball pitch package according to the present invention. Figures 2A ~ 2K are schematic diagrams for making gold wire bonding pads. [Description of main component symbols] 1 Substrate 3 First metal layer 5 Core substrate through hole 7 First plated metal layer 12 1243441 9, 21, 28, 30, 32 Dry film 11 Inner circuit opening 13 Dielectric layer 15 Thin copper layer 17 Patterned photoresist layer 19 Second electroplated metal layer 19a Circuit 19b Gold wire pad 19c Alignment target 23 Electroplated nickel layer 25 Solder resist layer 26 Immersion gold layer 27 Electroplated gold layer