TWI238480B - Manufacturing method of chip package carrier substrate - Google Patents

Abstract

A manufacturing method of chip package carrier substrate is introduced. It uses bottom plating to form copper columns and hence the bump pads with micro-opening as lifted to the surface of the solder resist. This method can match solder paste manufacturing process currently used to resolve the product scrap problems that the traditional semiconductor carrier substrate cannot deal with the pad pitch scaling and poor solder pasting due to small bump pad opening, low yielding rate carrier substrate fabrication and not effectively combined with the pad during packaging. This method can provide carrier substrate circuit layout with ultra-high density and a complete solution that aims at the structural requirements of the design and package for ultra-high density chip in nanometer process.

Description

1238480 V. Description of the invention (1) [Technical field to which the invention belongs], especially, the invention relates to the design of a J-generation wafer of a semiconductor carrier board, a chip packaging carrier board, and a manufacturing method thereof in response to Increasing demand for packaging density. [Because there are many previous technologies, it has been updated, and now Chip) In addition • 1 3um chip carrier board speed has been reduced to board manufacturing packaging requirements have been reduced and the structure has been reduced] ^ #The increasing trend of thin and short electronic products, In addition, the technology of chips also rapidly increases the number of I / 0 chips. Relatively, F 1 i P has now adopted flip-chip sealing technology in high-end products, and the packaging density has continued to increase. From 〇.18un ^, due to the rapid innovation of professional wafer foundry technology ^, nanometer grades (90nm, 65nm.

1 Λ 也 "should be combined with the pad spacing (Bump PitcfU 1 is currently required to carry 150um or even 100um. The improvement in alignment accuracy in the process of ^ now still satisfies the interval. However, the next generation The product's chip packaging technology institute '' Super macro pitch carrier board to 100 μm

Known technology I is no longer sufficient to support this chip packaging demand ’, so it is imperative to develop new carrier board structures and manufacturing methods to provide solutions. The conventional wafer carrier board structure is generally a multilayer printed circuit board with two to eight layers. The material used is ceramic or organic materials, and the circuit conduction of the multilayer structure is based on mechanical drilling or laser drilling. , Then pull the wire to make the bump bump of the chip connection bump (Bump), and then set the solder pad area with Solder Resist, and finally

Page 5 1238480 V. Description of the invention (2) Solder is applied to the steel plate printing method. When the distance between the wafer and the bonding pad is reduced from 200 um to 100 um, the wiring between the bonding pads will cause the limited pad opening area to be too small (it will be quickly reduced by the diameter of 100 um). Resistors and traditional exposure and development equipment have insufficient process capability to manufacture, and the printing technology is limited due to the solder mask openings being too small, so that the printing solder cannot be filled into the solder pads embedded in the solder resist. Or the short circuit can be caused by the shrinkage of the pitch during printing, which will prevent the solder from filling into the opening. There are two known methods for setting limit pads. One is to use solder resist (Solder Resist Defined Lands), and the other is to use metal pads (Metal Defined Lands). The first figure is a schematic diagram of the limitation of the conventional solder resist. The second figure is a schematic diagram of the limitation of the metal surface by the conventional method. As shown in the first figure, because the width of the solder pad 101 is too small (less than 60um), the solder 102 cannot be pressed down into the solder pad 101 by printing, resulting in the solder 102 and the solder pad 1. There is a gap between 0 and 1, which will affect the welding quality. As shown in the second figure, the solder resist 200 between the two solder pads 201 is too small (less than 75um), and the area of the solder resist 2 0 2b is insufficient. This results in insufficient adhesion and peeling. At the same time, if it is not possible to embed the solder pad under the solder resist, raise the position to the solder resist, because the potting (U nder F i 1 1) can not be successfully filled under the chip during packaging, or due to the amount of solder (Solder Volume) Insufficient bonding strength. Therefore, the conventionally known manufacturing method cannot make tiny opening connection bumps on a wafer carrier.

Page 6 1238480 V. Description of the invention (3) Therefore, it is necessary to improve the conventional wafer carrier board manufacturing method to solve the limitations and problems caused by the conventional technology. [Summary of the Invention] Based on the lack of the above-mentioned conventional technology, the first disclosure of the present invention provides a method for manufacturing a wafer-package carrier board, which mainly consists of opening a limited pad area by means of CCD fine-drag alignment laser drilling, and then Apply conductive pad electroplating (Bottom Plating) metal plating to make metal pillars, such as Copper Column, to raise the height of the bumps and solder pads buried in the solder resist to the surface of the solder resist, and use it as the surface. Treatment (such as nickel / gold plating, tin-lead, anti-oxidation treatment, etc.). In this way, metal pillars can provide a cushioning function for material stress changes at high temperatures of the package, and can also solve the problems of insufficient bonding pad strength and printing technology limitations that cannot be applied with solder. At the same time, this method can also raise the position of the pad to the surface, replacing the conventional method, it is easy to bury the pad in the solder resist. This structure is also helpful to the potting process after the IC is combined during the packaging process, which can greatly improve the flow resistance. Trouble, to solve the problem of ultra-macro IC packaging. This method can provide higher chip packaging density and yield, and provide a solution in the manufacture of carrier boards in response to the next generation wafer nanotechnology to produce ultra-high-density IC chips and package structural requirements. [Embodiment] The third figures (A)-(V) are schematic diagrams showing the manufacturing steps of a chip package carrier according to the present invention. And with the detailed description, as an embodiment of the present invention:

1238480 V. Description of the invention (4) The third diagram (A)-(C) shows a step of providing a carrier board, as shown in the third diagram (A) 'Including a carrier board 301' The carrier board 301 may be an organic material Such as Bisaleimide Triazine (BT), even made of ceramic materials. A first metal layer 302 a and 3 2 2 b are formed on the surface of the carrier plate 301 in advance. The first metal layers 3 2 a and 3 2 b may be copper (Cu). Next, as shown in the third figure (B), a plurality of carrier board through holes 3 03 are formed in advance on the carrier board 301. As shown in the third figure (C), a first metal-plated layer 304 is formed in the first metal layer 30 2 and the carrier board through holes 3 03. The first metal-plated layer 30 4 may be copper (Cu). The second pictures (D)-(F) show a step of forming an inner layer circuit. As shown in the third picture (D) 'the image of the dry film 3 0 5 is used as the screen to place the first metal plating layer 3 0 4 and The first metal layer 302 is etched, and the remaining portion forms the inner layer circuit 306, as shown in the third figure (E). A black oxide inner layer circuit layer 307 forming step is a method of oxidizing the inner layer circuit 306. The black oxide inner layer circuit layer 307 is formed on the surface of the inner layer circuit 306, as shown in the third figure (F). . The third figure (G)-(H) shows a 9-9 step of forming a dielectric layer 308 and a second metal layer, as shown in the third figure (G) 'is covered with a dielectric substance and a metal foil A dielectric layer ^ 8 and a second metal layer 309 are formed on the inner layer circuit 3 06 by a high-temperature compression method. The dielectric layer 308 may be made of an organic material such as ^ ㈣nimide BT) or other dielectric substances. The metal layer 309 may be made of copper (Cu) M.之 饴, ^ Α ΐ # 故人 η 狂。 After that, as shown in the third figure (i), Ran Huan transformed the second metal layer 3 0 9 to form the first full-thickness η R-R r τ, γM, Chengdi-metal layers 3 9a and 3 9b. The second figure (I)-(N) shows that a bin becomes a common φ a 同-the same, ^ ^ 0 Ma t Cheng; 丨 the electrical layer through hole 3 1 2 steps, the first picture (I) to dry Film 3l〇 (j) rv Film) • The image of Dry h ίΠ〇 is a laser mask

Page 8 1238480 V. Description of the invention (5) 311, as shown in the third picture (j) + send ^ Sheng ^ go to the third picture (K), in the dielectric Li i: ί :: " Hole 312, and through the dielectric layer through holes 3 1 ZO with electroless metal plating (such as Cu) and report the goods ## The third picture (L) of the household caterpillar. 313, such as eight Φ 厗 捅 π 士 * Di Yi 0 (M) 'Using a dry film 3, 5 to fill the dielectric layer vias with a metal 314', where the metal can be as shown in the third figure (N).硐 tu C tuj forms the dielectric so that this carrier can: This may include repeating the formation of the inner circuit layer and the second metal n step and the formation of & electrical layer through-hole steps = y on the board has a plurality of layers. The hole structure is formed by the button υ η artificially—combined with the pad circuit layer step, which is the two μ road layer 31_3i6b, where the layer on the load surface Λ ❹ is the bump side, located on the bottom of the carrier board, f The pad circuit layer is on the solder ball side; as shown in Figure (P), a plurality of knots are not formed: = :, a solder resist is applied, and the bump ㈡L 塾 line =: and a plurality of anti-fresh resists are formed The combination of welding 318. 7 a m Q ^ not Application of anti-electric mineral resistance agent 3 1 9 on the anti-freshness inhibitor 2 and forming a plurality of tiny openings 32 o with a CCD para-laser. ㈣ΓΛ / ί 'A plurality of metal pillars are formed by a bottom electro-mineral method. 321 Yu Erji small opening 3 2 0, the bottom of the stomach electroplating method uses these small openings 3 2 0 as the cathode, and through the dielectric through hole 312 in the metal μ push the board through hole 3 0 3 from the carrier board Conduction is performed under 301, so that metal ions such as copper (Cu) in the plating solution can be deposited into the minute openings 32 to form the metal pillars 321 ', and the height and height of the metal pillars 321 are raised to resist plating.

1238480 V. Description of the invention (6) Surface of resist 3 1 9 The third picture — 丨 3 丨 ^ All the surface treatment steps, first remove the anti-electroplating, the anti-resistance agent 317, on the two sides of the carrier board 301 with thin gold ',' " the metal columns out 321 and these are combined with 318 pads and solder ball side circuit layers. 〇xing # Ilf, (T), the step of forming a solder ball pad soldering zone is connected to the ball side with a solder resist 322 to form a plurality of solder ball pads 323. As shown in the second figure (U), the surface treatment step is performed on the metals ^ 32, the combination pads 318 and the solder ball pads 323, and Π, redundant accumulation / gold, error-free solder With organic protective film. Brother Eryuan IV), as shown in the figure below, the metal pillars 321 are formed by welding and convex transfer. The series of zinc is 325 ^ ^ ^ 326 ^ t ^, Λ326 '^ ^ ^ # 鲜 枓 3 25Τ It is general tin-lead solder or lead-free solder. Above, for those who are familiar with the art, they should be clear and can engage in non-departure: invention: modification and change of God and scope. Therefore, it means that the modifications and changes mentioned in this J Ming and the present invention should be included; the right «

Page 10 1238480 Brief description of the diagram The first diagram is a schematic diagram of the limitation of the conventional solder resist. The second figure is a schematic diagram of the limitation of the metal surface. The third figures (A)--(V) show the manufacturing steps of the chip package carrier board of the present invention. [Description of component symbols] 10 1 solder pad 1 0 2 solder 2 0 1 solder pad 2 0 2 a solder resist 2 0 2 b solder resist 2 0 3 solder 3 0 1 carrier board 3 0 2a first metal layer 3 0 2b first metal layer 3 0 3 carrier board through hole 3 0 4 first mineral metal layer 3 0 5 dry film 3 0 6 inner layer circuit 3 0 7 black oxide inner layer circuit layer 3 0 8 dielectric layer 3 0 9 Two metal layers 3 1 0 dry film 3 11 laser photomask

1238480 Brief description of the drawing 3 1 2 Dielectric layer through hole 3 13 Second metal plating layer 3 14 Metal 3 1 5 Dry film 3 1 6 a Bond pad circuit layer 3 1 6 b Bond pad circuit layer 3 1 7 Solder resist 3 1 8 Combined with solder pad 3 1 9 Anti-plating resist 3 2 0 Micro openings 321 Metal pillars 3 2 2 Solder resist 3 2 3 Fresh balls 3 2 4 Surface treatment 3 2 5 Solder 3 2 6 Solder Pad bump

Page 12

Claims (1)

i 1238480 VI. Application for Patent Scope 1. A method for manufacturing a chip package carrier board, comprising: providing a carrier board with a bonding pad circuit layer, wherein the bonding pad circuit layer is provided with an anti-plating resist and has a plurality of A combination of bonding pads and micro openings; and a plurality of metal pillars formed in the micro-openings by a bottom plating method, so that the height of the metal pillars is raised to the surface of the anti-plating resist. The manufacturing method includes providing a carrier board with a bonding pad circuit layer, further comprising: forming a first metal layer on the surface of the carrier board in advance, and forming a plurality of carrier board through holes on the carrier board, and A first metal layer is formed on the surface of a metal layer and the through hole of the carrier board. The step of forming the inner layer circuit is to etch the first metal plating layer and the first metal layer to form a trench. The unetched portion forms the inner layer circuit. Then, a blackened inner layer circuit layer is formed on the surface of the inner layer circuit. The step of forming a dielectric layer and a second metal layer is to fill the through holes and the trenches of the carrier with a dielectric substance. And cover the entire internal circuit, and then a metal foil is formed on the surface of the dielectric layer, and then the metal foil is thinned to the second metal layer; the step of forming a dielectric layer via is to form a plurality of dielectric layer vias. Forming a second bond metal layer in the dielectric layer vias, and filling the dielectric layer vias with metal; forming a bonding pad circuit layer step, forming the bonding pad by etching. Circuit layer, wherein the bonding pad circuit layer on the upper surface of the carrier board is a bump side, and the bonding pad circuit layer on the lower surface of the carrier board is a solder ball side; Page 13 1238480 Case No. 93109350 Amendment VI. Scope of patent application and formation of multiple bonding pads on the junction side 3. If the patent application step includes: Performing the formation of the speed worm road layer and performing the formation of the plural number 4介 与 介 5 · If the formation of electric flux belongs to ion 6 · If the metal is removed from the anti-etching, the surface of the bare fresh ball is welded on the surface of a plurality of welds. The block pad bump patent line through-hole through-hole patent metal carrier board deposition patent is a copper bonding pad area step, which is a step of applying a solder resist on the bump line layer and forming a plurality of bonding pads. The manufacturing method of the first item, the bottom plating method is followed by a plating resist step, and the two sides of the carrier board are quickly stepped out of the metal pillars and the bonding pads and the solder ball side by a thin metal step. Applying a solder resist on the solder ball side, a ball pad; and a step of performing the steps at the metal pillars and the bonding pads to transfer the solder to the metal pillars to form a block And level the pad bumps. The manufacturing method of the second item further includes a repeating step, a step of forming a dielectric layer and a second metal layer, and a forming step, so that the carrier board can have a plurality of layers of internal circuit structures. The manufacturing method of the first item, wherein the bottom electroplating method uses the bottom of the micro openings as a cathode, and conducts electricity through the through hole through the underside of the carrier board, so that gold in the plating solution reaches the micro openings A metal pillar. The manufacturing method of item 5 wherein the ion in the plating solution and the material of the metal pillar are copper. Page 14 1238480 _Case No. 93109350_Year_Month__ VI. Scope of Patent Application 7. For the manufacturing method of item 1 of the patent scope, the carrier board can be organic materials such as Bisaleimide Triazing (BT) and ceramic materials. 8. The manufacturing method as described in the first item of the patent application, wherein when the height of the metal pillars is raised to the surface of the anti-plating resist, they can be used together with the height of the anti-plating resist. 9. The manufacturing method according to item 1 of the patent application range, wherein the height of the metal pillars can be higher than the height of the plating resist when it is raised to the surface of the plating resist. 10. The manufacturing method according to item 1 of the patent application range, wherein the height of the metal pillars can be lower than the height of the plating resist when the height of the metal pillars is raised to the surface of the plating resist. 1 1. The manufacturing method according to item 2 of the scope of patent application, wherein the material of the first metal layer _ can be copper. 1 2. The manufacturing method according to item 2 of the scope of patent application, wherein the material of the first metal plating layer may be copper. 1 3. The manufacturing method according to item 2 of the scope of patent application, wherein the material of the second metal layer may be copper. 1 4. The manufacturing method according to item 2 of the patent application scope, wherein the material of the second metal plating layer may be copper. 1 5. The manufacturing method according to item 2 of the scope of patent application, wherein the metal filled in the through holes of the dielectric layers may be copper. 1 6. The manufacturing method according to item 3 of the patent application scope, wherein the solder can be tin ® lead solder and lead-free solder. 1 7. The manufacturing method according to item 1 of the patent application scope, wherein the chip package carrier is a flip chip carrier. Page 15