TWI239698B - Structure of memory card and producing method thereof - Google Patents

Structure of memory card and producing method thereof Download PDF

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Publication number
TWI239698B
TWI239698B TW093130326A TW93130326A TWI239698B TW I239698 B TWI239698 B TW I239698B TW 093130326 A TW093130326 A TW 093130326A TW 93130326 A TW93130326 A TW 93130326A TW I239698 B TWI239698 B TW I239698B
Authority
TW
Taiwan
Prior art keywords
memory
memory card
cavity
item
internal contacts
Prior art date
Application number
TW093130326A
Other languages
English (en)
Other versions
TW200612628A (en
Inventor
Cheng-Hsien Kuo
Ming-Jhy Jiang
Cheng-Kang Yu
Hui-Chuan Chuang
Original Assignee
Advanced Flash Memory Card Tec
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Flash Memory Card Tec filed Critical Advanced Flash Memory Card Tec
Priority to TW093130326A priority Critical patent/TWI239698B/zh
Priority to US10/904,975 priority patent/US7205644B2/en
Priority to KR1020040108990A priority patent/KR100695864B1/ko
Priority to JP2005010640A priority patent/JP2006107420A/ja
Application granted granted Critical
Publication of TWI239698B publication Critical patent/TWI239698B/zh
Publication of TW200612628A publication Critical patent/TW200612628A/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5388—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/181—Encapsulation

Description

rf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種記憶裝置及其製造方法，且特 別是有關於一種記憶卡及其製造方法。 【先前技術】 近年來，電子積體電路技術與材料進步快速，其晶 ^之，積日益縮小，但功能卻日益強大，應用之廣泛可說 疋無遠弗屆，因此利用電子積體電路所生產之產品已漸朝 向輕薄短小m ’舉凡電传典、触減及各種數位 產品等等不勝枚舉。而且，因為晶片封裝技術之日益成熟， T面亡已有將單―晶片或多晶片封裝於厚度相當薄之卡片 藉由晶片内可儲存大錄位資料的特性，形成一種比 性記錄雜之體積更小的可抽換式記賴。此種電 子媒體統稱為記憶卡。 憶卡記憶卡的結構。請參照圖1，此記 ^130 u 11G、—記憶體晶片12G、—封膠材 塑r體14〇。基板u〇具有-第-表面112 外面矣 114 ’其中第—表面112具有多個對 外接點116盥内邱接點f ^ 口円。丨接點118，對 \ 係電性連接。此外，記㈣曰 片U0为別與内部接點118電性 W體日日 包覆記恃體日以20L 另外，封膠材料130 14〇則藉由熱轉Η2覆蓋於第：^^8。’而塑膠卡體 然而近幾年來’由於對#料儲存容量的需求日益增 -^-^1 ^ ^^^^twf.doc/006 加，習知的記憶卡的資料儲存容量已漸漸不符合所需。因 此’如何增加記憶卡的資料儲存容量之需求已成為日益迫 切的問題。 【發明内容】 ^月的目的；^是在提供—種記憶卡結構，以增加 記憶卡的資訊儲存容量。 ^明的3 —目的是提供_觀憶卡製造方法，以 製造上述之記憶卡結構。 本發明提ih-種記憶卡結構 ίΓ:?晶片、一封膠材料以及-上=。 二表面第一表面及對應之-第二表面，其中第 表面/、有，騎接點，第二表面 別斑内部接2憶體晶片堆疊於凹穴中，且記憶體晶片分 應之内部接點。超薄塑膠卡體覆蓋 塑膠卡體對應記憶體晶片的位盍置於 0.15mm。 具厚度介於0.1〜 依照本發明所述之記憶卡結構， 體外型例如符合钱型多雜記憶 ^之㈣塑膠卡 片例如係藉由多條導線電性連接格^記憶體晶 二 rr，二 如係以封膠材料彼此間隔。應之—個記憶體晶片之間例 Ι239·__ 依照本發明所述之記憶卡結構，上述之封膠材 如包括環氧樹脂或聚隨亞胺。此外，超薄塑膠卡體之^例 例如係選自於由聚碳酸酯（PC)、聚笨乙烯(PS)及内才_料 一稀-苯乙稀樹脂(ABS)所組成之族群或其他合、尚 丁 型工程塑膠。 〃 σ ^ '泛用 本發明提出一種記憶卡製造方法，此記憶卡努造 法包括下列步驟：首先，提供一基板，此基板具有二第一 表面及對應之一第二表面。其中，第一表面具有多個對外 接點’第二表面具有至少一凹穴，而凹穴周緣配置有多個 内部接點，且對外接點與内部接點係電性連接。 接著，將多個記憶體晶片堆疊於凹穴中，並分別電 性連接記憶體晶片與内部接點，且進行一封膠步驟，以— 封膠材料包覆記憶體晶片及對應之内部接點。之後，提供 一超薄塑膠卡體，覆蓋於第二表面，並與基板結合。其中， 超薄塑勝卡體對應記憶體晶片的位置之厚度介於〇」〜 0.15mm 〇 依照本發明所述之記憶卡製造方法，上述之超薄塑 膠卡體與基板結合後，其外型符合智慧型多媒體記憶卡 (Smart Media Card)之規格。此外，電性連接記憶體晶片 與内部接點的方法包括打線。 依照本發明所述之記憶卡製造方法，上述之記憶體 晶片堆疊於凹穴的方式’例如係將f己憶體晶片兩兩成一組 分別堆疊於凹穴中。此堆疊方法，包括下列步驟··首先， 將其中之一記憶體晶片配置於凹穴中。接著，電性連接記 14296twf.doc/006 憶體晶片與部分内部接點。然後，進行封膠步驟之第一階 段，以封膠材料包覆記憶體晶片及對應之内部接點。之後， 將另一記憶體晶片配置於封膠材料上。再來，電性連接另 -記憶體晶片與部分内部接點。然後，進行封膠步驟之第 二階段，以封膠材料包覆另一記憶體晶片及對應之内部接 點。 ’ 依照本發明所述之記憶卡製造方法，上述之電性連 接記憶體晶片與内部接點的方法包括打線。此外，封膠步 驟的方法包括點膠(dispensing)。另外，超薄塑膠卡體例如 係藉由灌模的方法製成，灌模的方法包括下列步驟：首先， 提供一模具及一真空幫浦，模具具有一模穴，真空幫浦連 通至模穴。之後，進行一射出灌模步驟，以一填料機構輸 入一灌模材料於模具之模穴中，並同時藉由真空幫浦從模 具之模穴中吸出氣體。 ' 本發明之記憶卡因於基板上設有凹穴，且使用一超 薄塑膠卡體，故能將多個記憶體晶片堆疊於凹穴中，因此 旎增加記憶卡的資訊儲存容量。此外，超薄塑膠卡體於製 作時，係使用真空幫浦對模穴進行抽氣，所以可製作厚^ 極薄的超薄塑膠卡體。 又 為讓本發明之上述和其他目的、特徵和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 圖2繪示為本發明之一實施例的記憶卡結構圖。請 1239698 14296twf.doc/006 參照圖2，此記憶卡2〇〇包括一基板21〇、多個記憶體晶 片220、一封膠材料230以及一超薄塑膠卡體240 ◦基板 210具有一第一表面212及對應之一第二表面214，其中 第一表面212具有多個對外接點216，而第二表面214具 有至少一凹穴202，且凹穴202周緣配置有多個内部接點 218 ’對外接點216與内部接點218係電性連接。另外， 多個圯憶體晶片220堆疊於凹穴202中，在本實施例中， 記憶體晶片220係以兩兩成一組而堆疊於凹穴2〇2中，且 兄憶體晶片220分別與内部接點218電性連接。 如圖2所繪示，封膠材料230包覆記憶體晶片220 及對應之内部接點218，而超薄塑膠卡體240覆蓋於第二 表面214 °其中’超薄塑膠卡體240對應記憶體晶片220 的位置之厚度介於0.1〜0.15mm。 圖3A〜圖3C繪示記憶卡内的記憶體晶片於平面上 之排列方式。請同時參照圖3A〜圖3C，記憶體晶片220 配置於6己憶卡200上的數目如圖3A所示可為1組。或者， 記憶體晶# 220可如圖3B所示，以並列的方式配置於記 憶卡200上。又或者，4組如記憶體晶片22〇可如圖sc 所不，以陣列的方式配置於記憶卡200上。 圖4Α〜圖4D繪示本發明之一實施例的記憶卡製造 方法。百先，請參照圖4Α，提供一基板21〇，基板21〇 具有第一表面212及對應之第二表面214。其中，第一表 面212具有多個對外接點216，用以和外界進行資訊交換， 而第一表面214具有至少一凹穴202'，凹六202周緣配置 1239698 14296twf.doc/006 有多個内部接點218，且對外接點216與内部接點218藉 由基板210上的圖案化線路（未繪示）及盲孔（未繪示）" 而電性連接。 接著’請芩照圖4B，將記憶體晶片222配置於凹穴 202中，並可利用打線的方式將記憶體晶片222與部分内 =接點218進行電性連接，而導線226例如為金線或鉬線 等電阻抗值較小的材料。之後，例如利用點膠或其他合適 的封裝方式將封膠材料23〇，例如為環氧樹脂(ep〇xy)或聚 ^亞胺(polyimide)包覆記憶體晶片222及對應之内部接點 、，之後，請參考圖4C，將記憶體晶片224配置於封膠 材料230上，並可利用打線的方式將記憶體晶片224與部 分内部接點218做電性連接。 ^ " 丹术，請參考圖 叫… 71〒珂胗何科』川例如利用點膠 224、Π庙適的封裝方式將封膠材料230 &覆記憶體晶^ 224及對應之内部接點218。 卡體i?-參ί圖2，利用熱溶膠242將超薄塑膠 邻槿件L—面214上，以保護記憶卡2〇0的内 卡體240的特徵在於對應於記 匕體日日片224的位置，其厚度介於 料為選自於由聚碳酸酯(PC)、聚 八 婦-苯乙稀樹脂陶所組成)之以 工程塑膠。 其他合適的泛用型 其外型例如係符合智慧 於記憶卡200製作完成後， I239698w f.doc/006 型多媒體記憶卡之規格。但是，本實施例之記憶卡200的 外型亦可以製作成符合其他種類的規格，例如CF記憶卡
(Compact Flash Memory Card)、MS 記憶卡(Memory Stick Card)、MS Duo 記憶卡(Memory Stick Duo)、xD 記憶卡(xD
Picture Card)、MMC 記憶卡（Multi Media Card)、RS MMC 記憶卡(Reduced Size Multi Media Card)、SD 記憶卡（Secure Digital Card)、Mini SD 記憶卡(Mini Secure Digital Card)、 μ 記憶卡(μ Card)、RS μ 記憶卡(Reduced Size μ Card). ··等 其他類似功能之小型記憶卡。 為了製作出超薄塑膠卡體240，其用以製作超薄塑膠 卡體240的設備及方法必須經過特別的設計，圖5繪示為 超薄塑膠卡體的製作示意圖。請參照圖5，模具31〇具有 一模穴312，而模穴312的形狀對應於超薄塑膠卡體240 的外型。製作時，將灌模材料332藉填料機構330經由孔 洞316填入。在此同時，真空幫浦32〇將模穴312中的空 ^抽出，致使模穴312中的壓力降低。由於模穴312中的
壓力極低’所以灌模材料332能均勻地充滿整個模穴312， 使得製作出來的超薄塑膠卡體具有厚度極薄且材質均 勻的特性。 、 值得注意的是，在本實施例中，記憶體晶片係採用 、=成-組而堆疊在-起。⑽’本發明並不限於使用上 二:式將記憶體晶片進行堆疊，亦可以採較錯堆疊的方 二或者’在某些狀況下’亦不限於兩兩成_組地堆疊在 也可以夕個（大於兩個）成一組地堆疊在一起，或 11 Ι239698„ 單獨只置放一記憶體晶片。 知上所述’在本發明之記憶卡因於 且使用-超薄塑踢卡體，故能將多個記憶體， 穴中，因此能增加記憶卡的資訊儲 片=凹 膠:體於製作時’係使用真空幫浦對模穴進行抽氣塑 可製作厚度極薄的超薄歸卡體。。 仃抽孔’所以 雖然本發明已以較佳實施例揭露如上，然其 以限定本發明，任何熟習此技藝者，在不脫離本 神和範圍内，當可作些許之更動與潤飾，因此本發明之: 護範圍當視後附之申請專利範圍所界定者為準。 ” 【圖式簡單說明】 圖1繪示一種習知記憶卡的結構。 圖2繪示為本發明之一實施例的記憶卡結構圖。 圖3Α〜圖3C繪示記憶卡内的記憶體晶片於平面上 之排列方式。 圖4Α〜圖4D緣示本發明之一實施例的記憶卡製造 方法。 圖5繪示為超薄塑膠卡體的製作示意圖。 【主要元件符號說明】 100 ··記憶卡 110 :基板 112 :第一表面 114 :第二表面 116 :對外接點 12 1239698 14296twf.doc/006 118 :内部接點 120 :記憶體晶片 130 :封膠材料 140 :塑膠卡體 142 :熱熔膠 200 ··記憶卡 202 :凹穴 210 :基板 212 :第一表面 214 :第二表面 216 :對外接點 218 :内部接點 220, 222, 224 :記憶體晶片 230 :封膠材料 240 :超薄塑膠卡體 242 :熱熔膠 310 :模具 312 :模穴 316 :孔洞 320 ·•真空幫浦 330 :填料機構 332 :灌模材料

Claims (1)

  1. wf.doc/006 申請專利範圍 1. 一種記憶卡結構，包括： 一基板，具有一第一表 中該第一表面具有多數個對外接胃/，==二表面’其 一凹穴’該凹穴周緣配置有多部:表=有至少 點與該些内部接點電性連接； 卩接2，该些對外接 多數個記憶體晶片堆疊於該凹穴中立 晶片分別與該些内部接點電性連接； Μ二圮饫體 -封膠材料，包覆該些記憶體 部接點；以及 71夂對應之该些内 一超薄塑膠卡體，覆蓋於該第二表 〇塑It對應該些毫_位置，其厚度介 2. 如申請專利範圍第！項所述之記憶卡結構，盆中續 超薄塑勝卡體外㈣合智慧型多舰記憶卡之規格。、" 3. 如申請專利範圍第1項所述之記憶卡結構，其中該 些記憶體晶片係藉由多數條導線€性連接該些内部^點二 4. 如申請專利範圍第3項所述之記憶卡結構，其中該 些導線包括金線及鋁線其中之一。 X 5·如申請專利範圍第1項所述之記憶卡結構，其中該 些δ己憶體晶片兩兩成一組，分別堆疊於該凹穴中。 6·如申請專利範圍第5項所述之記憶卡結構，其中對 應之該二個記憶體晶片之間係以該封膠材料彼此間隔。 7·如申請專利範圍第1項所述之記憶卡結構，其中該 14 I23969Jtw f.doc/006 封膠材料包括環氧翻旨及賴亞胺其中之一。 超薄塑二專利㈣第1項所述之記憶卡結構，其中該 iPU% X -之材料係選自於由聚碳酸酯(PC)、聚苯乙烯 ==‘丁二秦笨乙稀樹脂(abs)所組成之族群。 曰種圯憶卡製造方法，包括： 基板，该基板具有一第一表面及對應之一第 面具有至二:忒第—表面具有多數個對外接點，該第二表 該：對外該凹穴周緣配置有多數個内部接點， —耵卜接點與该些内部接點電性連接； 連接Ϊ :3 2片堆疊於該凹穴中’並分別電性 驟，以些内部接點，且進行一封膠步 部接點· r > ;〃，包覆該些記憶體晶片及對應之該些内 板^供=薄轉卡體，錢於該第二表面，與該基 置、；ΐ::=， 其中該申5月專利乾圍第9項所述之記憶卡製造方法， 多媒與該基板結合後，其外型符合智慧型 其中^申^專Γ範圍第9項所述之記憶卡製造方法， 打線。 憶體晶片與該些内部接點的方法包括 其中專鄕㈣9销敎記料製造方法， 中》亥些讀體晶牌疊於該凹穴的方式，細該些記憶 15 f.doc/006 1239698 14296tw 體晶片兩兩分成一組，分別堆疊於該凹穴中。 13·如申請專利範圍第12項所述之記憶卡製造方法， 其中母對應^一 3己憶體晶片的堆疊方法，包括_ · 將其中之一 5己憶體晶片配置於該凹穴中； 電性連接该圮憶體晶片與部分該些内部接點； 進行該封膠步驟之第一階段’以該封膠材料包覆該 記憶體晶片及對應之該些内部接點； 將另一記憶體晶片配置於該封膠材料上； 電性連接该另一記憶體晶片與部分該些内部接點； 以及 _ 進行該封膠步驟之第二階段，以該封膠材料包覆該 另一記憶體晶片及對應之該些内部接點。 14·如申請專利範圍第13項所述之記憶卡製造方法， 其中電性連接该些記憶體晶#與該些内部接點的方法包括 打線。 15·如巾請專利·第9項所述之記憶卡製造方法， ”中該封膠步驟的方法包括點膠(dispensing)。 包括 中申圍第9销叙記憶卡料方法，其 中該糾_切储由賴的方法製造，物模的方法 提供—模具及—真空幫浦，該模具具有 〜 /、空幫浦連通至該模穴_;以及 、八〇 進行—射出灌模步驟，以一填料機構， 二二中’並同時藉由該真空幫浦從該模
TW093130326A 2004-10-07 2004-10-07 Structure of memory card and producing method thereof TWI239698B (en)

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TW093130326A TWI239698B (en) 2004-10-07 2004-10-07 Structure of memory card and producing method thereof
US10/904,975 US7205644B2 (en) 2004-10-07 2004-12-08 Memory card structure and manufacturing method thereof
KR1020040108990A KR100695864B1 (ko) 2004-10-07 2004-12-20 메모리 카드 구조 및 그 제조 방법
JP2005010640A JP2006107420A (ja) 2004-10-07 2005-01-18 メモリカード構造とその製造方法

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TW200612628A TW200612628A (en) 2006-04-16

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Cited By (1)

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TWI405129B (zh) * 2005-11-14 2013-08-11 Tyco Electronics France Sas 智慧卡本體、智慧卡及其製程

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WO2007026392A1 (ja) 2005-08-30 2007-03-08 Spansion Llc 半導体装置およびその製造方法
TW200739756A (en) * 2006-04-03 2007-10-16 qin-dong Liu Method of packaging flash memory cards
US8110899B2 (en) * 2006-12-20 2012-02-07 Intel Corporation Method for incorporating existing silicon die into 3D integrated stack
US11500329B2 (en) * 2020-06-10 2022-11-15 Canon Kabushiki Kaisha Cartridge and manufacturing method of cartridge

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KR100209782B1 (ko) * 1994-08-30 1999-07-15 가나이 쓰도무 반도체 장치
KR100335717B1 (ko) * 2000-02-18 2002-05-08 윤종용 고용량 메모리 카드
KR20020007576A (ko) * 2000-07-18 2002-01-29 윤종용 칩 온 보드 타입의 메모리 카드
KR20030014863A (ko) * 2001-08-13 2003-02-20 삼성전자주식회사 적층된 초박형 패키지
JP3507059B2 (ja) * 2002-06-27 2004-03-15 沖電気工業株式会社 積層マルチチップパッケージ
KR20030083306A (ko) * 2002-04-20 2003-10-30 삼성전자주식회사 메모리 카드

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI405129B (zh) * 2005-11-14 2013-08-11 Tyco Electronics France Sas 智慧卡本體、智慧卡及其製程

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KR20050099453A (ko) 2005-10-13
US7205644B2 (en) 2007-04-17
TW200612628A (en) 2006-04-16
JP2006107420A (ja) 2006-04-20
KR100695864B1 (ko) 2007-03-19
US20060077749A1 (en) 2006-04-13

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