TWI236048B - Method for flip chip bonding by utilizing an interposer with embeded bumps - Google Patents

Method for flip chip bonding by utilizing an interposer with embeded bumps Download PDF

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Publication number
TWI236048B
TWI236048B TW093132044A TW93132044A TWI236048B TW I236048 B TWI236048 B TW I236048B TW 093132044 A TW093132044 A TW 093132044A TW 93132044 A TW93132044 A TW 93132044A TW I236048 B TWI236048 B TW I236048B
Authority
TW
Taiwan
Prior art keywords
bumps
openings
interposer
item
wafer
Prior art date
Application number
TW093132044A
Other languages
English (en)
Other versions
TW200614321A (en
Inventor
Ming-Lun Ho
Chih-Ming Chung
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW093132044A priority Critical patent/TWI236048B/zh
Priority to US11/136,181 priority patent/US7098071B2/en
Application granted granted Critical
Publication of TWI236048B publication Critical patent/TWI236048B/zh
Publication of TW200614321A publication Critical patent/TW200614321A/zh

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Description

1236048 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種形成覆晶接合結構之方法，特別是一種 使用具有嵌合凸塊之中介層以形成覆晶接合結構之方法。 【先前技術】 參考圖1，顯示習知使用具有嵌合凸塊之膠帶型底膠 (underfill tape)之覆晶接合（flip chip bonding)方法。該習知 之方法如下所述，首先提供一晶片10，該晶片1〇具有一晶 片表面11，接著，黏附一膠帶型底膠（underfilltape)12於該 晶片表面11上。之後，以雷射鑽孔（laser drill)之方式形成 複數個開口 13於該膠帶型底膠12上，再以電鍍方s(plating) 形成複數個凸塊14於該等開口 13内，該等凸塊14之成分係為 63%重量的錫及37%重量的鉛，且該等凸塊14之高度係等於 该等開口 13之深度，因此該等凸塊14剛好填滿該等開口 13。 接著，提供一基板15，該基板15具有一基板表面16，該 基板表面16上具有複數個預錫球（pre_s〇ider)17，該等預錫 球1 7之位置係相對於該等開口丨3。接著，利用一壓合頭 (B〇ndHead)18壓合該晶片1〇與該基板15，其中該晶片表面 11係面對於該基板表面16，使該等預錫球17與該等凸塊η 相接觸。最後，施以高溫（例如2〇〇t：以上）高壓（例如3〇心） 使該等預錫球17與該等凸塊14熔接，以形成一覆晶接合。 «亥白知之方法最大的問題為對位不易。因為該等凸塊Μ 剛好填滿4等開口 13，目此該膠帶型底谬Η之下表面⑼與 該等預錫球17接觸之表面）係為-平整之表面。如此-來， 94162.doc 1236048 在壓合過程中該晶片10及該基板15容易產生相對移動而產 生偏移，因而容易造成產品瑕疵。 因此，有必要提供一創新且富進步性的覆晶接合方法， 以解決上述問題。 【發明内容】 本發明之主要目的係提供一種使用具有嵌合凸塊之中介 層（imerposer)(例如··膠帶型底膠或B階段膠材（B_stage matenal)等）之覆晶接合方法，其中該凸塊係未填滿該中介 層之開口而形成缺口，當進行壓合步驟時，基板上之預錫 求了真入^亥缺口，利用$亥凸塊與該預錫球間之自行對位能 力’可避免產生偏移現象。 為達上述目的，本發明提出一種使用具有嵌合凸塊之中 介層之覆晶接合方法，包括： (a) 提供一第一元件，該第一元件具有一第一表面； (b) 形成一中介層於該第一表面上； (c) 形成複數個開口於該中介層上； (d) 形成複數個凸塊於該等開口内，其中該等凸塊之高度 小於該等開口之深度； (e) 提供一第二元件，該第二元件具有一第二表面，該第 二表面上具有複數個預錫球，該等預錫球之位置係相對於 該等開口；及 ⑴壓合該第一元件與該第二元件，且使該等預錫球容置 於該等開口内而與該等凸塊連接。 【實施方式】 94l62.doc • 6 - 1236048 參考圖2至圖6,顯示本發明使用具有嵌合凸塊之中介層 之覆晶接合方法示意圖。本發明之方法如下所述，首先， 參考圖2，提供一第一元件（例如一晶片20)，該晶片20具有 一第一表面21。接著，附加一中介層（例如一膠帶型底膠22) 於該第一表面21上。然後，參考圖3，形成複數個開口 23 於該膠帶型底膠22上，以暴露出該晶片20上之銲墊（圖中未 示）。該形成開口 23之方式可以是雷射鑽孔或是曝光顯影等 習知之方式。 接著’參考圖4 ’以電鍍方式形成複數個凸塊24於該等開 口 23内。該等凸塊24之成分可以為63%重量的錫及37%重量 的鉛或疋5°/〇重量的錫及95%重量的船，或是該等凸塊24係 為金凸塊或是銅凸塊。此外，該等凸塊24之高度係小於該 等開口 23之深度，而形成複數個缺口 23 j，亦即該等凸塊μ 未填滿該等開口 23。 接著，參考圖5，提供一第二元件（例如一基板25)，該基 板25具有一第二表面26，該第二表面％上具有複數個預錫 球27，該等預錫球27之位置係相對於該等開口 23。該等預 錫球27之高度係等於或大於該等缺口 231之深度（亦即該等 口 23之深度與該等凸塊24之高度之差），以確保該等預錫 球27可以填滿該等缺口 231。 接著，利用一壓合頭（BondHead)28壓合該晶片2〇及該基 板25 ’其中該第_表面21係面對於該第二表面％，使該等 預錫球27容置於該等開口23内而與該等凸塊以相接觸：最 後進行一迴銲（reflow)步驟，施以高溫（例如2〇〇。〇以上）高壓 94162.doc 1236048 (例如30 Kgm)約20分鐘，使該膠帶型底膠22填滿該晶片2〇 及該基板25間之空隙，並使該等預錫球27與該等凸塊以熔 接，以形成一覆晶接合，如圖6所示。 在本實施例中，該第一元件係為一晶片，該第二元件係 為一基板。然而可以理解的是，該第一元件可以是一基板， 該第二元件則為一晶片，該膠帶型底膠係貼合於該基板 上。此外，還有一種情況為該第一元件係為一基板，該第 二元件係為一晶圓，該膠帶型底膠係貼合於該基板上，而 於該晶圓形成預錫球，待切割該晶圓以形成複數個晶粒之 後’再壓合該基板與該晶粒。 在本實施例中，該中介層係為一膠帶型底膠。然而可以 理解的是，該中介層亦可以是一3階段膠材，其係為一半固 態之膠，且其係鍍覆於該第一元件之第一表面上，之後需 要昇溫使其變成半固態，然後再進行上述之開口、植凸塊、 壓合及迴銲等步驟。值得注意的是，在迴銲步驟中，該B 階段膠材會變成一可塑性膠材，而填滿第一元件及第二元 件間之空隙，此時需持續一段時間（如3〇分鐘）之溫度（如 1 75 C )使該B階段膠材完全硬化不再變形。 上述實施例僅為說明本發明之原理及其功效，並非限制 本發明，因此習於此技術之人士對上述實施例進行修改及 變化仍不脫本發明之精神。本發明之權利範圍應如後述之 申凊專利範圍所列。 【圖式簡單說明】 圖1顯示習知使用具有嵌合凸塊之膠帶型底膠之覆晶接 94162.doc 1236048 合方法；及 圖2至圖6顯示本發明使用具有嵌合凸塊之中介層之覆晶 接合方法分解示意圖。 【主要元件符號說明】 10 晶片 11 晶片表面 12 膠帶型底膠 13 開口 14 凸塊 15 基板 16 基板表面 17 預錫球 18 壓合頭 19 下表面 20 晶片 21 第一表面 22 膠帶型底膠 23 開口 24 凸塊 25 基板 26 第二表面 27 預錫球 28 壓合頭 231 缺口
94162.doc

Claims (1)

1236048 十、申請專利範圍·· i 一種使料有嵌合凸塊之巾 ⑷提供—第—元件， l日接合方法，包括 70忏4弟一兀件具有一第一表面； ⑻形成-中介層（interpGser)於該第—表面上^ , (c)形成複數個開口於該中介層上； ⑷形成複數個凸塊於該等開口内，其中該等凸塊之高 度小於该等開口之深度； ⑷提供-第二元件’該第二元件具有一第二表面，該 弟-表面上具有複數個預錫球(㈣。lder)，該等預錫球 之位置係相對於該等開口；及 2·如請求項1之方法 元件係為一基板， 3·如請求項1之方法 元件係為一晶片， 4·如請求項1之方法 元件係為一晶圓 ⑴麼合該第一元件與該第二元件，且使該等預錫球容 置於該等開Π内而與該等凸塊連接。 第一元件係為一晶片，該第 其中該第一元件係為一基板，該第 其中該第一元件係為一基板，該第二 且步驟（e)之後更包括一切割該晶圓以 形成後數個晶粒之步驟，步驟（f)係壓合該基板與該晶粒。 5 · 士口呑月 工苜 1 夕· Htr 、、4· ** 之方去，其中該中介層係為一膠帶型底膠 (underfill tape) 〇 6· 士明求項丨之方法，其中該中介層係為一 b階段膠材 (B-Stage material)。 7·如明求項1之方法，其中該等預錫球之高度係等於該等開 94162.doc 1236048 口之深度與該等凸塊之高度之差。 8. 9. 10 11 12. 13 14 15 16 如睛求項1之方法’其中該等預錫球之高度係大於該等開 口之深度與該等凸塊之高度之差。 如請求項1之方法，其中步驟（b)中該中介層係貼合於該第 一表面。 如請求項1之方法’其中步驟（b)中該中介層係鍍覆於該第 一表面。 ^求項i之方法’其中步驟⑷中係以雷射鑽孔而形成該 :請求項i之方法’其中步驟⑷中係以曝光顯影方式而形 成該等開口。 7求項1之方法’其中步驟⑺之後更包括-迴銲（reflow) V驟使該等預錫球及該等凸塊熔合。 ^ 4項1之方法’其中該等凸塊之成分係為63%重量的 錫及37%重量的鉛。 該等凸塊之成分係為5%重量的錫 如凊求項1之方法，其中 及95%重量的鉛。 塊 _如吻求項1之方法，其中該等凸塊係為金凸 94162.doc
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