TWI234804B - Chip compressing mechanism and chip compressing process - Google Patents

Chip compressing mechanism and chip compressing process Download PDF

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Publication number
TWI234804B
TWI234804B TW093123205A TW93123205A TWI234804B TW I234804 B TWI234804 B TW I234804B TW 093123205 A TW093123205 A TW 093123205A TW 93123205 A TW93123205 A TW 93123205A TW I234804 B TWI234804 B TW I234804B
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Taiwan
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wafer
item
pressing mechanism
patent application
scope
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TW093123205A
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English (en)
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TW200606992A (en
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Chin-Chung Tu
Zheng-Jie Huang
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Chunghwa Picture Tubes Ltd
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Priority to TW093123205A priority Critical patent/TWI234804B/zh
Priority to US10/711,378 priority patent/US7219824B2/en
Application granted granted Critical
Publication of TWI234804B publication Critical patent/TWI234804B/zh
Publication of TW200606992A publication Critical patent/TW200606992A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T403/00—Joints and connections
    • Y10T403/32—Articulated members
    • Y10T403/32008—Plural distinct articulation axes
    • Y10T403/32041—Universal

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Micromachines (AREA)
  • Magnetic Heads (AREA)

Description

1234804 13816twf.doc 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片壓著機構(chip compressing mechanism)與晶片壓著製程，且特別是有關於一種可提升 晶片壓著接合之良率(yield factor)的晶片壓著機構與晶片 壓著製程。 【先前技術】 隨著電腦性能的大幅進步以及網際網路、多媒體技 術的高度發展，目前影像資訊的傳遞大多已由類比轉為數 位傳輸。為了配合現代生活模式，視訊或影像裝置之體積 曰漸趨於輕薄。傳統使用陰極射線管(Cathode Ray Tube， CRT)之顯示器雖然仍有其優點，但是由於内部電子腔的 結構’使得顯不器體積魔大而佔空間，且顯示時仍有輕射 線傷眼等問題。因此，配合光電技術與半導體製造技術所 發展之平面顯示器（Flat Panel Display，FPD)，例如液晶顯 示器（Liquid Crystal Display，LCD)、有機電激發光顯示器 (Organic Electro-Luminescent Display，OELD)或是電聚顯 示器（Plasma Display Panel，PDP)等，已逐漸成為顯示器產 品之主流。 在些平面顯不為中’大部分皆採用例如玻璃基板 等透明基板，而非其他電子產品所常用之電路板。因此在 平面顯示器所使用之晶片的接合技術方面，主要發展出g 片-電路板接合技術(Chip On Board，COB)、捲帶式晶片接 合技術(Tape Automated Bonding, TAB)與晶片_破璃接合技 I2348q34 6tw£d〇c 術(Chip On Glass, COG)等類型的接合技術。 圖1繪示為習知晶片-玻璃接合技術之示意圖。請參 照圖1，習知晶片-玻璃接合技術係先提供一晶片5〇於一 玻璃基板80上。以液晶顯示器為例，玻璃基板8〇可為液 晶顯示之薄膜電晶體(Thin Film Transistor，TFT)陣列基 板。其中，玻璃基板8〇上具有多個接觸墊(contactpad)82， 而晶片50上則配置有多個金凸塊52。此外，在玻璃基板 80與晶片50之間更配置有一異方性導電膜7〇(Anis〇tiOpic
Conductive Film，ACF)。在進行晶片5〇與玻璃美 接合時，係以一晶片壓著機構100對晶片50進"行熱壓著 (thermo compression)。如此一來，金凸塊52即可透過異 方性導電膜70内的導電粒子而電性連接至接觸塾幻，同 時藉由高溫來固化異方性導電膜70，以穩固金凸塊52與 接觸墊82之電性連接關係。 A … 但是，習知技術所使用之晶片壓著機構1〇〇由於提 供作用力F1之方向固定，因此若作用力F ^ 心乃问禾蛮 直於玻璃基板80時(如圖1所示），晶片5〇就無法以平疒 於玻璃基板80之方式與其接合，進而造成接合良率的= 降。再者，由於晶片接合已屬於平面顯示器之後段製程， 且接合失敗後重工(rework)不易，因此若晶片 需報廢接近完玉之平面訴ϋ。 U敗則 .為解決上述問題，目前各家平面顯示器的製造廠商 係在進行每一批晶片的熱壓著前，會先對晶片壓槿、° 行校準的動作。但是，這種校準動作不僅耗時，又會= 1234804 13816twf.doc 額外成本。而且，即使晶片壓著機構在經過校準後，也仍 無法確保晶片可以平行於玻璃基板之方式與其接合。由此 可知，晶片接合之良率的提升已成為平面顯示器的製造過 程中亟待解決的課題之一。 【發明内容】 本發明的目的就是在提供一種晶片壓著機構，適於 提高晶片壓著接合之良率。 本發明的再一目的是提供一種晶片壓著製程，適於 提南晶片壓著接合之良率。 本發明提出一種晶片壓著機構，其主要係由一加壓 (loading)組件、一壓頭(head)組件及一球體(gimbal)所構 成。壓頭組件設置在加壓組件之底下，且壓頭組件與加壓 組件之間具有一間隔(gap)。球體配置於加壓組件與壓頭 組件之間，並撐起加壓組件與壓頭組件之間的間隔。 本發明再提出一種晶片壓著製程，其係先提供一前 述之晶片壓著機構。接著，將至少一晶片置於一基板上。 之後，藉由晶片壓著機構將晶片壓著至基板上。其中，加 壓組件所施加之壓著力在經過球體之傳遞後，係以垂直基 板之方向而經由壓頭組件均勻施加在晶片上。 系；τ'上所述，本發明之晶片壓著機構與晶片壓著製程 中，由於壓頭組件在接觸晶片時可自動進行調整，因^可 提升晶片與玻璃基板接合之良率。 為讓本發明之上述和其他目的、特徵和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 489a1 3816twf.doc 說明如下。 【實施方式】 圖2繪示為本發明第一實施例之晶片壓著機構的剖 面示意圖，而圖3繪示為本發明第二實施例之晶片壓著機 構的剖面示意圖。請參照圖2與圖3，在此所舉例說明之 本發明兩種實施例的晶片壓著機構200, 300其主要構件 皆相同。晶片壓著機構200, 300主要分別由加壓組件21〇, 310、壓頭組件230, 330及球體280, 380所構成。壓頭組 件230，330設置在加壓組件210，310之底下，且加壓組 件210, 310與壓頭組件230, 330之間具有一間隔G而可 相對活動。壓頭組件230, 330可用以接觸並壓著至少一 晶片50(繪示於圖2中），以使晶片50電性接合至一基板 80(繪示於圖2中）。球體280, 380配置於加壓組件21〇, 310 與壓頭組件230, 330之間，並撐起加壓組件21〇, 310與 壓頭組件230, 330之間的間隔G。 如此一來，由於加壓組件210，310及壓頭組件230, 330係分別與球體280，380進行點接觸，且加壓組件21〇, 310與壓頭組件230, 330之間存在間隔g，因此當壓頭組 件230, 330受到外力作用時，即可相對於加壓組件2丨〇, 3 i〇 產生適當的旋轉及/或位移。 另外，晶片壓著機構200, 300中，加壓組件21〇, 31〇 例如分別具有一凹槽212, 312，且球體28〇, 38〇可藉由凹 槽212,312之作用而適當定位於其中。 接著請參照圖2 ’此貫施例之壓頭組件230例如具有 I2348〇46twfdoc -卡置槽232 ’而加壓組件2财靠近壓頭組件23〇之部 分的尺寸係大於卡置槽232之開口，因此加壓組件21〇在 靠近壓頭組件230之部分可卡置於卡置槽232内。在此實 施例中，壓頭組件230例如至少由一墊片25〇及一環片24〇 所構成。球體280例如係接觸墊片25〇。環片24〇例如與 墊片250四相互固接。其中，環片24〇之外圈係接觸塾片、 250，而環片240之内圈例如未接觸墊片25〇而共同構成 前述之卡置槽232。為使球體28〇可獲得適當的定位，墊 片250可更具有一凹槽252,而球體28〇即可適當地定位 於凹槽252内。 此外，由於在晶片-玻璃接合技術中，一般除了對晶 片50加壓外也會同時對晶片5〇加熱，因此壓頭組件230 可更增加一加熱板260，其固接至墊片250之下表面處。 加熱板260之加熱方式例如係通入電源以藉由熱電阻產生 增溫。 另外，壓頭組件230也可更包括一墊片27〇，其固接 於加熱板260,且墊片250與墊片270分別位於加熱板260 之相對側。再者’壓頭組件230可利用至少一個鎖固件290 來依序貝穿並螺合J辰片240、塾片250、加熱板260與塾 片270。在此，鎖固件290可為螺絲。當然，壓頭組件230 中的各構件也可以其他鎖固方式進行組裝。 接著請參照圖3，此實施例之晶片壓著機構3〇〇例如 更包括多個鎖固件390，其貫穿加壓組件310並鎖固壓頭 組件330。其中，鎖固件390與加壓組件31〇之間可以相 1234804 13816twf.doc 對滑動，因此當壓頭組件330受到外力作用時，即可相對 於^壓組件310產生適當的旋轉及/或位移。此外，晶片 壓著機構300可更包括多個彈性件395，其套合在鎖固件 390暴露於加壓組件310與壓頭組件33〇外之部分。在圖 3^中，彈性件395例如係套合在鎖固件39〇之暴露端與加 [、、且件310之間。在此，鎖固件可為螺絲，而彈性件 395可為彈簧。 另外，圖3所示之壓頭組件33〇可包括一墊片35〇、 一加熱板360及一墊片370，其分別與圖2所示之墊片 250加熱板260及墊片270相同，在此即不再贅述。 請再參照圖2，本發明亦提出一種晶片壓著製程，其 係先提供如圖2之晶片壓著機構2〇〇，但並不侷限於使用 此晶片壓著機構200，只要能完成下列所述之晶片壓著製 程即可。接著，將至少一個晶片5〇置於基板8〇上。此外， 例如在晶片50與基板80之間配置一異方性導電膜7〇。 之後，將晶片壓著機構200降下。當壓頭組件230接觸到 晶片50時，若壓頭組件23〇未平行接觸晶片5〇，則晶片 50就會在與壓頭組件230之接觸點提供一作用力F2，進 而轉動壓頭組件230使其平行接觸晶片50。如此一來， 加壓組件21〇所施加之壓著力在經過球體28〇之傳遞後， 就可以垂直基板80之方向而經由壓頭組件230均勻施加 在晶片50上。在壓頭組件23〇自然調整與晶片5〇之接觸 狀態後’晶片壓著機構2〇〇即可將晶片50均勻地壓著接 合至基板80上。 1234804 13816twf.doc 此夕卜 供曰曰乃座著機構200將晶片5〇壓著接合至基 板80時，例如更包括利用加熱板27〇對晶片5〇加熱，以 藉由高溫來固化異方性導電膜7〇，並穩固晶片5〇鱼基板 80之電性連接關係。。 ' 綜上所述，在本發明之晶片壓著機構與晶片壓著製 程中，由於加壓組件與_組件間係以可活動的方式相連 接’因此麼頭組件在接觸晶片時即可自動進行調整，並均 2施力= 日片上。如此—來，即可確保晶片以平行於玻璃 ϋΓ式與其接合，亦即是晶片上所有凸塊與玻璃基板 之接觸墊的接觸阻抗可大致相同，而不會出現部分接觸阻 Ϊίΐ過大Ϊ缺點。因此’本發明之晶片壓著機構與Ϊ片 壁者裝私可提升晶片與玻璃基板接合之良率。 、，然本發明已以較佳實施例揭露如上，然其並非用 明二任何熟習此技藝者，在不脫離本發明之精 護範^視後二可：些許之更動與潤飾’因此本發明之保 =;ί:Γ請專利範圍所界定者為準。 =1繪示為習知晶片_破璃接合技術之示意圖。 面示i圖。繪不為本發明第—實施例之晶片壓著機構的剖 面示^圖3。、、不為本發明第二實施例之晶片壓著機構的剖 【主要元件符號說明】 1234804 13816twf.doc 52 :金凸塊 70 :異方性導電膜 80 :玻璃基板 82 :接觸墊 100 :晶片壓著機構 F1 :作用力 200、300 :晶片壓著機構 210、310 :加壓組件 212、312、252、352 :凹槽 230、330 :壓頭組件 232 :卡置槽 240 :環片 250、350、270、370 :墊片 260、360 :加熱板 280、380 :球體 290、390 :鎖固件 395 :彈性件 G :間隔 F2 :作用力

Claims (1)

1234804 13816twf.doc 十、申請專利範圍： 1·一種晶片壓著機構，至少包括： 一加壓組件； 一壓頭組件，設置在該加壓組件之底下，且該壓頭 組件與該加壓組件之間具有一間隔；以及 、 一球體，配置於該加壓組件與該壓頭組件之間，並 撐起該加壓組件與該壓頭組件之間的該間隔。 2·如申請專利範圍第1項所述之晶片壓著機構，其中 17亥壓頭組件具有 ^置槽，且該加壓組件的底部係部分卡 置於該卡置槽内。 刀 3·如申請專利範圍第2項所述之晶片壓著機構，其 該壓頭組件至少包括·· 〃 一第一墊片，接觸該球體；以及 一環片，固接於該第一墊片上，其中該環片之内 係與该苐一墊片構成該卡置槽。 4·如申請專利範圍第3項所述之晶片壓著機構，其中 该第一墊片之上表面具有一第一凹槽，且該球體係配置於 該第一凹槽内。 、 5·如申請專利範圍第3項所述之晶片壓著機構，其中 该壓頭組件更包括一加熱板，固接於該第一墊片之下表面 處0 义 6·如申請專利範圍第5項所述之晶片壓著機構，其中 該壓頭組件更包括一第二墊片，其係與該加熱板固接了以 使該加熱板夾於該第一墊片與該第二墊片之間。 13 I2348〇i6tw,〇c 7.如申請專利範圍第6項所述之晶片壓著機構，其中 $壓頭組件更包括至少―鎖固件，貫穿並螺合該環片、該 第一墊片、該加熱板與該第二墊片。 κ 8·如申請專利範圍第7項所述之晶片壓著機 盆 該鎖固件包括螺絲。 + 9·如申請專利範圍第丨項所述之晶片壓著機構，盆中 該加壓組件之下表面具有—第二凹槽，且該球 置 該第二凹槽内。 置於 10·如申請專利範圍第i項所述之晶片壓著機構 包括夕數個鎖目件，貫穿該加壓时並且侧該屢頭植 件，且該些鎖固件與該加壓組件之間可以相對滑動。、 u•如申請專利範圍第丨〇項所述之晶片壓著機構，盆 中該些鎖固件包括螺絲。 /、 12·如申請專利範圍第1G項所述之晶片壓著機 性件’套合在暴露於該加壓組件與該壓頭組 件外的该些鎖固件上。 13.如申請專利範圍第12項所述之 中該些彈性件包括彈簧。 者賴其 中專利範圍第1G項所述之晶片壓著機構，其 ^碩、轉至少包括—第—墊片，其係接觸該球體。 ㈣Λ如劫申請專利範圍第14項所述之晶片壓著機構，其 之上表面具有一第一凹槽’且該球體係配置 於5玄第一凹槽内。 16.如申請專利範圍第14項所述夕晶片壓著機構，其 14 I2348U_C 中該壓頭組件更包括一加熱板，固接於該第一墊片之下表 面處。 17·如申請專利範圍第16項所述之晶片壓著機構，其 中該壓頭組件更包括一第二墊片，其係與該加熱板固接， 以使該加熱板夾於該第一墊片與該第二墊片之間。 18·—種晶片壓著製程，至少包括： 提供如申請專利範圍第1項所述之晶片壓著機構； 將至少一晶片置於一基板上；以及
藉由該晶片壓著機構將該晶片壓著至該基板上，其 中該加壓組件所施加之壓著力在經過該球體之傳遞後，係 以垂直该基板之方向而經由該壓頭組件均勻施加在該晶片 上0 #19.如申請專利範圍第18項所述之晶片壓著製程，其 中藉由該晶片壓著機構將該晶片㈣至該基板上 包 括同時加熱該晶片。 °
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