TWI231982B - Semiconductor package with runners on heat slug - Google Patents

Semiconductor package with runners on heat slug Download PDF

Info

Publication number
TWI231982B
TWI231982B TW093111304A TW93111304A TWI231982B TW I231982 B TWI231982 B TW I231982B TW 093111304 A TW093111304 A TW 093111304A TW 93111304 A TW93111304 A TW 93111304A TW I231982 B TWI231982 B TW I231982B
Authority
TW
Taiwan
Prior art keywords
glue injection
heat dissipation
glue
cover
package structure
Prior art date
Application number
TW093111304A
Other languages
Chinese (zh)
Other versions
TW200536085A (en
Inventor
Yun-Lung Chang
Yaw-Yuh Yang
Ting-Rung Cheng
Jun-Cheng Liu
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW093111304A priority Critical patent/TWI231982B/en
Application granted granted Critical
Publication of TWI231982B publication Critical patent/TWI231982B/en
Publication of TW200536085A publication Critical patent/TW200536085A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor package with runners on heat slug includes a substrate, a chip and a heat slug. The chip and heat slug are attached to the upper surface of the substrate. The heat slug has a heat-dissipating surface and a bottom surface corresponding to the heat-dissipating surface. A plurality of runners and a plurality of openings are formed on the heat-dissipating surface. The runners connect each other. The openings are formed at running ends of the runners and pass through the heat slug to its bottom surface. A molding compound is formed on the upper surface of the substrate. The molding compound seals the chip and fills in the runners and the openings, but exposes the heat-dissipating surface.

Description

1231982^ 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於一種具有散熱蓋之半導體封裝構造， 特別係有關於一種注膠流道在散熱蓋上之半導體封裝構 造。 【先前技術】 IW著製造半導體技術的提昇，晶片的運算速度越來越 陕’產生之熱量也越來越高，如熱量不能被散出將損害其 封震結構内之基板、晶片或其它元件，因此會將散熱元 件’例如散熱片或散熱蓋，裝設於一半導體封裝構造之晶 2之裸露表面、該半導體封裝構造之封膠體上表面或直接 汉於該封膠體中，如中華民國專利公告第466726號「具散 熱5之半導體封裝件」所揭示者，其係包括一基板、至少 「晶片、一散熱片及多數導電元件，該晶片係黏接至並與 板，性連接，該散熱片係具有一片體及用以將該片體 t牙起回度而使該片體位於晶片上方之支撐部，該片體具 f 一頂面及一相對之底面，該頂面係外露出一用以包覆該 曰曰片及散熱片之封裝膠體，而該底面相對於該晶片之處上 則形f有一厚部，令該厚部之端面形成有多數之流道，且 該厚部之端面與晶片間形成有一間隙，該些導電元件係用 以相接於該基板上，以供晶片藉之與外界裝置電性連接， 該半導體封裝件可利用該散熱片之片體在其底面之厚 f开^成有多數之流道，以改善其模壓時封裝膠體之模流流 速0 【發明内容】1231982 ^ V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor package structure with a heat dissipation cover, and more particularly to a semiconductor package structure with a glue injection channel on the heat dissipation cover. [Previous technology] IW is advancing the manufacturing semiconductor technology, the operation speed of the chip is getting more and more, and the heat generated is getting higher and higher. For example, if the heat cannot be dissipated, it will damage the substrate, wafer or other components in the vibration isolation structure. Therefore, a heat sink element such as a heat sink or a heat sink cover is mounted on the bare surface of the crystal 2 of a semiconductor package structure, the upper surface of the sealing compound of the semiconductor package structure, or directly in the sealing compound, such as the Republic of China patent Announced in Announcement No. 466726 "Semiconductor Package with Heat Dissipation 5", which includes a substrate, at least "wafer, a heat sink, and most conductive elements, which is bonded to and sexually connected to the board. The sheet system has a sheet body and a supporting portion for raising and lowering the sheet body t so that the sheet body is located above the wafer. The sheet body has a top surface and an opposite bottom surface, and the top surface is exposed to the outside. It is used to cover the encapsulating gel of the chip and the heat sink, and the bottom surface is formed with a thick portion on the side opposite to the wafer, so that the end surface of the thick portion has a plurality of flow channels, and the thickness of the thick portion End face A gap is formed between the chip and the conductive elements. The conductive elements are used to be connected to the substrate for the chip to be electrically connected to external devices. The semiconductor package can use the thickness of the sheet of the heat sink on its bottom surface. f is opened to have a large number of flow channels to improve the mold flow velocity of the encapsulated gel when it is molded 0 [contents of the invention]

1231982___ 五、發明說明（2) 本發明之主要目的係在於提供一種注膠流道在散熱蓋 f之半導體封裝構造，^係包含一基板、一晶片、一散熱 蓋及一封膠體，該散熱蓋之一散熱面係形成有複數個注膠 流道产複數個入膠孔’使得該封膠體在封膠過程（m〇lding process)中，該封膠體可經由該些注膠流道與該些入膠孔 多點？主膠以密封該晶片’並填充於該些注膠流道與該些入 膠孔)以達到模流平衡之功效。 本發明之次一目的係在於提供一種注膠流道在散熱蓋 上之半導體封裝構造’其係包含一基板、一晶片、一散熱 蓋及一封膠體，該散熱蓋之一散熱面係形成有複數個注膠 流道及複數個入膠孔，使得該封膠體在封膠過程中，該封 膠體可經由該些注膠流道與該些入膠孔多點注膠以密封該 晶片’該封膠體並填充於該些注膠流道與該些入膠孔，以 增進該散熱蓋與該封膠體之結合性。 依本發明之注膠流道在散熱蓋上之半導體封裝構造> 其係包含一基板、一晶片、一散熱蓋及一封膠體，該基板 係具有一上表面及一下表面，該晶片係固設於該基板之該 上表面’並與該基板電性連接，該散熱蓋係固設於該基板 之該上表面，且該散熱蓋係具有一散熱面及一相對之底 面’該散熱面係形成有複數個注膠流道及複數個入膠孔， 該些注膠流道係相互連通，該些入膠孔係設於對應注膠流 道之一端並貫穿至該散熱蓋之底面，該封膠體係經由該散 熱蓋·^該些注膠流道與該些入膠孔密封該晶片並填充於該 些注_流道與該些入膠孔，且顯露該散熱蓋之該散熱面。1231982___ V. Description of the invention (2) The main purpose of the present invention is to provide a semiconductor package structure with a glue injection channel in a heat dissipation cover f, which includes a substrate, a wafer, a heat dissipation cover and a colloid. The heat dissipation cover One of the heat-dissipating surfaces is formed with a plurality of glue injection channels to produce a plurality of glue injection holes, so that the sealant is in the molding process, and the sealant can pass through the injection channels and the glue channels. More points in the plastic hole? The main glue is to seal the wafer 'and fill the glue injection channels and the glue injection holes) to achieve the effect of mold flow balance. A secondary object of the present invention is to provide a semiconductor package structure with a glue injection channel on a heat dissipation cover, which includes a substrate, a wafer, a heat dissipation cover and a colloid, and a heat dissipation surface of the heat dissipation cover is formed with A plurality of glue injection channels and a plurality of glue holes, so that during the glue sealing process, the sealant can be injected through the glue channels and the glue holes in multiple points to seal the wafer. The gel is sealed and filled in the glue injection channels and the glue holes, so as to improve the bonding between the heat dissipation cover and the gel. The semiconductor package structure of the glue injection channel on the heat dissipation cover according to the present invention > It comprises a substrate, a wafer, a heat dissipation cover and a glue, the substrate has an upper surface and a lower surface, and the wafer is fixed. The heat dissipation cover is fixed on the upper surface of the substrate and is electrically connected to the substrate. The heat dissipation cover has a heat dissipation surface and an opposite bottom surface. A plurality of glue injection channels and a plurality of glue injection holes are formed. The glue injection channels are communicated with each other. The glue injection holes are provided at one end corresponding to the glue injection channels and penetrate to the bottom surface of the heat dissipation cover. The sealing system seals the wafer through the heat-dissipating cover and the glue injection channels and the glue-injection holes and fills the glue-injection channels and the glue-injection holes, and exposes the heat-dissipating surface of the heat-dissipation cover.

1231982____ 五、發明說明（3) 【實施方式】 參閱所附圖式，本發明將列舉以下之實施例說明。 依本發明之第一具體實施例，請參閱第1及2圖，一種 注膠流道在散熱蓋上之半導體封裝構造丨〇()，其係包含一 基板110、一晶片120、一散熱蓋13〇及一封膠體140，該基 板11(|係具有一上表面Π 1及一下表面112，該晶片12〇係固 設於該基板110之上表面111，並藉由複數個銲線15〇與該 基板110電性連接，該散熱蓋130係固設於該基板110之該 上表面111，且該散熱蓋130係具有一散熱面131及一相對 之底面132，該散熱面131係形成有複數個注膠流道133及 複數個入膠孔134，該些注膠流道133係相互連通，每一注 膠流道133係具有一第一端135與一第二端136 ,在本實施 例中，該些注膠流道1 33係以半蝕刻方式形成，其蝕刻深 度係不小於該散熱蓋130厚度的二分之一為佳，該些入膠 ，孔1 34係設於對應注膠流道1 33之第：端135並貫穿至該散 熱蓋130之該底面132，且該散熱蓋130之該底面132與該基 板11 0之間係具有一間隙，該封膠體140係具有一注膠口折 斷面141，在本實施例中，該些注膠流道133之第二端136 (即連通處）係鄰近該注膠口折斷面141，以利該封膠體14〇 在封膠過程中導流該封膠體140，該封膠體140係經由該散 熱蓋1七0之該些入膠孔134多點注膠以密封該晶片120，且 該封¥體140係填充於該些注膠流道133與該些入膠孔 134，|並顯露該散熱蓋130之散熱面131，該注膠流道在散 熱蓋上之半導體封裝構造100另包含複數個植接於該基板1231982____ V. Description of the invention (3) [Embodiment] Referring to the attached drawings, the present invention will enumerate the following embodiments. According to a first specific embodiment of the present invention, please refer to FIGS. 1 and 2, a semiconductor package structure with a glue injection channel on a heat sink cover () (), which includes a substrate 110, a chip 120, and a heat sink cover. 13〇 and a colloid 140, the substrate 11 (| has an upper surface Π 1 and a lower surface 112, the wafer 120 is fixedly disposed on the upper surface 111 of the substrate 110, and a plurality of bonding wires 15 Electrically connected to the substrate 110, the heat dissipation cover 130 is fixed on the upper surface 111 of the substrate 110, and the heat dissipation cover 130 has a heat dissipation surface 131 and an opposite bottom surface 132. The heat dissipation surface 131 is formed with A plurality of glue injection runners 133 and a plurality of glue injection holes 134 are connected to each other. Each glue injection runner 133 has a first end 135 and a second end 136. In this embodiment, In the example, the glue injection channels 1 33 are formed by semi-etching, and the etching depth is preferably not less than one-half of the thickness of the heat sink cover 130. The glue injection holes 1 34 are provided in the corresponding injection holes. The first end 135 of the glue runner 1 33 penetrates to the bottom surface 132 of the heat dissipation cover 130, and the bottom surface 132 of the heat dissipation cover 130 There is a gap between the substrates 110, and the sealing body 140 has a glue injection port break surface 141. In this embodiment, the second ends 136 (ie, the connecting points) of the glue injection channels 133 are adjacent to each other. The injection port breaks the section 141 to facilitate the sealing compound 140 to guide the sealing compound 140 during the sealing process, and the sealing compound 140 is injected through the heat-dissipating cover 170 through the 134 injection holes 134 of the injection point. The chip 120 is sealed, and the sealing body 140 is filled in the glue injection channels 133 and the glue injection holes 134, and the heat dissipation surface 131 of the heat dissipation cover 130 is exposed. The glue injection channels are in the heat dissipation cover. The semiconductor package structure 100 further includes a plurality of implants on the substrate.

第11頁 T231982 五、發明說明（5) 241，在本實施例中’該注膠口折斷面241係位於該散熱蓋 230之中央，而該些注膠流道233之第二端236係鄰近該注 膠口折斷面241，較佳地，該散熱蓋230係在鄰近該注膠口 折斷面241處形成有另一入膠孔234a，該封膠體240係經由 該散熱蓋230之該些入膠孔234與該入膠孔234a多點注谬以 密封該晶片220，該封膠體240係填充於該些注膠流道 233、該些入膠孔234與該入膠孔234a，且顯露該散熱蓋 230之散熱面231，該半導體封裝構造200另包含複數個植 接於該基板210下表面212之銲球260，用以作為該半導體 封裝構造2 0 0對外電性連接。 本$明之保護範圍當視後附之申請專利範圍所界定者 ίΐ所Γ可熟知此項技藝者’在不脫離本發明之精神和範 圍内所作之任何變化與修改，均屬於本發明之保 1231982 圖式簡單說明 【圖式簡單說明】 第1圖：依據本發明之〆具體實施例，一種注膠流道在政 熱蓋上之半導體封裝構造之俯視示意圖； 、，：献 第2圖：依據本發明之/具體實施例，該注膠流道·政… 蓋上之半導體封裝構造沿第1圖2-2線之截面示意圖、、’ ^ 第3圖：依據本發明之二具體實施例，一種 >主膠//,L 1^在政 熱蓋上之半導體封裝構造之俯視示意圖；及 第4圖：依據本發明之二具體實施例，該注膠=道在散熱 蓋上之半導體封裝構造沿第3圖4-4線之截面示意圖 元件符號簡單說明： 100 半導體封襞構造 110 基板 111 120 晶片 130 散熱蓋… 131 133 注膠流道 134 136 弟— 140 封膠體 141 150 銲線 160 銲球 200 半導體封裝構造 210 基板 211 220 晶片 230 散熱蓋 231 上表面 112 下表面 散熱面 入膠孔 132 135 底面 注膠口 折斷面 上表面 212 下表面 散熱面 232 底面T231982 on page 11 V. Description of the invention (5) 241. In this embodiment, the fracture surface 241 of the injection port is located in the center of the heat dissipation cover 230, and the second ends 236 of the injection channels 233 are adjacent. The glue injection port break surface 241, preferably, the heat dissipation cover 230 is formed with another glue hole 234a adjacent to the glue injection port break surface 241, and the sealing body 240 is passed through the heat dissipation cover 230 The glue hole 234 and the glue hole 234a are injected at multiple points to seal the wafer 220. The sealant 240 is filled in the glue injection channels 233, the glue holes 234 and the glue hole 234a, and reveals that The heat dissipation surface 231 of the heat dissipation cover 230, and the semiconductor package structure 200 further includes a plurality of solder balls 260 implanted on the lower surface 212 of the substrate 210 for external electrical connection of the semiconductor package structure 200. The scope of protection of this patent shall be deemed to be defined by the scope of the appended patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention are protected by the present invention 1231982 Brief description of the drawings [Simplified description of the drawings] Figure 1: According to a specific embodiment of the present invention, a schematic plan view of a semiconductor package structure with a glue injection channel on a political heat cover; According to a specific embodiment of the present invention, the glue injection channel and the government ... A schematic cross-sectional view of the covered semiconductor package structure along the line 2-2 in FIG. 1, ′ ^ FIG. 3: According to the second specific embodiment of the present invention, A top view of a semiconductor package structure with main glue ///, L1 ^ on a political heat cover; and FIG. 4: According to a second specific embodiment of the present invention, the glue injection = semiconductor package on a heat dissipation cover The structure is a cross-sectional schematic diagram along the line 4-4 in Figure 3. The component symbols are simply explained: 100 semiconductor sealing structure 110 substrate 111 120 wafer 130 heat sink ... 131 133 injection channel 134 136 brother — 140 sealing body 141 150 bonding wire 160 Ball 200 210 211 220 a semiconductor package structure 230 of the substrate wafer 231 on the lower surface of the heat sink cover 112 into the rubber surface of the heat dissipation surface holes in the lower surface of the bottom surface of the heat dissipation surface 232 bottom surface 132 135 note the break plane surface 212 of the plastic mouth

第14頁 1231982 圖式簡單說明 233 注膠流道 234 入膠孔 235 第一端 236 第二端 240 封膠體 241 注膠口折斷面 250 銲線 260 焊球 234a 入膠孔 irai 第15頁Page 14 1231982 Brief description of the drawing 233 Glue injection channel 234 Insert hole 235 First end 236 Second end 240 Sealing body 241 Injection port break section 250 Welding wire 260 Solder ball 234a Insert hole irai Page 15

Claims (1)

1231982___一 六、申請專利範圍 【申請專利範圍】 1、 一種注膠流道在散熱蓋上之半導體封裝構造，其係包 含： 一基板，其係具有一上表面及一下表面； 一晶片，其係固設於該基板之該上表面，並與該基板 電性連接； 一散熱蓋，其係固設於該基板之該上表面，該散熱蓋 係具有一散熱面及一相對之底面，該散熱面係形成有複數 個注膠流道及複數個入膠孔，該些注膠流道係相互連通， 該些入膠孔係設於對應之注膠流道並貫穿至該散熱蓋之底 面；及 一封膠體，其係密封該晶片並填充於該些注膠流道與 該些入膠孔，且顯露該散熱面。 2、 如申請專利範圍第1項所述之注膠流道在散熱蓋上之 ;半導體封裝構造’其中該封膠體係經由該I熱蓋之該些入 膠孔以密封該晶片。 3、 如申請專利範圍第1項所述之注膠流道在散熱蓋上之 半導體封裝構造，其中該封膠體係具有一注膠口折斷面。 4、 如申請專利範圍第3項所述之注膠流道在散熱蓋上之 半導體封裝構造，其中每一注膠流道係異有一第一端與一 第二端，該些入膠孔係設於對應注膠流道之第一端，該些 >主膠流道之該些第二端係鄰近該注膠口折斷面。 、如申請專利範圍第3項所述之注膠流道在散熱蓋上之 半導體封裝構造’其中該封膠體之注膠口折斷面，其係位1231982___16. Scope of patent application [Scope of patent application] 1. A semiconductor package structure with a glue injection channel on a heat dissipation cover, which includes: a substrate having an upper surface and a lower surface; a wafer, which Fastened on the upper surface of the substrate and electrically connected to the substrate; a heat sink cover is fixed on the upper surface of the substrate; the heat sink cover has a heat dissipation surface and an opposite bottom surface; The heat dissipation surface is formed with a plurality of glue injection channels and a plurality of glue injection holes. The glue injection channels are communicated with each other. The glue injection holes are provided in the corresponding glue injection channels and penetrate to the bottom surface of the heat dissipation cover. And a colloid, which seals the wafer and fills the glue injection channels and the glue injection holes, and exposes the heat dissipation surface. 2. The glue injection channel as described in item 1 of the patent application scope on the heat dissipation cover; the semiconductor package structure 'wherein the sealing system passes through the plastic injection holes of the I heat cover to seal the chip. 3. The semiconductor package structure of the glue injection channel on the heat dissipation cover as described in item 1 of the scope of the patent application, wherein the glue sealing system has a glue injection port fracture surface. 4. According to the semiconductor package structure of the glue injection channel on the heat dissipation cover described in item 3 of the scope of the patent application, each of the glue injection channels has a first end and a second end. The second ends of the main glue runners are set at the first ends corresponding to the glue injection channels, and the second ends of the main glue runners are adjacent to the injection port fracture surface. 2. The semiconductor package structure of the glue injection channel on the heat dissipation cover as described in item 3 of the scope of the patent application, wherein the glue injection port of the sealant is broken and its position is ^211 QR? I六、令請專利範厨 於該散熱蓋之尹央。 ^]如申請專利範圍第5項所述之漆膠流道在散熱篕上之 半導體封裝構造，其令該散熱蓋形戒有另—入膠孔，其係 鄰近該注膠口折斷面。 μ 7、 “申請專利範圍第1項所述之涞谬流道在散熱蓋上之 半導^封裝構造，其中該些注膠流道之味度係不小於該散 熱蓋，度的二分之一。 8、 ‘申請專利範圍第1項所述之注膠流道在散熱蓋上之 半導洋封裝構造，其中該些注膠流道係以半钱刻方式形 成。| ν 9、 k申請專利範圍第1項所述之注膠流道在散熱蓋上之 半導k封裝構造，其中該些注膠流道係以衝壓方式形成。 10、如申請專利範圍第1項所述之注膠流道在散熱蓋/上之 半導體封裝構造’其另包含複數個銲球，其係植接於該基 板之該下表面：。^ 211 QR? I VI. Order the patent fan to Yin Yang of this heat sink. ^] According to the semiconductor package structure of the lacquer runner on the heat sink as described in item 5 of the scope of the patent application, the heat sink cover is shaped like a plastic hole, which is adjacent to the fracture surface of the injection port. μ 7. "Semiconductor ^ package structure of the erroneous runner on the heat sink cover as described in item 1 of the scope of patent application, wherein the taste of the glue injection runners is not less than that of the heat sink cover, which is half of the degree. I. 8. The semi-conducting package structure of the glue injection runner on the heat dissipation cover described in item 1 of the scope of the patent application, wherein the glue injection runners are formed in a half-money engraving manner. | Ν 9, k applications The semi-conducting k-package structure of the glue injection runner on the heat dissipation cover described in item 1 of the patent scope, wherein the glue injection runners are formed by stamping. 10. The glue injection described in item 1 of the patent scope The semiconductor package structure of the runner on the heat sink cover / further includes a plurality of solder balls, which are implanted on the lower surface of the substrate :. 第17頁Page 17
TW093111304A 2004-04-22 2004-04-22 Semiconductor package with runners on heat slug TWI231982B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW093111304A TWI231982B (en) 2004-04-22 2004-04-22 Semiconductor package with runners on heat slug

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093111304A TWI231982B (en) 2004-04-22 2004-04-22 Semiconductor package with runners on heat slug

Publications (2)

Publication Number Publication Date
TWI231982B true TWI231982B (en) 2005-05-01
TW200536085A TW200536085A (en) 2005-11-01

Family

ID=36251110

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093111304A TWI231982B (en) 2004-04-22 2004-04-22 Semiconductor package with runners on heat slug

Country Status (1)

Country Link
TW (1) TWI231982B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118136597A (en) * 2024-05-10 2024-06-04 甬矽电子(宁波)股份有限公司 Radiator structure of flip chip ball grid array and packaging method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI479615B (en) * 2012-08-17 2015-04-01 矽品精密工業股份有限公司 Semiconductor package and heat sink thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118136597A (en) * 2024-05-10 2024-06-04 甬矽电子(宁波)股份有限公司 Radiator structure of flip chip ball grid array and packaging method thereof

Also Published As

Publication number Publication date
TW200536085A (en) 2005-11-01

Similar Documents

Publication Publication Date Title
KR970005712B1 (en) High heat sink package
US7847375B2 (en) Electronic device and method of manufacturing same
CN109637983B (en) Chip package
JP4254527B2 (en) Semiconductor device
CN213601865U (en) Semiconductor package
JPH04306865A (en) Semiconductor device and manufacture thereof
JP5172290B2 (en) Semiconductor device
WO2013150890A1 (en) Semiconductor device
TWI231982B (en) Semiconductor package with runners on heat slug
JPS6150387B2 (en)
JP7135293B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP4995764B2 (en) Lead supported semiconductor package
JP2007142105A (en) Semiconductor device and method for manufacturing the same
JPH06295971A (en) Semiconductor device and its lead frame
JP2014107375A (en) Semiconductor device and semiconductor device manufacturing method
KR102410257B1 (en) Double side cooling power semiconductor discrete package
JP2005353805A (en) Semiconductor device and its manufacturing method
WO2014132897A1 (en) Semiconductor device
JPH0555280A (en) Resin-sealing method for resin-sealed semiconductor device
JP4246598B2 (en) Power semiconductor device
JPH0831986A (en) Semiconductor device having heatsink
JPH03116856A (en) Semiconductor device
JPH04123442A (en) Semiconductor integrated circuit device
JP2002134560A (en) Semiconductor device
JPH03268347A (en) Semiconductor device

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent