JP2005353805A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2005353805A
JP2005353805A JP2004172294A JP2004172294A JP2005353805A JP 2005353805 A JP2005353805 A JP 2005353805A JP 2004172294 A JP2004172294 A JP 2004172294A JP 2004172294 A JP2004172294 A JP 2004172294A JP 2005353805 A JP2005353805 A JP 2005353805A
Authority
JP
Japan
Prior art keywords
insulating sheet
element mounting
power semiconductor
lead
mounting portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004172294A
Other languages
Japanese (ja)
Inventor
Toshitaka Sekine
敏孝 関根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2004172294A priority Critical patent/JP2005353805A/en
Publication of JP2005353805A publication Critical patent/JP2005353805A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a power semiconductor element, which has reduced heat resistance sealed with resin, and to provide its manufacturing method, while holds the dielectric voltage. <P>SOLUTION: The semiconductor device comprises a power semiconductor element 2 mounted on the element-mounting part 1b of a lead frame, a bonding wire 3 for electrically connecting the electrode of the power semiconductor element to the lead 1a of the lead frame, an insulating sheet 5 having a main face on which the element-mounting part is mounted, and a resin sealing body which seals the insulating sheet, the element-mounting part, the power semiconductor element and the like. The heat conductivity of the insulating sheet is higher than that of the sealing body. The insulating sheet, having a higher heat conductivity than the resin sealing body, is provided below the element-mounting part, whereby it is unnecessary to take into account the filling properties of a sealing resin, and insulation is fully insured, while a thickness of this portion can be thinned and the heat resistance can be decreased. A metal sheet is secured to the insulating sheet, whereby hardness is held and an operability is enhanced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、パワー半導体素子をリードフレームに搭載し樹脂封止した半導体装置及びその製造方法に関するものである。   The present invention relates to a semiconductor device in which a power semiconductor element is mounted on a lead frame and sealed with a resin, and a method for manufacturing the same.

ＩＧＢＴ(Insulated Gate Bipolar Transistor) 、パワーＭＯＳＦＥＴなどのパワー半導体素子は、絶縁耐圧が高く、且つ熱抵抗の小さい半導体パッケージが必要である。
図４は、従来の半導体装置の断面図を示している。この半導体装置では、リードフレーム１０１を用いる。リードフレーム１０１は、リード部１０１ａ及び素子搭載部１０１ｂを備えている。リード部１０１ａは、素子搭載部１０１ｂに一体に繋がるリードと、アルミニウムなどからなるボンディングワイヤ１０３によって素子搭載部に搭載された半導体素子の表面電極に電気的に接続されたリードとを備えている。素子搭載部１０１ｂにはＩＧＢＴやＭＯＳＦＥＴなどのパワー半導体素子１０２が固着されている。そして、パワー素子１０２、素子搭載部１０１ｂ、リード部１０１ａの一部、ボンディングワイヤ１０３は、トランスファモールド法などにより形成されたエポキシ樹脂などを材料とする樹脂封止体１０４により樹脂封止されている。
従来のリードフレームに搭載された樹脂封止型半導体装置において、特許文献１には、ヒートシンクとリードフレームとの間に放熱性フィラーを含有した絶縁層を介在させた構造が記載されている。 Power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs require a semiconductor package having high withstand voltage and low thermal resistance.
FIG. 4 shows a cross-sectional view of a conventional semiconductor device. In this semiconductor device, a lead frame 101 is used. The lead frame 101 includes a lead portion 101a and an element mounting portion 101b. The lead part 101a includes a lead integrally connected to the element mounting part 101b and a lead electrically connected to the surface electrode of the semiconductor element mounted on the element mounting part by a bonding wire 103 made of aluminum or the like. A power semiconductor element 102 such as IGBT or MOSFET is fixed to the element mounting portion 101b. The power element 102, the element mounting portion 101b, a part of the lead portion 101a, and the bonding wire 103 are resin-sealed by a resin sealing body 104 made of an epoxy resin or the like formed by a transfer molding method or the like. .
In a resin-encapsulated semiconductor device mounted on a conventional lead frame, Patent Document 1 describes a structure in which an insulating layer containing a heat dissipating filler is interposed between a heat sink and a lead frame.

このような樹脂封止型の半導体装置は、エポキシ樹脂などの熱硬化性樹脂を樹脂封止体に用いるが、放熱性を向上させるために樹脂封止体１０４として高熱伝導タイプの樹脂を使用する必要がある。それと共に、リードフレーム１０１の素子搭載部１０１ｂに搭載されたパワー半導体素子１０２の実装面に対向する面の樹脂厚（素子搭載部より下の部分の厚さ（ｄ））を薄化する必要がある。しかしながら、この部分は、薄くすればするほど樹脂を均一に充填することは困難である。均一性がなければ部分的に絶縁性が損なわれて半導体装置が破壊される。従来、絶縁性を維持するためには、この部分の厚さは、５００μｍは必要であった（ｄ＝５００）。従って、この部分を薄くして熱抵抗を低減することは困難であった。
特開平２０００−２６０９１８号公報（図１） In such a resin-encapsulated semiconductor device, a thermosetting resin such as an epoxy resin is used for the resin encapsulant, but a high thermal conductivity type resin is used as the resin encapsulant 104 in order to improve heat dissipation. There is a need. At the same time, it is necessary to reduce the resin thickness (thickness (d) of the portion below the element mounting portion) of the surface facing the mounting surface of the power semiconductor element 102 mounted on the element mounting portion 101b of the lead frame 101. is there. However, the thinner this part is, the more difficult it is to uniformly fill the resin. If there is no uniformity, the insulation is partially lost and the semiconductor device is destroyed. Conventionally, in order to maintain insulation, the thickness of this portion has been required to be 500 μm (d = 500). Therefore, it is difficult to reduce the thermal resistance by thinning this portion.
Japanese Unexamined Patent Publication No. 2000-260918 (FIG. 1)

本発明は、以上の問題を解決するためになされたものであり、絶縁耐圧を保ちながら熱抵抗を低減したパワー半導体素子を樹脂封止した半導体装置及びその製造方法を提供する。   The present invention has been made to solve the above problems, and provides a semiconductor device in which a power semiconductor element having a reduced thermal resistance while maintaining a withstand voltage is resin-sealed, and a method for manufacturing the same.

本発明の半導体装置の一態様は、リードフレームと、前記リードフレームの素子搭載部に搭載されたパワー半導体素子と、前記パワー半導体素子の電極と前記リードフレームのリード部とを電気的に接続するボンディングワイヤと、前記素子搭載部を搭載する主面を有する絶縁シートと、前記リード部の一部、前記素子搭載部を搭載する絶縁シート主面、前記素子搭載部及び前記パワー半導体素子を封止する樹脂封止体とを備え、前記絶縁シートの熱伝導率は、前記樹脂封止体の熱伝導率よりも高いことを特徴としている。   One aspect of the semiconductor device of the present invention electrically connects a lead frame, a power semiconductor element mounted on an element mounting portion of the lead frame, an electrode of the power semiconductor element, and a lead portion of the lead frame. A bonding wire, an insulating sheet having a main surface for mounting the element mounting portion, a part of the lead portion, an insulating sheet main surface for mounting the element mounting portion, the element mounting portion, and the power semiconductor element are sealed. The insulating sheet has a thermal conductivity higher than that of the resin sealing body.

また、本発明の半導体装置の一態様は、リードフレームと、前記リードフレームの素子搭載部に搭載されたパワー半導体素子と、前記パワー半導体素子の電極と前記リードフレームのリード部とを電気的に接続するボンディングワイヤと、前記素子搭載部を搭載する主面を有する絶縁シートと、前記絶縁シートの前記素子搭載部を搭載する主面とは対向する面に形成された金属シートと、前記リード部の一部、前記素子搭載部を搭載する絶縁シート主面、前記金属シートの前記絶縁シートが設けられた面とは反対の面、前記素子搭載部及び前記パワー半導体素子を封止する樹脂封止体とを備え、前記絶縁シートの熱伝導率は、前記樹脂封止体の熱伝導率よりも高いことを特徴としている。   According to another aspect of the semiconductor device of the present invention, a lead frame, a power semiconductor element mounted on an element mounting portion of the lead frame, an electrode of the power semiconductor element, and a lead portion of the lead frame are electrically connected. A bonding wire to be connected; an insulating sheet having a main surface on which the element mounting portion is mounted; a metal sheet formed on a surface of the insulating sheet facing the main surface on which the element mounting portion is mounted; and the lead portion Part of the insulating sheet main surface for mounting the element mounting portion, the surface of the metal sheet opposite to the surface on which the insulating sheet is provided, resin sealing for sealing the element mounting portion and the power semiconductor element And a thermal conductivity of the insulating sheet is higher than a thermal conductivity of the resin-encapsulated body.

また、本発明の半導体装置の製造方法の一態様は、リードフレームの素子搭載部にパワー半導体素子を搭載する工程と、前記パワー半導体素子の電極と前記リードフレームのリード部とをボンディングワイヤにより電気的に接続する工程と、半硬化状態の絶縁シートの一面に金属シートを設ける工程と、前記素子搭載部を前記絶縁シートの前記金属シートが設けられた主面とは対向する主面に搭載する工程と、前記パワー半導体素子を搭載した前記リードフレームを金型に載置し、前記リード部の一部、前記素子搭載部を搭載する絶縁シート主面、前記素子搭載部及び前記パワー半導体素子を封止する樹脂封止体を形成する工程とを備え、前記絶縁シートの熱伝導率は、前記樹脂封止体の熱伝導率よりも高いことを特徴としている。   According to another aspect of the method of manufacturing a semiconductor device of the present invention, a step of mounting a power semiconductor element on an element mounting portion of a lead frame, and an electrode of the power semiconductor element and a lead portion of the lead frame are electrically connected by a bonding wire. The step of providing a connection, the step of providing a metal sheet on one surface of the semi-cured insulating sheet, and mounting the element mounting portion on the main surface of the insulating sheet opposite to the main surface provided with the metal sheet. A step of placing the lead frame on which the power semiconductor element is mounted on a mold, a part of the lead part, an insulating sheet main surface on which the element mounting part is mounted, the element mounting part, and the power semiconductor element; And a step of forming a resin sealing body to be sealed, wherein the thermal conductivity of the insulating sheet is higher than the thermal conductivity of the resin sealing body.

本発明は、樹脂封止体より熱伝導率の高い絶縁シートを素子搭載部の下の部分に設けることにより封止樹脂の充填性を考慮する必要がなくなり、絶縁性を充分確保しながらこの部分の厚みの薄化が可能となり熱抵抗の低減が可能となる。また、絶縁シートは使用前は半硬化状態にあるので、硬度が十分でなく作業性が悪いが、絶縁シートに金属シートを固着することにより硬度が保て作業性が向上すると共に樹脂封止後の外力による絶縁シートのワレ、カケで絶縁が保てなくなることを防止する。   The present invention eliminates the need to consider the filling property of the sealing resin by providing an insulating sheet having a higher thermal conductivity than that of the resin sealing body in the lower portion of the element mounting portion, and this portion while ensuring sufficient insulation. It is possible to reduce the thickness of the film and to reduce the thermal resistance. Also, since the insulating sheet is in a semi-cured state before use, the hardness is not sufficient and workability is poor, but by fixing the metal sheet to the insulating sheet, the hardness is maintained and workability is improved and after resin sealing Prevents insulation from being lost due to cracks and cracks in the insulation sheet due to external forces.

本発明は、樹脂封止型の半導体パッケージにおいて、絶縁シートを用いることにより絶縁耐圧を保ちながら熱抵抗を低減させることを特徴とする。
以下、実施例を参照して発明の実施の形態を説明する。 The present invention is characterized in that, in a resin-encapsulated semiconductor package, by using an insulating sheet, the thermal resistance is reduced while maintaining the withstand voltage.
Hereinafter, embodiments of the invention will be described with reference to examples.

まず、図１及び図２を参照して実施例１を説明する。
図１は、この実施例のヒートシンクを備え樹脂封止された半導体装置の断面図、図２は、図１に示す半導体装置を上方から透視してみた透視平面図であり、図１は、図２のＡ−Ａ′線に沿う部分の断面図である。この半導体装置では、リードフレーム１を用いる。リードフレーム１は、フレーム部（図示しない）に保持されたリード部１ａ及び素子搭載部１ｂを備えている。リードフレーム１は、例えば、Ｃｕを素材としている。勿論材料はこれに限るものではなく、Ｃｕの合金やＦｅ＋４２Ｎｉ合金などを用いることができる。リード部１ａは、素子搭載部１ｂに一体に繋がるリードと、アルミニウムなどからなるボンディングワイヤ３によって素子搭載部１ｂに搭載された半導体素子２の表面電極（図示しない）に電気的に接続されたリードとを備えている。素子搭載部１ｂにはＩＧＢＴやＭＯＳＦＥＴ、パワートランジスタなどのパワー半導体素子２がはんだなどにより固着されている。素子搭載部１ｂは、パワー半導体素子２が完全に占めることができる主面を有している。 First, Embodiment 1 will be described with reference to FIGS.
FIG. 1 is a cross-sectional view of a resin-sealed semiconductor device provided with a heat sink of this embodiment, FIG. 2 is a perspective plan view of the semiconductor device shown in FIG. 1 seen from above, and FIG. It is sectional drawing of the part which follows the AA 'line of 2. FIG. In this semiconductor device, a lead frame 1 is used. The lead frame 1 includes a lead portion 1a and an element mounting portion 1b held by a frame portion (not shown). The lead frame 1 is made of Cu, for example. Of course, the material is not limited to this, and an alloy of Cu, an Fe + 42Ni alloy, or the like can be used. The lead portion 1a is a lead integrally connected to the element mounting portion 1b, and a lead electrically connected to a surface electrode (not shown) of the semiconductor element 2 mounted on the element mounting portion 1b by a bonding wire 3 made of aluminum or the like. And has. A power semiconductor element 2 such as an IGBT, MOSFET, or power transistor is fixed to the element mounting portion 1b with solder or the like. The element mounting portion 1b has a main surface on which the power semiconductor element 2 can be completely occupied.

また、素子搭載部１ｂは、絶縁シート５の上に搭載されている。絶縁シート５は、素子搭載部１ｂが完全に占めることができる主面を有している。この実施例では絶縁シート５にはエポキシ樹脂などの熱硬化性樹脂を用いているが、本発明はエポキシ樹脂に限定されるものではなく、他の周知の熱硬化性樹脂を用いることができる。絶縁シート５は、少なくとも半導体素子を封止する樹脂封止体より熱伝導性の高いものが用いられる。通常半導体素子を封止する樹脂封止体は、この実施例も含めて、２．５Ｗ／ｍ・Ｋ程度の熱伝導性を有している。この実施例では３．５Ｗ／ｍ・Ｋ程度の熱伝導性を有する絶縁シート５を用いている。本発明で用いられる絶縁シートは、３．０Ｗ／ｍ・Ｋ以上、より好ましくは、３．５Ｗ／ｍ・Ｋ以上の熱伝導性を有している。この実施例の絶縁シート５の厚みは２５０μｍ程度である。本発明では、絶縁シートの厚さは、３００μｍ以下、より好ましくは２００〜２５０μｍが適当である。絶縁シートの厚さがこの範囲にあれば従来より絶縁破壊を恐れは少なくなる。   The element mounting portion 1b is mounted on the insulating sheet 5. The insulating sheet 5 has a main surface that can be completely occupied by the element mounting portion 1b. In this embodiment, a thermosetting resin such as an epoxy resin is used for the insulating sheet 5, but the present invention is not limited to the epoxy resin, and other known thermosetting resins can be used. As the insulating sheet 5, a material having higher thermal conductivity than a resin sealing body that seals at least a semiconductor element is used. The resin sealing body that normally seals the semiconductor element has a thermal conductivity of about 2.5 W / m · K including this embodiment. In this embodiment, the insulating sheet 5 having a thermal conductivity of about 3.5 W / m · K is used. The insulating sheet used in the present invention has a thermal conductivity of 3.0 W / m · K or more, more preferably 3.5 W / m · K or more. The thickness of the insulating sheet 5 of this embodiment is about 250 μm. In the present invention, the thickness of the insulating sheet is 300 μm or less, more preferably 200 to 250 μm. If the thickness of the insulating sheet is within this range, there is less fear of dielectric breakdown than in the past.

素子搭載部上のパワー半導体素子２、素子搭載部１ｂ、リード部１ａの一部、ボンディングワイヤ３及び絶縁シート５の素子搭載部が搭載されている主面は、トランスファモールド法などにより形成されたエポキシ樹脂などを材料とする樹脂封止体４により封止されている。絶縁シート５の素子搭載部が搭載されている主面と対向する主面は、樹脂封止体から露出している。絶縁シートの熱伝導率は、絶縁シートに混入されるシリカや窒化アルミなどの無機質フィラーの量によって調製される。本発明において、絶縁シートに含まれるシリカなどの無機質フィラー含有量は、７０〜８０重量％が適当である。フィラーの含有量が多いと成形性が低下して作業中に絶縁シートが破壊されてしまう。一方、含有量が少ないと所期の熱伝導度を得ることは難しい。無機質フィラーの含有量がこの範囲内にあるならば、絶縁シートの熱伝導率を３Ｗ／ｍ・Ｋ以上に安定して調整することができる。
この実施例における半導体装置は、高熱伝導の絶縁シートを設けることにより、封止樹脂の充填性を考慮する必要がなくなり、絶縁性を十分確保しながら薄肉部（樹脂封止体の素子搭載部の下の領域）の厚みの薄厚化が可能となり、したがって、この部分の熱抵抗の低減が可能となる。 The main surface on which the power semiconductor element 2, the element mounting portion 1b, a part of the lead portion 1a, the bonding wire 3 and the element mounting portion of the insulating sheet 5 are mounted is formed by a transfer mold method or the like. It is sealed with a resin sealing body 4 made of an epoxy resin or the like. The main surface opposite to the main surface on which the element mounting portion of the insulating sheet 5 is mounted is exposed from the resin sealing body. The thermal conductivity of the insulating sheet is adjusted by the amount of inorganic filler such as silica or aluminum nitride mixed in the insulating sheet. In this invention, 70-80 weight% is suitable for inorganic filler content, such as a silica contained in an insulating sheet. If the content of the filler is large, the moldability is lowered and the insulating sheet is destroyed during the operation. On the other hand, if the content is small, it is difficult to obtain the desired thermal conductivity. If the content of the inorganic filler is within this range, the thermal conductivity of the insulating sheet can be stably adjusted to 3 W / m · K or more.
In the semiconductor device in this embodiment, it is not necessary to consider the filling property of the sealing resin by providing an insulating sheet with high thermal conductivity, and the thin wall portion (of the element mounting portion of the resin sealing body) while ensuring sufficient insulation. The thickness of the lower region) can be reduced, and therefore the thermal resistance of this portion can be reduced.

次に、図を参照しながらこの実施例の半導体装置の製造方法を説明する。
まず、ＩＧＢＴなどのパワー半導体素子５を素子搭載部１ｂにはんだ等により固着する。図２に示すように、ベッドといわれる素子搭載部１ｂは、引き出し端子となるリード部１ａの１つ（コレクタ端子）に連続的に繋がっている。やはり引き出し端子（エミッタ端子及びゲート端子）となる２本のリード部１ａは、素子搭載部１ｂとは少し離れていて、これらリード部１ａとパワー半導体素子２の２つの表面電極２ａ、２ａとをそれぞれＡｌなどからなるボンディングワイヤ３、３により電気的に接続する。 Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to the drawings.
First, the power semiconductor element 5 such as IGBT is fixed to the element mounting portion 1b with solder or the like. As shown in FIG. 2, the element mounting portion 1b called a bed is continuously connected to one of the lead portions 1a (collector terminal) serving as a lead terminal. The two lead portions 1a that also serve as lead terminals (emitter terminal and gate terminal) are slightly separated from the element mounting portion 1b, and the lead portion 1a and the two surface electrodes 2a and 2a of the power semiconductor element 2 are connected to each other. They are electrically connected by bonding wires 3 and 3 made of Al, respectively.

その後、図示はしないが、先ずは厚さが２５０μｍのエポキシ樹脂からなる半硬化状態の絶縁シート５を、次にパワー半導体素子２を搭載したリードフレーム１を成型金型のキャビティ内に載置する。この時、キャビティ内の下金型の部分に絶縁シート５が直接接しており、その上に素子搭載部１ｂが載置されている。この成型金型が密閉されて、エポキシ樹脂などの樹脂がキャビティ内に充填されて封止樹脂あるいは樹脂封止体４が形成される。成型金型から取り出された樹脂封止体４及び絶縁シート５は、熟成されて硬化する。その後、樹脂封止体４から露出していたフレーム部やバリなどを取り除いて半導体装置が形成される。
この実施例では素子搭載部より下の部分は、絶縁シートで構成されているので従来より薄く形成される。この実施例の素子搭載部より下の部分は、図４に示される従来例の前記素子搭載部より下の部分（ｄ（＝５００μｍ）に相当する）に比較して１／２の薄さになりながら、絶縁性は十分維持され、熱抵抗が低減されている。 Thereafter, although not shown, first, the semi-cured insulating sheet 5 made of an epoxy resin having a thickness of 250 μm is placed, and then the lead frame 1 on which the power semiconductor element 2 is mounted is placed in the cavity of the molding die. . At this time, the insulating sheet 5 is in direct contact with the lower mold portion in the cavity, and the element mounting portion 1b is placed thereon. The molding die is sealed, and a resin such as an epoxy resin is filled in the cavity to form a sealing resin or a resin sealing body 4. The resin sealing body 4 and the insulating sheet 5 taken out from the molding die are aged and hardened. Thereafter, the frame portion and burrs exposed from the resin sealing body 4 are removed to form a semiconductor device.
In this embodiment, the portion below the element mounting portion is made of an insulating sheet, so that it is thinner than the conventional one. The portion below the element mounting portion of this embodiment is ½ the thickness of the portion below the element mounting portion of the conventional example shown in FIG. 4 (corresponding to d (= 500 μm)). However, the insulation is sufficiently maintained and the thermal resistance is reduced.

次に、図３を参照して実施例２を説明する。
図３は、この実施例のヒートシンクを備え樹脂封止された半導体装置の断面図であり、実施例１を説明する図２と同じ様な平面形状になっている。リードフレーム２１は、フレーム部（図示しない）に保持されたリード部２１ａ及び素子搭載部２１ｂを備えている。リードフレーム２１は、例えば、Ｃｕを素材としている。リード部２１ａは、素子搭載部２１ｂに一体に繋がるリードと、アルミニウムなどからなるボンディングワイヤ２３によって素子搭載部２１ｂに搭載された半導体素子２２の表面電極（図示しない）に電気的に接続されたリードとを備えている。素子搭載部２１ｂにはＩＧＢＴやＭＯＳＦＥＴ、パワートランジスタなどのパワー半導体素子２２がはんだなどにより固着されている。素子搭載部２１ｂは、パワー半導体素子２２が完全に占めることができる主面を有している。また、素子搭載部２１ｂは、絶縁シート２５の上に搭載されている。絶縁シート２５は、素子搭載部２１ｂが完全に占めることができる主面を有している。 Next, Embodiment 2 will be described with reference to FIG.
FIG. 3 is a cross-sectional view of a resin-sealed semiconductor device provided with the heat sink of this embodiment, and has a planar shape similar to that of FIG. The lead frame 21 includes a lead portion 21a and an element mounting portion 21b held by a frame portion (not shown). The lead frame 21 is made of Cu, for example. The lead portion 21a is a lead that is integrally connected to the element mounting portion 21b, and a lead that is electrically connected to a surface electrode (not shown) of the semiconductor element 22 mounted on the element mounting portion 21b by a bonding wire 23 made of aluminum or the like. And. A power semiconductor element 22 such as an IGBT, a MOSFET, or a power transistor is fixed to the element mounting portion 21b with solder or the like. The element mounting portion 21b has a main surface on which the power semiconductor element 22 can be completely occupied. The element mounting portion 21b is mounted on the insulating sheet 25. The insulating sheet 25 has a main surface that can be completely occupied by the element mounting portion 21b.

絶縁シート２５は、少なくとも半導体素子を封止する樹脂封止体より熱伝導性の高いものが用いられる。通常半導体素子を封止する樹脂封止体は、この実施例も含めて、２．５Ｗ／ｍ・Ｋ程度の熱伝導性を有している。この実施例では３．５Ｗ／ｍ・Ｋ程度の熱伝導性を有する絶縁シート２５を用いている。また、この実施例の絶縁シート２５の厚みは２５０μｍ程度である。
絶縁シート２５の１つの主面には素子搭載部２１ｂが搭載されており、この主面と対向する他の主面（この場合絶縁シートの下面）は、アルミニウム箔などからなる金属シート２６により被覆されている。本発明においては、金属シートには、Ａｌ（アルミニウム）箔に限らず、Ｃｕ（銅）箔などを他の金属を用いることができる。その厚さは、０．２ｍｍ以下が好ましく、この実施例では１００μｍのものを用いている。Ｃｕ箔を用いる場合には表面の酸化を防ぐためにメッキ処理を施すこともできる。素子搭載部上のパワー半導体素子２２、素子搭載部２１ｂ、リード部２１ａの一部、ボンディングワイヤ２３、絶縁シート２５の素子搭載部が搭載されている主面及び金属シート２６の絶縁シートを被覆している主面は、トランスファモールド法などにより形成されたエポキシ樹脂などを材料とする樹脂封止体２４により封止されている。 As the insulating sheet 25, a sheet having a higher thermal conductivity than a resin sealing body that seals at least a semiconductor element is used. The resin sealing body that normally seals the semiconductor element has a thermal conductivity of about 2.5 W / m · K including this embodiment. In this embodiment, an insulating sheet 25 having a thermal conductivity of about 3.5 W / m · K is used. Further, the thickness of the insulating sheet 25 of this embodiment is about 250 μm.
The element mounting portion 21b is mounted on one main surface of the insulating sheet 25, and the other main surface (in this case, the lower surface of the insulating sheet) facing the main surface is covered with a metal sheet 26 made of aluminum foil or the like. Has been. In the present invention, the metal sheet is not limited to the Al (aluminum) foil, and other metals such as a Cu (copper) foil can be used. The thickness is preferably 0.2 mm or less, and in this embodiment, a thickness of 100 μm is used. In the case of using Cu foil, a plating process can be applied to prevent oxidation of the surface. The power semiconductor element 22 on the element mounting part, the element mounting part 21b, a part of the lead part 21a, the main surface on which the element mounting part of the bonding wire 23 and the insulating sheet 25 is mounted, and the insulating sheet of the metal sheet 26 are covered. The main surface is sealed with a resin sealing body 24 made of an epoxy resin or the like formed by a transfer mold method or the like.

金属シート２６の絶縁シートを被覆している主面と対向する主面は、樹脂封止体２４から露出している。絶縁シートの熱伝導率は、絶縁シートに混入されるシリカなどの無機質フィラーの量によって調製される。本発明に用いる絶縁シートの無機質フィラー含有量は、７０〜８０重量％が適当である。フィラーの含有量が多いと成形性が低下して作業中に絶縁シートが破壊されてしまう。一方、含有量が少ないと所期の熱伝導度を得ることは難しい。
この実施例における半導体装置は、高熱伝導の絶縁シートを設けることにより、封止樹脂の充填性を考慮する必要がなくなり、絶縁性を十分確保しながら薄肉部（樹脂封止体の素子搭載部の下の領域）の厚みの薄厚化が可能となって、この部分の熱抵抗の低減が可能となる。 The main surface opposite to the main surface covering the insulating sheet of the metal sheet 26 is exposed from the resin sealing body 24. The thermal conductivity of the insulating sheet is prepared by the amount of inorganic filler such as silica mixed in the insulating sheet. The inorganic filler content of the insulating sheet used in the present invention is suitably 70 to 80% by weight. If the content of the filler is large, the moldability is lowered and the insulating sheet is destroyed during the operation. On the other hand, if the content is small, it is difficult to obtain the desired thermal conductivity.
In the semiconductor device in this embodiment, it is not necessary to consider the filling property of the sealing resin by providing an insulating sheet with high thermal conductivity, and the thin wall portion (of the element mounting portion of the resin sealing body) while ensuring sufficient insulation. The thickness of the lower region) can be reduced, and the thermal resistance of this portion can be reduced.

次に、この実施例の半導体装置の製造方法を説明する。
まず、ＩＧＢＴなどのパワー半導体素子２２を素子搭載部２１ｂにはんだなどの手段により固着する。素子搭載部２１ｂは、引き出し端子となるリード部２１ａの１つ（コレクタ端子）に連続的に繋がっている。また、やはり引き出し端子（エミッタ端子及びゲート端子）となる２本のリード部２１ａは、素子搭載部２１ｂとは少し離れている。これらリード部２１ａとパワー半導体素子２２の２つの表面電極とをそれぞれＡｌなどからなるボンディングワイヤ２３により電気的に接続する。 Next, a method for manufacturing the semiconductor device of this embodiment will be described.
First, the power semiconductor element 22 such as IGBT is fixed to the element mounting portion 21b by means such as solder. The element mounting portion 21b is continuously connected to one of the lead portions 21a (collector terminal) serving as a lead terminal. In addition, the two lead portions 21a that also serve as lead terminals (emitter terminal and gate terminal) are slightly separated from the element mounting portion 21b. The lead portion 21a and the two surface electrodes of the power semiconductor element 22 are electrically connected to each other by bonding wires 23 made of Al or the like.

その後、図示はしないが、先ずはアルミニウム箔等の金属シート２６に貼り付けた厚さが２５０μｍのエポキシ樹脂からなる半硬化状態の絶縁シート２５を、次にパワー半導体素子２２を搭載したリードフレーム２１を成型金型のキャビティ内に載置する。この時、キャビティ内の下金型の部分に金属シート２６が直接接しており、その上に絶縁シート２５を介して素子搭載部２１ｂが載置されている。この成型金型が密閉されて、エポキシ樹脂などの樹脂がキャビティ内に充填されて封止樹脂あるいは樹脂封止体２４が形成される。成型金型から取り出された樹脂封止体２４及び絶縁シート２５は、熟成されて硬化する。その後、樹脂封止体２４から露出していたフレーム部やバリなどを取り除いて半導体装置が形成される。
絶縁シートは、工程の初期の段階では半硬化状態にあるので、硬度が十分でなく作業性が悪い。しかし、アルミニウム箔などの金属シートを設けることにより絶縁シートの硬度が保て作業性が容易となると共に樹脂封止後の外力による絶縁シートのワレ、カケで絶縁が保てなくなることを十分防止できる。また、この金属シートがこの部分の熱抵抗を低減させることも可能になる。 Thereafter, although not shown in the drawing, first, a semi-cured insulating sheet 25 made of an epoxy resin having a thickness of 250 μm attached to a metal sheet 26 such as aluminum foil, and then a lead frame 21 on which a power semiconductor element 22 is mounted Is placed in the cavity of the molding die. At this time, the metal sheet 26 is in direct contact with the lower mold portion in the cavity, and the element mounting portion 21b is placed on the metal sheet 26 via the insulating sheet 25. The molding die is sealed, and a resin such as an epoxy resin is filled in the cavity to form a sealing resin or a resin sealing body 24. The resin sealing body 24 and the insulating sheet 25 taken out from the molding die are aged and hardened. Thereafter, the frame portion and burrs exposed from the resin sealing body 24 are removed to form a semiconductor device.
Since the insulating sheet is in a semi-cured state at the initial stage of the process, the hardness is not sufficient and workability is poor. However, by providing a metal sheet such as an aluminum foil, the hardness of the insulating sheet can be maintained and workability can be facilitated, and it is possible to sufficiently prevent insulation from being lost due to cracking or chipping of the insulating sheet due to external force after resin sealing. . In addition, this metal sheet can reduce the thermal resistance of this portion.

本発明の実施例１に係るヒートシンクを備え樹脂封止された半導体装置の断面図。1 is a cross-sectional view of a resin-sealed semiconductor device that includes a heat sink according to a first embodiment of the present invention. 図１に示す半導体装置を上方から透視してみた透視平面図。FIG. 2 is a perspective plan view of the semiconductor device shown in FIG. 1 viewed from above. 本発明の実施例２のヒートシンクを備え樹脂封止された半導体装置の断面図。Sectional drawing of the semiconductor device resin-sealed provided with the heat sink of Example 2 of this invention. 従来の半導体装置の断面図。Sectional drawing of the conventional semiconductor device.

符号の説明Explanation of symbols

１、２１ リードフレーム
１ａ、２１ａ リードフレームのリード部
１ｂ、２１ｂ リードフレームの素子搭載部
２ パワー半導体素子
２ａ パワー半導体素子の表面電極
３ ボンディングワイヤ
４、２４ 樹脂封止体
５、２５ 絶縁シート
２６ 金属シート 1, 21 Lead frame 1a, 21a Lead frame lead part 1b, 21b Lead frame element mounting part 2 Power semiconductor element 2a Surface electrode of power semiconductor element 3 Bonding wire 4, 24 Resin encapsulant 5, 25 Insulating sheet 26 Metal Sheet

Claims (5)

リードフレームと、
前記リードフレームの素子搭載部に搭載されたパワー半導体素子と、
前記パワー半導体素子の電極と前記リードフレームのリード部とを電気的に接続するボンディングワイヤと、
前記素子搭載部を搭載する主面を有する絶縁シートと、
前記リード部の一部、前記素子搭載部を搭載する絶縁シート主面、前記素子搭載部及び前記パワー半導体素子を封止する樹脂封止体とを備え、
前記絶縁シートの熱伝導率は、前記樹脂封止体の熱伝導率よりも高いことを特徴とする半導体装置。 A lead frame,
A power semiconductor element mounted on the element mounting portion of the lead frame;
A bonding wire for electrically connecting the electrode of the power semiconductor element and the lead portion of the lead frame;
An insulating sheet having a main surface on which the element mounting portion is mounted;
A part of the lead part, an insulating sheet main surface for mounting the element mounting part, a resin sealing body for sealing the element mounting part and the power semiconductor element,
The semiconductor device according to claim 1, wherein a thermal conductivity of the insulating sheet is higher than a thermal conductivity of the resin sealing body. リードフレームと、
前記リードフレームの素子搭載部に搭載されたパワー半導体素子と、
前記パワー半導体素子の電極と前記リードフレームのリード部とを電気的に接続するボンディングワイヤと、
前記素子搭載部を搭載する主面を有する絶縁シートと、
前記絶縁シートの前記素子搭載部を搭載する主面とは対向する面に形成された金属シートと、
前記リード部の一部、前記素子搭載部を搭載する絶縁シート主面、前記金属シートの前記絶縁シートが設けられた面とは反対の面、前記素子搭載部及び前記パワー半導体素子を封止する樹脂封止体とを備え、
前記絶縁シートの熱伝導率は、前記樹脂封止体の熱伝導率よりも高いことを特徴とする半導体装置。 A lead frame,
A power semiconductor element mounted on the element mounting portion of the lead frame;
A bonding wire for electrically connecting the electrode of the power semiconductor element and the lead portion of the lead frame;
An insulating sheet having a main surface on which the element mounting portion is mounted;
A metal sheet formed on a surface opposite to a main surface on which the element mounting portion of the insulating sheet is mounted;
A part of the lead part, an insulating sheet main surface on which the element mounting part is mounted, a surface of the metal sheet opposite to the surface on which the insulating sheet is provided, the element mounting part, and the power semiconductor element are sealed. A resin sealing body,
The semiconductor device according to claim 1, wherein a thermal conductivity of the insulating sheet is higher than a thermal conductivity of the resin sealing body. 前記絶縁シートの熱伝導率は、３Ｗ／ｍ・Ｋ以上であることを特徴とする請求項１又は請求項２に記載の半導体装置。 The semiconductor device according to claim 1, wherein the insulating sheet has a thermal conductivity of 3 W / m · K or more. 前記絶縁シートには無機フィラーが含有されており、その含有率は、７０〜８０重量％であることを特徴とする請求項１乃至請求項３のいずれかに記載の半導体装置。 The semiconductor device according to claim 1, wherein the insulating sheet contains an inorganic filler, and the content thereof is 70 to 80% by weight. リードフレームの素子搭載部にパワー半導体素子を搭載する工程と、
前記パワー半導体素子の電極と前記リードフレームのリード部とをボンディングワイヤにより電気的に接続する工程と、
半硬化状態の絶縁シートの一面に金属シートを設ける工程と、
前記素子搭載部を前記絶縁シートの前記金属シートが設けられた主面とは対向する主面に搭載する工程と、
前記パワー半導体素子を搭載した前記リードフレームを金型に載置し、前記リード部の一部、前記素子搭載部を搭載する絶縁シート主面、前記素子搭載部及び前記パワー半導体素子を封止する樹脂封止体を形成する工程とを備え、
前記絶縁シートの熱伝導率は、前記樹脂封止体の熱伝導率よりも高いことを特徴とする半導体装置の製造方法。 Mounting a power semiconductor element on the element mounting portion of the lead frame;
Electrically connecting the electrode of the power semiconductor element and the lead portion of the lead frame with a bonding wire;
Providing a metal sheet on one surface of the semi-cured insulating sheet;
Mounting the element mounting portion on a main surface of the insulating sheet opposite to the main surface provided with the metal sheet;
The lead frame on which the power semiconductor element is mounted is placed on a mold, and a part of the lead part, an insulating sheet main surface on which the element mounting part is mounted, the element mounting part, and the power semiconductor element are sealed. Forming a resin sealing body,
The method of manufacturing a semiconductor device, wherein the thermal conductivity of the insulating sheet is higher than the thermal conductivity of the resin sealing body.
JP2004172294A 2004-06-10 2004-06-10 Semiconductor device and its manufacturing method Pending JP2005353805A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004172294A JP2005353805A (en) 2004-06-10 2004-06-10 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004172294A JP2005353805A (en) 2004-06-10 2004-06-10 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2005353805A true JP2005353805A (en) 2005-12-22

Family

ID=35588013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004172294A Pending JP2005353805A (en) 2004-06-10 2004-06-10 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2005353805A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008021220A2 (en) 2006-08-11 2008-02-21 Vishay General Semiconductor Llc Semiconductor device and method for manufacturing a semiconductor device having improved heat dissipation capabilities
JP2012059927A (en) * 2010-09-09 2012-03-22 Rohm Co Ltd Semiconductor device and method for manufacturing the semiconductor device
JP5949935B2 (en) * 2012-10-25 2016-07-13 三菱電機株式会社 Semiconductor device
US10373896B2 (en) 2014-03-28 2019-08-06 Mitsubishi Electric Corporation Semiconductor module and drive device equipped with semiconductor module
EP4109519A3 (en) * 2021-06-23 2023-01-11 Infineon Technologies Austria AG Semiconductor package with releasable isolation layer protection

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008021220A2 (en) 2006-08-11 2008-02-21 Vishay General Semiconductor Llc Semiconductor device and method for manufacturing a semiconductor device having improved heat dissipation capabilities
EP2057665A4 (en) * 2006-08-11 2016-01-06 Vishay Gen Semiconductor Llc Semiconductor device and method for manufacturing a semiconductor device having improved heat dissipation capabilities
JP2012059927A (en) * 2010-09-09 2012-03-22 Rohm Co Ltd Semiconductor device and method for manufacturing the semiconductor device
JP5949935B2 (en) * 2012-10-25 2016-07-13 三菱電機株式会社 Semiconductor device
JPWO2014064806A1 (en) * 2012-10-25 2016-09-05 三菱電機株式会社 Semiconductor device
US9601408B2 (en) 2012-10-25 2017-03-21 Mitsubishi Electric Corporation Semiconductor device
US10373896B2 (en) 2014-03-28 2019-08-06 Mitsubishi Electric Corporation Semiconductor module and drive device equipped with semiconductor module
EP4109519A3 (en) * 2021-06-23 2023-01-11 Infineon Technologies Austria AG Semiconductor package with releasable isolation layer protection
US11791238B2 (en) 2021-06-23 2023-10-17 Infineon Technologies Austria Ag Semiconductor package with releasable isolation layer protection
US12080625B2 (en) 2021-06-23 2024-09-03 Infineon Technologies Austria Ag Semiconductor package with releasable isolation layer protection

Similar Documents

Publication Publication Date Title
US7671453B2 (en) Semiconductor device and method for producing the same
US7045907B2 (en) Semiconductor device and method of manufacturing same
US7582958B2 (en) Semiconductor package
JP6115738B2 (en) Semiconductor device and manufacturing method thereof
JP5163055B2 (en) Power semiconductor module
US20060056213A1 (en) Power module package having excellent heat sink emission capability and method for manufacturing the same
JP2010021338A (en) Semiconductor device, and method of manufacturing the same
US20050082690A1 (en) Method for producing semiconductor device and semiconductor device
JP2003124437A (en) Semiconductor device
JP4146785B2 (en) Power semiconductor device
WO2016166834A1 (en) Semiconductor device
JP2005191071A (en) Semiconductor device
JP2008263210A (en) Power semiconductor package
JP4100332B2 (en) Electronic device and manufacturing method thereof
JP2005353805A (en) Semiconductor device and its manufacturing method
KR101490751B1 (en) Semiconductor device and manufacturing method thereof
JP7135293B2 (en) Semiconductor device and method for manufacturing semiconductor device
US11152275B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP2000091472A (en) Semiconductor device
JP2002110867A (en) Semiconductor device and its manufacturing method
EP2309538A2 (en) Package for semiconductor devices
JP2017191807A (en) Power semiconductor device and manufacturing method of power semiconductor device
US11462504B2 (en) Semiconductor apparatus
JP2019110278A (en) Semiconductor device
KR20180002419A (en) Power module and manufacturing method therefor