1230405 五、發明說明（1 ) 【發明所屬技術領域】 本發明係關於以具有特定面方位之矽（Si)單結晶（矽）爲 基板，而構成複合半導體元件的技術。 【習知技術】 已知有含有如以硼（B)與磷（P)爲構成元素之磷化硼（BP) 系IE -V族化合物半導體（磷化硼系半導體）作爲第！]j-v族 化合物半導體之一種（參照：寺本巖著，「半導體裝置槪 論」（書名）（ 1 995年3月30日）、培風館發行初版，第 26〜28頁）。磷化硼（BP)係由飛利浦（Philips)的離子結合度 小於0.006(參照：飛利浦著，「半導體結合論」（ 1 9 8 5年7 月25曰）、吉岡書店發行第3版，第51頁），且幾乎全部 共價鍵結所構成的物質。此外，因爲屬於閃鋅礦（zinc-blend)型立方晶， 因此具有退縮的價帶電之能帶構造（參照 生駒俊明、生駒英明共著，「複合半導體基礎物性入門」 (書名，中譯）（1991年9月10日）、培風館發行初版，第 14〜17頁）。因此，磷化硼便具有可輕易獲得p型導電層的 優點。 在習知技術中，利用單結晶基板上所設置的磷化硼層， 而構成各種複合半導體元件。譬如已知有如利用磷化硼層 的異質接面雙極性電晶體（HBTK參照，J. Electrochem· Soc.，1 25(4)(1 978),第663〜637頁）。此外，有如將磷化硼 層利用爲窗（window)層的太陽能電池（參照上述 J· Electrochem. Soc.，）。尙有揭不利用憐化硼以及其混晶’ 1230405 五、發明說明（2) 而構成藍色帶或綠色帶之發光二極體（LED)或雷射二極體 (LD)的技術（參照日本專利①第2 809690號、②第2809691 號、③第2809692號各公報、以及④美國專利第6,069,021 號）。 單量體的磷化硼（BP;boron monophosphide)的晶格常數 約4.5 3 8 A(參照上述「半導體裝置槪論」，28頁）。此外， 被利用爲基板的矽（Si)單結晶係相同立方晶的閃鋅礦（zinc-blend)型結晶，晶格常數約5.431A(參照上述「半導體裝置 槪論」，28頁）。所以，將晶格失配（lattice mismatch)度 相對於矽單結晶晶格常數（ = 5.431 A)，依雙方結晶的晶格常 數差異（ = 〇.893A)比率表示的話，約大至16.6%。爲防止隨 此較大晶格失配度所引起的磷化硼層，從Si基板表面上 剝落，便有揭示將由含有在較低溫下所成長非晶質之多晶 磷化硼所構成的低溫緩衝層，設置於Si基板表面上的技 術手段（參照上述美國專利第6,069,02 1號）。 【發明欲解決之課題】 在習知技術中，磷化硼系半導體層係譬如表面爲{1.0.0} 或{1.1 · 1 ·}結晶面之矽單結晶的基板所形成的（參照上述美 國專利第6,069,021號）。特別係{1.1.1.}結晶面因爲相較 於{1 · 0 · 0 ·}結晶面下，矽原子屬於較密集的存在，因此在 抑制對構成低溫緩衝層的硼（B)與磷（P)的矽單結晶基板內 部之滲透上頗爲有效。 但是，矽單結晶的{1.1.1 ·}結晶面相互間隔約3.136A。 -4- 1230405 五、發明說明（3) 此外，磷化硼（BP:晶格常數=4·5 3 8Α)的{1.1.0.}結晶面間隔 爲3.209 A，與矽單結晶的{ 1 · 1 . 1 ·}結晶面間隔並不一致。 因此，習知在將{1 · 1.1 ·}結晶面當作表面的矽單結晶基板 上，所形成的硼化矽層，便將造成形成含有大量錯位或層 積缺陷等結晶缺陷的粗糙結晶層等問題發生。 有鑒於斯’本發明係提供一種將使於{1 · 1 · 1 ·}矽單結晶 表面上交叉的矽之{1·1·1.}結晶面間隔，形成與磷化硼的 {1·1·0.}結晶面間隔一致之表面的矽單結晶，作爲基板的 技術，而獲得結晶性優越的磷化硼系半導體層。 【解決課題之手段】 本發明之主旨在於利用將構成矽單結晶基板表面的結晶 面方位予以特定，而解決上述習知技術問題點。換句話 說，本發明係： (1) 一種複合半導體元件，係在具備有：由矽（Si)單結晶 (矽）所構成的基板表面上，設置著含有以硼（B)與磷（P)爲 構成元素之磷化硼（BP)系半導體層的複合半導體元件；其 中，將朝向Π.Ι.Ο.]結晶方位，傾斜5.0度（。）以上且9.0 度（° )以下之角度的{1.1.1.}結晶面設爲表面之矽單結晶， 當作基板。 (2) 上述（1)所述之複合半導體元件，係將朝向[丨.；!·〇·]結 晶方位，傾斜7·3±0·5度（。）之角度範圍的{i.i.i.}結晶面 設爲表面之矽單結晶，當作基板。 (3) 上述（1)所述之複合半導體元件，係由在將朝向 1230405 五、發明說明（4 ) [1.1.0.]結晶方位，傾斜5.0度（° )以上且9.0度（° )以下之 角度的{ 1 . 1 · 1 .}結晶面設爲表面之矽單結晶基板上，通過 由磷化硼系半導體層所構成的低溫緩衝層，並層積上具有 {1 .1.0·}結晶面之磷化硼系半導體層的層積結構所構成。 (4) 上述（2)所述之複合半導體元件，係由在將朝向 [1.1.0.]結晶方位，傾斜7.3±0.5度（° )之角度範圍內的 { 1 · 1 · 1 ·}結晶面設爲表面之矽單結晶基板上，通過著由磷 化硼系半導體層所構成的低溫緩衝層，並層積上具有 {1·1·0·}結晶面之磷化硼（ΒΡ)半導體層的層積結構所構 成。 (5) —種發光元件係由上述（1)至（4)中任一項所述複合半 導體元件所構成。 (6) —種電晶體係由上述（1)至（4)中任一項所述複合半導 體元件所構成。 此外，本發明係： (7) —種複合半導體元件之製造方法，在將朝向[i.Ko.] 結晶方位，傾斜5.0度（° )以上且9.0度（° )以下之角度的 { 1 · 1 · 1 ·}結晶面設爲表面之砂單結晶基板上，通過著由憐 化硼系半導體層所構成的低溫緩衝層，然後層積上具有 {1 · 1 ·〇·}結晶面之磷化硼系半導體層的層積結構所構成。 (8) —種複合半導體元件之製造方法，係在將朝向Π. ；[.〇.；! 結晶方位，傾斜7·3± 0.5度（° )之角度範圍內的{1 .1.1.}結 晶面設爲表面之砂單結晶基板上，通過著由磷化硼系半導 1230405 五、發明說明（5 ) 體層所構成的低溫緩衝層，然後層積上具有{1.1.0·}結晶 面之磷化硼（BP)半導體層的層積結構所構成。 【發明實施形態】 爲說明本發明內容，將以{1.1.1.}結晶面2a爲表面的 {1.1.1·}-矽單結晶1之截面模式圖，例示於第1圖中。 { 1 · 1 · 1 ·}-砂單結晶表面係並未傾斜於任何結晶方位的正確 { 1 · 1 · 1 .}結晶面2a。屬於立方晶閃鋅礦型，且屬於{ 1 . 1 . 1 .} 結晶面相互間的交叉角度爲70.5度（° )(參照「易學電子 繞射與初級結晶學」（1 997年7月10日）、共立出版（股）出 版初版，第57頁）。所以，在屬於{ 1 · 1 .1 ·}-矽單結晶1， 且構成表面的{1·1·1·}結晶面2a中，將存在有依角度70.5 度（°)交叉的{1.1.1·}結晶面2b。Si單結晶的{1.1.1.}結晶 面間隔約3.136A，譬如與磷化硼（BP)的{ 1.1.0.}結晶面間 隔（ = 3.209人）差異約0.073A。即，此結晶面間隔（ = 〇.〇73A) 相對於Si單結晶的{ 1 · 1 · 1 ·}結晶面間隔的差異比率 ( = 0·07 3Α/3.3 16Α)，約達 2.3%。即，在無傾斜之矽{1.1.1·} 結晶面中，譬如在與磷化硼的{1.1 ·0·}結晶面間的結晶面 間隔差異，仍然存在頗大的差異。 此外，交叉於在Π· 1.0·]結晶方向上，依Θ度（0。< 0 < 90。）角度傾斜之{1·1·1·}結晶表面2c的{1.1.1.}結晶面2b 間隔（=上單位A) ’與{1.1.1·}結晶面2b之原本發明結晶面 間隔（ = dQ:A)之間的關係，如第2圖所示。傾斜於[1.1.0·] 結晶方向的U.1.U結晶表面2c中，Si的{1.1.1.}結晶面 1230405 五、發明說明（6 ) 間之間隔（ = d)較d〇( = 3.316A)更延長。在[m]結晶方向 上’父叉於傾斜0 之{ 1 · 1 · 1 .}結晶表面2 c的{ 1 · 1 . 1 }結晶 面2b間隔（ = d)如下式（1)所示。 d(A) = d0/sin( Θ +70.5)° (式（1)) 隨Θ的增大，d將接近dQ。 若依照上述式（1)，設定 0 =5.0。（sin(5.0。+70.5。）= 0.9681) 話’將變爲d = 3.239A，譬如一致於磷化硼·鎵混晶 (B。· 9 5 G a。。5 P )的{ 1 .1 · 0 ·}結晶面之結晶面間隔。若設定爲0 = 9.0° (sin(79.5° ) = 0.9832)，d = 3.19〇A，便可獲得具有依 一致於BNQ.Q3PQ 97之{ 1.1.0}結晶面間隔距離交叉的{丨」」} 結晶面2b之{ 1 . 1 .1 ·}結晶表面2c。若0在5·(Γ以上且9.0 。以下，與單體磷化硼（ΒΡ)之{1.1.0·}結晶面間隔間的差異 比率，亦將減少至低於± 1.0%，而頗適於獲得結晶缺陷密 度較少之優越結晶性磷化硼系半導體層。 本發明實施形態的較佳例子可舉例如：係在將於<1 .1 .〇·> 結晶方位上，傾斜5.0°的（1.1.1.)結晶面設定爲表面的硼 (Β)摻雜ρ型Si單結晶基板上，通過由鋅（Ζη)摻雜磷化硼· 鎵混晶（B^^GausP)所構成的低溫緩衝層，而構成具備有 由{1.1.0.}結晶面所構成鎂（％8)摻雜！3型6().95〇3。.()5層之層 積構造體所構成的複合半導體元件。此外，尙可舉例如： 在將於<-1·1·0·>方向上，傾斜9.0°的（-1.1.1.)結晶面設定 爲表面的磷（Ρ)摻雜Ρ型Si單結晶基板上，通過由無摻雜 (u n d e 〇 p e)磷化硼所構成的低溫緩衝層，然後再層積砂（S1) 1230405 五、發明說明（7) 摻雜的η型磷化硼層，而構成如發光元件用途的層積結構 體。 再者，若將0設定爲7.3° (sin(77.8° ) = 0.9774)，藉由 上述式（1)， d便可合致於單量體的磷化硼（BP)之{1.1.0·} 結晶面的結晶面間隔（ = 3.209A)。若將Θ設定在7.3° ±0.5° 範圍內的話，d便可收束於3.203A( 0 =7.8°之情況）至 3.2 15A(0 =6.8°之情況）範圍內，所以BP的{1·1·〇.}結晶 面間隔（ = 3.209A)與d間的差異比率，便可降低至0.2%以, 下。第3圖所示係在將0爲7.3°之{1.1.1.}結晶面設定爲 表面2c的{ 1 .1 .1 .}-矽單結晶1基板上，成長出平行於基板 1表面的磷化硼（BP)之{1.1.0.}結晶面4之模式圖。在傾斜 於[1.1.0·]結晶方向7.3°的{1.1.1.}結晶表面2c上，交叉 著擁有3.209A間隔的{1.1.1.}結晶面2b。此{1.1.1·}結晶 面2b在表面2c的間隔，因爲一致於磷化硼系半導體層3 之{1.1.0.}結晶面4間隔，因此將促進{1.1.0.}-BP結晶層 3的成長。此外，藉由與交叉於{1.1.1.}-矽單結晶1表面 2c之{1.1.1 ·}結晶面2b面間隔（ = d)的整合性，特別是可獲 得錯位或層積缺陷等結晶缺陷密度較小的結晶性優越之磷 化硼半導體層。在矽單結晶基板表面上，譬如當通過著由 磷化硼系半導體層所構成的低溫緩衝層，然後再層積磷化 硼半導體層的情況時，亦不致喪失獲得由{1.1.0.}所構成 的磷化硼半導體層的效果。可謂利用設置含非晶質的多晶 低溫緩衝層，便具有獲得與矽單結晶基板間，密接性佳之 1230405 五、發明說明（8) {1·1.0·卜磷化硼半導體層的優點。 右利用將傾斜於[1 · 1 · 0 ·]結晶方向適當角度的{ 1 . 1 · 1 . }-結 晶面設定爲表面之{ 1 1 1 }-Si基板上，所形成結晶性佳的 { 1 · 1 · 0 ·}-磷化硼系半導體層，便具有獲得特性優越的複合 半導體元件之優點。本發明實施形態的較佳例子，可舉例 如：將傾斜於<1.0.-1>結晶方位7.0。之（1.-1.1)結晶面設定 爲表面的硼（B)摻雜p型Si單結晶基板上，通過著由無摻 雜磷化硼（BP)所構成的低溫緩衝層，而構成由具備有 {1.1.0.}結晶面所構成之鈹（Be)摻雜p型BP層的層積構造 體所構成的複合半導體元件。特別係將室溫下的禁帶寬度 設定爲3.0 ±0.2eV的磷化硼層所構成結晶性佳之結晶層， 譬如可有效的利用發光元件中，構成單或雙異質（異質）接 合構造發光部的阻障層（覆蓋層）。 除發光元件之外，若利用本發明之結晶性優越的磷化硼 系半導體層的話，便可構成如：受光元件、pn接合型二極 體（整流器）、異質接面雙極性電晶體（HBT)等複合半導體 元件。譬如表面受光型之受光元件則可在下示（A)項所述 導電性基板上，依序層積（B)〜（E)項所記載的機能層而構成 層積構造體。 (A) 將傾斜< 1 · 1 · 0 · >結晶方向7 · 3 °之（1 · 1 . 1 ·)結晶面設定 爲表面的銻（Sb)摻雜η型{1.1.1.}-Si單結晶基板 (B) 由Si摻雜η型磷化硼（BP)所構成之含非晶質體的接 結晶所構成的低溫緩衝層 -10- 1230405 五、發明說明（9) (C) 由主要配置呈平行於（A)所述基板表面的{〗.；!.〇.}_結 晶面所構成的Si摻雜η型磷化硼層。 (D) 主要由單量體之磷化硼（ΒΡ:晶格常數=4.5 3 8 Α)與晶格 失配（mismatch)性較少的立方晶氮化鎵（GaN:晶格常數 = 4·51〇Α)所構成的局阻抗GaN層 (E) 摻雜鈹（Be)的p型磷化硼層。 此層積結構因爲氣化録（GaN)層晶格失配（mismatch)度較 少’且層積於形成適當傾斜（1 · 1 · 1 ·)-矽結晶表面上所形成 的結晶性優越之磷化硼層上，特別可形成結晶性優越的 GaN 層。 再者，由利用結晶性優越之磷化硼系半導體層之下示 (I)〜（IV)項所述機能層的層積構造體，而構成如npn接合 型 HBT。 (I)兼具集電（collector)層作用，且將傾斜<-1.1.〇.>結晶 方向7.3°之（-1.1.1·)結晶面設定爲表面的銻（Sb)摻雜p型 {1.1 .1.} - S i單結晶基板 (Π)由鋅（Zn)摻雜p型磷化硼（BP)所構成之含非晶質體 的多結晶所構成的低溫緩衝層 (m )由主要配置呈平行於（1)所述基板表面的{1.1.0.}-結 晶面之Be摻雜p型磷化硼層所構成的基底（base)層 (IV)由5夕（Si)摻雜η型磷·化硼（BP)所構成射極（emitter) 層。 在上述例中，因爲將經添加賦予較高正孔濃度之鈹爲p -11- 1230405 五、發明說明（1〇) 型雜質的離子結合性較少磷化硼構成基底層，因此特別可 獲得由低阻抗P型導電層所構成的基底層。 【作用】 將朝向[1· 1 .0.]結晶方位傾斜之{ 1 .1. 1 ·}結晶面設爲表面 的矽（Si)單結晶基板，因爲隨所傾斜的角度，便可將交叉 於Si之{ 1.1 .1·}結晶表面的{ 1. 1.1.}結晶面間隔，一致於磷 化硼系半導體層，特別合致於單量體磷化硼（BP)的{1.1.0.} 結晶面間隔，因此具有促進由{1.1 · 0 ·}結晶面所構成磷化 硼系半導體層的成長。 【實施例】 (第1實施例） 在本發明第1實施例中，舉傾斜於<-1 .-1 ·0>結晶方向的 角度爲5.0°的（-1.-1.1)結晶面設定爲表面的矽（Si)單結 晶，當作基板而構成LED的情況作爲例子，用來具體說 明本發明。本第1實施例之LED1A之截面構造，模式的 圖示於第4圖中。 供構成LED1A的層積結構體1B，在以硼摻雜p型（-1.1.0)-矽單結晶（矽）爲基板1〇1上，依序層積具下述 (2)〜（4)所述機能層而構成。基板101表面因爲屬於傾斜於 <-1.-1.〇.>方向5.0°的（-1.1.1.)結晶面，因此在表面上交 叉的{1 1 1 }結晶面（dQ = 3.136A)間隔（ = d)便爲3.272A。 (1)利用三乙化硼（（C2H5)3B)/縢（PH3)/氫（H2)系常壓 MOCVD法，在3 50°C下進行成長，而構成以非晶質爲主 -12- 1230405 五、發明說明（11) 體的多晶鋅（Ζη)摻雜磷化硼（BP)所構成的低溫緩衝層1 02 (2) 利用（C2H5)3B/ 三甲基銦（（CH3)3In)/PH3/H2 系常壓 MOCVD手段，在85CTC下進行成長，由鎂（Mg)摻雜p型 磷化硼•銦混晶（Β^ΙΝ。.。/··晶格常數=4.62 8 A)層所構成的 下部阻障層103。Mg摻雜源採用合雙環物二烯基鎂（分子 式：（bis-(C5H5)2Mg))。 (3) 利用三甲化鎵（（CH3)3Ga)/(CH3)3In/氨（NH3)/H2 系常壓 MOCVD法，在850°C下成長出主要由立方晶矽（Si)摻雜η 型GaQ.75In。25Ν層（晶格常數=4.628Α)所構成的發光層 1〇4(載送氣體濃度与6Xl017cm-3、厚度与120nm)。 (4) 利用（C2H5)3B/PH3/H2 系常壓 MOCVD 法，在 400°C 下 成長出主要由室溫下禁帶寬度爲3.leV的矽摻雜η型磷化 硼（ΒΡ)所構成非晶質的上部阻障層105。 構成下部阻障層103的磷化硼·銦混晶（Β^Ιηα ^ρ)層因 爲隔著低溫緩衝層1 02而設置，因此便將形成不致從低溫 緩衝層1 02剝離的連續膜。此外，下部阻障層1 〇3將形成 由BQ 93InQ ()7P{l.；L0.}結晶面所構成的結晶層。因爲將此 具有依與{1.1.0.}結晶面間隔一致之距離，進行交叉的Si-{1·1·1·}結晶面之（-1.1.1.)單結晶爲基板而形成，因此利用 截面ΤΕΜ方法觀察結晶結構，BQ 93InQ ()7P層內部，將不 致出現錯位或層積缺陷密度，特別係未發現增加。 在上部阻障層105中央，設置由金•錫（Au.Sn)圓形電極 (直徑=120 // m)所構成的歐姆性表面電極106。p型Si基 -13- 1230405 五、發明說明（12) 板101背面幾乎整面設置由鋁（A1)所構成歐姆性背面電極 107，而構成 LED1A。 所構成的藍色L E D 1 A具有下不（a)〜（d)項所述特性。 (a) 發光中心波長：460nm (b) 輝度：7毫燭光 (c) 順方向電壓：3·0伏特（V)(順方向電流=20mA) (d) 反方向電壓：5V(反方向電流=10 // A) 再者，發光光譜的半寬値（所謂：FWHM)爲20nm，屬於 優越的單色性發光。將傾斜於[Π0]方向5.0度的{111 }-Si 單結晶當作基板，而所形成室溫禁帶寬度約3. leV的 {110}·憐化棚•姻混晶（B〇93InQ()7P)下部阻障層1〇3，具有 優越結晶性，因此對高輝度的LED 1 A頗有貢獻。 (第2實施例） 在本發明第2實施例中，舉傾斜於< 1 · -1 · 〇 >結晶方向的 角度爲7.3°的（1.-1.1)結晶面設定爲表面的矽（Si)單結晶 當作基板，而構成肖特基（Schottky)接合型場效型電晶體 (MESFET)的情況爲例子，具體說明本發明。 本第2實施例之MESFET2A之截面構造，模式的圖示 於第5圖中。供構成MESFET2A的層積結構體2B，在無 摻雜高阻抗（1.-1.1)-矽單結晶（矽）爲基板101上，依序層 積具下述（1)〜（4)所述機能層而構成。基板101表面因爲屬 於傾斜於<1.-1.〇.>方向7.3°的（1·-1·1·)結晶面，因此在表 面上交叉的{1·1·1·}結晶面（dQ = 3.l36A)間隔（ = d)便爲 -14- 1230405 五、發明說明（13) 3.209A。 (1) 利用-(G-2H5)3B/PH3/H2 系常壓 MOCVD 法，在 3 5 0 °C 下 進行成長’而構成以非晶質爲主體的多晶無摻雜且高阻抗 磷化硼（BP)所構成的低溫緩衝層1〇2 (2) 同樣的，利用（C2H5)3B/PH3/H2系常壓 MOCVD手 段，在85(TC下進行成長，由氧（0)摻雜高阻抗（室溫下的 阻抗率与1〇4Ω ·οπι)ΒΡ層（晶格常數=4·5 3 8Α)層所構成緩衝 層108。氧摻雜源爲三乙氧基硼（分子式：（c2h5〇)3B)。 (3) 利用（CH3)3Ga/NH3/H2 系常壓 MOCVD 法，在 85 0〇C 下成長出主要由立方晶無摻雜η型GaQ.94InQ.Q6N層（晶格常 數=4·538Α)所構成的動作層1〇9(載送氣體濃度与2 X 1017cnT3、厚度与 40nm)。 (4) 利用（C2H5)3B/PH3/H2 系常壓 MOCVD 法，在 400°C 下 成長出主要由室溫下禁帶寬度爲3. leV的無摻雜n型BP 層’所構成供形成非晶質肯特基閘極（gate)用之接觸層 110° 構成高阻抗緩衝層108的磷化硼（BP)層，形成由{1.1.0.} 結晶面所構成的結晶層。因爲將依使表面的Si { 1 · 1 . 1 .}晶 格面間隔，一致於BP的{1.1.0·}結晶面間隔（d = 3.209A)之 方式的{1.1.1 .}-Si單結晶設定基板，因此利用截面TEM 方法觀察結晶結構，將測得高阻抗緩衝層1 0 8層內部的錯 位密度，低於約1 X 105cm·2。 利用週知的微影（照相蝕刻）技術，如第5圖截面模式圖 -15- 1230405 五、發明說明（14) 所示，限定於將預定形成閘極11 1的區域，去除接觸層 110。其次，在同區域中所裸露出的動作層109表面上， 利用一般的電子束蒸鍍機構，依序真空蒸鍍鈦（Ti)與鋁 (A1)。藉此便構成將接觸到動作層109側設定爲鈦（Ti)， 將表層設定爲鋁（A1)的雙層結構肖特基接觸型閘極111。 閘極1 1 1的電極長度設定爲約2.5 // m。包夾著閘極1 1 1並 呈相對向配置的η型BP接觸層110表面上，設置歐姆 (Ohmic)性源（source)極 112 及汲極（drain)113。源極 112 與汲極113二歐姆電極並未接觸到動作層109，可由任何 金·鎳合金（Au95重量％ + Ge5重量％)、鎳（Ni)及金（Au)三層 構造所構成。 在源極112與汲極113間，當施加+20V的源極•汲極電 壓（ = VDS)時，MESFET2A便將顯示出以下値流特性。 Ο)源極•汲極電流（ID s): 2.5 m A (b) 相互電導（gm):20 毫米 Siemens(mS)/mm (c) 夾止電壓：_10.0V。 特別係因爲將表面爲傾斜於[1.1.0.]結晶方位7.3°的 { 1 . 1 · 1 .}結晶面的{ 1 . 1 .1 ·} · S i單結晶基板1 〇 1，利用爲基板 1〇1而所形成結晶性優越，且高阻抗的{1.1.0. }-BP層構成 緩衝層108，因此具有可防止對緩衝層108內部的IDS遺 漏（1 e a k)效果。 【發明效果】 依照本發明的話，可適當的獲得磷化硼（BP)系半導體 -16- 1230405 五、發明說明（15) 層’特別係獲得由{1.1. 〇 ·}結晶面所構成的{1.1.0.}-磷化硼 系半導體層。因爲將依適當角度傾斜於{1.1.0.}方向之 {1 · 1 · 1 ·}結晶面的設定爲表面的{1 · 1 · 1 ·} -Si單結晶當作基 板’而更構成複合半導體元件，因此利用結晶性優越的磷 化硼系半導體層，便可提供如發光單色性優越的複合半導 體元件。 再者，依照本發明的話，將譬如依與磷化硼（BP)之 {1 · 1 · 0 ·}結晶面間隔相同間隔，交叉S i之{1.1.1.}結晶面的 { 1 · 1 . 1 .} - S i單結晶當作基板’因爲利用結晶性優越且高阻 抗之磷化硼層，而構成場效型電晶體，便可提供夾止特性 優越的MESFET。 【圖式簡單說明】 第1圖係將{ 1.1 · 1 ·}結晶面當作表面的{ 1.1.1 .}-矽單結 晶截面剖示圖。 第2圖係將傾斜於{ 1 · 1 · 0 ·}方向的角度設定爲0的 {1·1·1·}-結晶面，當作表面的{1.1.1·}-矽單結晶截面剖示 圖。 第3圖係在傾斜於{1.1.0·}方向的角度爲7.3。之 表面上’成長出{l.i.o·}-磷化硼系半導體層的 成長模式截面圖。 第4圖係第1實施例中所記載LED截面模式圖。 第5圖係第2實施例中所記載MESFET截面模式圖 【元件符號說明】 -17- 1230405 五、發明說明（16) 1…{l.l.l.}-Si單結晶基板 1 A · · · LED 1 B，2 B…層積結構體 2A··· MESFET 2 a…形成S i單結晶表面的{ 1. 1 .1 .}結晶面 2b···交叉於形成表面之{ 1 .1 .1 .}-結晶面的{ 1 1 1 }-Si結晶面 2c…傾斜於[1 10]方向0 °的{ 1 1 1 }-Si結晶表面 3…{1.1.0.}-磷化硼半導體層 4…磷化硼的{1·1·〇.}-結晶面 101…單結晶基板 102…低溫緩衝層 1 03…下部阻障層 104…發光層 1 0 5…上部阻障層 1 0 6…表面電極 1 0 7…背面電極 108…高阻抗緩衝層 1 09…GalnN動作層 1 10…BP接觸層 111…Ti/Al鬧極 112··· AuGe/Ni/Au 源極 113·.· AuGe/Ni/Au 汲極 •18-1230405 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a technology for forming a composite semiconductor element using a silicon (Si) single crystal (silicon) having a specific plane orientation as a substrate. [Conventional Technology] It is known to contain boron phosphide (BP) based IE-V group compound semiconductors (boron phosphide based semiconductors) containing boron (B) and phosphorus (P) as constituent elements! ] J-V Group One of compound semiconductors (Refer to: Terawa Iwa, "Semiconductor Device Theory" (title) (March 30, 995), the first edition of Peifeng Museum, pages 26-28). Boron Phosphide (BP) is made by Philips with an ion-binding degree of less than 0.006 (Reference: By Philips, "Semiconductor Bond Theory" (July 25, 1985), Yoshioka Bookstore, 3rd Edition, 51 Page), and almost all covalently bonded substances. In addition, because it is a zinc-blend type cubic crystal, it has a receding valence band structure (see Ikuko Toshiaki and Ikuko Toyoaki, "Introduction to Basic Physical Properties of Composite Semiconductors" (title, Chinese translation) (1991) September 10th, 2010), the first edition of the Peifeng Pavilion, pages 14 ~ 17). Therefore, boron phosphide has the advantage that a p-type conductive layer can be easily obtained. In the conventional technology, various composite semiconductor elements are constituted by using a boron phosphide layer provided on a single crystal substrate. For example, a heterojunction bipolar transistor using a boron phosphide layer is known (see HBTK, J. Electrochem. Soc., 125 (4) (1 978), pp. 663 ~ 637). In addition, there is a solar cell using a boron phosphide layer as a window layer (see J. Electrochem. Soc., Above).尙 There is a technology that reveals light-emitting diodes (LEDs) or laser diodes (LDs) that make up blue or green bands without using boron phosphide and its mixed crystals (1230405) 5. Description of the invention (2) (Japanese Patent No. 2 809690, ② No. 2809691, ③ Gazette No. 2809692, and ④ US Patent No. 6,069,021). The single crystal boron phosphide (BP; boron monophosphide) has a lattice constant of about 4.5 3 8 A (see "Semiconductor Device Theory" above, page 28). In addition, the silicon (Si) single crystal used as the substrate is a zinc-blend type crystal of the same cubic crystal, and has a lattice constant of about 5.431A (refer to the above-mentioned "Semiconductor Device Theory", page 28). Therefore, the degree of lattice mismatch relative to the silicon single crystal lattice constant (= 5.431 A), expressed as the ratio of the lattice constant difference (= 〇.893A) of the two crystals, is as large as 16.6%. In order to prevent the boron phosphide layer caused by this large lattice mismatch from peeling off the surface of the Si substrate, it has been revealed that the low temperature will be composed of polycrystalline boron phosphide containing amorphous grown at lower temperatures. The buffer layer is a technical means provided on the surface of the Si substrate (refer to the aforementioned US Patent No. 6,069,02 1). [Problems to be Solved by the Invention] In the conventional technology, a boron phosphide-based semiconductor layer is formed of, for example, a silicon single crystal substrate having a {1.0.0} or {1.1 · 1 ·} crystal plane (refer to the above US) (Patent No. 6,069,021). In particular, the {1.1.1.} Crystal plane has a denser concentration of silicon atoms than the {1 · 0 · 0 ·} crystal plane, so it suppresses the formation of boron (B) and phosphorus ( P) The internal penetration of the silicon single crystal substrate is quite effective. However, the {1.1.1 ·} crystal planes of silicon single crystals are separated from each other by about 3.136A. -4- 1230405 V. Description of the invention (3) In addition, the {1.1.0.} Crystal plane interval of boron phosphide (BP: lattice constant = 4 · 5 3 8A) is 3.209 A, and {1 · 1. 1 ·} The crystal plane intervals are not uniform. Therefore, it is known that the silicon boride layer formed on a silicon single crystal substrate with the {1 · 1.1 ·} crystal plane as the surface will cause the formation of a rough crystal layer containing a large number of dislocations or lamination defects. And so on. In view of this, the present invention provides a space between {1 · 1 · 1.} Crystal planes of silicon that intersect on the {1 · 1 · 1 ·} silicon single crystal surface to form {1 ·· with boron phosphide. 1 · 0.} Silicon single crystals with uniformly spaced crystal planes are used as a substrate technology to obtain a boron phosphide-based semiconductor layer with excellent crystallinity. [Means for Solving the Problems] The main purpose of the present invention is to solve the problems of the conventional techniques by specifying the orientation of the crystal planes that constitute the surface of the silicon single crystal substrate. In other words, the present invention is: (1) A composite semiconductor device provided on the surface of a substrate comprising: a silicon (Si) single crystal (silicon); and a substrate containing boron (B) and phosphorus (P). ) Is a composite semiconductor element of a boron phosphide (BP) -based semiconductor layer constituting an element; wherein, it is oriented toward the crystal orientation of Π.Ι.Ο.], and is inclined at an angle of 5.0 ° (.) Or more and 9.0 ° (°) or less {1.1.1.} The silicon single crystal whose surface is set as the surface is used as a substrate. (2) The composite semiconductor device described in (1) above, is a {iii} crystal plane inclined at an angle range of 7 · 3 ± 0 · 5 degrees (.) Toward the [丨.;! · 〇 ·] crystal orientation. A silicon single crystal set as a surface is used as a substrate. (3) The composite semiconductor device described in (1) above is oriented in a direction of 1230405 V. Description of the invention (4) [1.1.0.] Crystal orientation, inclined at 5.0 degrees (°) to 9.0 degrees (°) The angle of the {1. 1 · 1.} Crystal plane is set on the surface of a silicon single crystal substrate, and a low-temperature buffer layer composed of a boron phosphide-based semiconductor layer passes through the layer and has {1 .1.0 ·} crystals laminated thereon. The surface is composed of a layered structure of a boron phosphide-based semiconductor layer. (4) The composite semiconductor device described in (2) above is formed by {1 · 1 · 1 ·} crystals which are inclined at an angle of 7.3 ± 0.5 degrees (°) toward the [1.1.0.] Crystal orientation. A silicon single crystal substrate having a surface as a surface is passed through a low-temperature buffer layer composed of a boron phosphide-based semiconductor layer, and a boron phosphide (BP) semiconductor having a {1 · 1 · 0 ·} crystal plane is laminated thereon. It consists of a layered structure. (5) A light-emitting element is composed of the composite semiconductor element according to any one of (1) to (4) above. (6) A seed crystal system is composed of the composite semiconductor element according to any one of (1) to (4) above. In addition, the present invention is: (7) A method for manufacturing a composite semiconductor element, which is inclined at an angle of 5.0 [deg.] (°) to 9.0 [deg.] ([1. 1 · 1 ·} A single crystal substrate with a crystal surface as the surface is passed through a low-temperature buffer layer composed of a boron-based semiconductor layer, and then phosphorous having a {1 · 1 · 〇 ·} crystal surface is laminated. It is composed of a layered structure of a boron-based semiconductor layer. (8) A method for manufacturing a composite semiconductor device, which is a {1.1.1.} Crystal in an angle range that will be oriented toward Π .; [.〇.;! Tilted by 7.3 ± 0.5 degrees (°) A single-crystal sand substrate with a surface as the surface is passed through a low-temperature buffer layer composed of a boron phosphide semiconductor 1230405 V. Description of the invention (5) The bulk layer is then laminated with a {1.1.0 ·} crystal plane A layered structure of a boron phosphide (BP) semiconductor layer. [Inventive Mode] In order to explain the present invention, a cross-sectional schematic diagram of {1.1.1 ·} -silicon single crystal 1 with {1.1.1.} Crystal plane 2a as a surface is illustrated in FIG. 1 as an example. {1 · 1 · 1 ·} -The surface of the single crystal of sand is not inclined to the correct {1 · 1 · 1.} Crystal surface 2a. It belongs to cubic sphalerite type and belongs to the {1. 1.1. 1.} Crystal planes with an intersection angle of 70.5 degrees (°) (refer to "Easy Electron Diffraction and Primary Crystallography" (July 1997) 10th), Kyoritsu Publishing Co., Ltd. publishes the first edition, page 57). Therefore, in the {1 · 1 · 1 ·} -silicon single crystal 1, and the {1 · 1 · 1 ·} crystal plane 2a constituting the surface, there will be {1.1. 1 ·} Crystal plane 2b. The {1.1.1.} Crystal plane spacing of Si single crystal is about 3.136A, for example, it is about 0.073A different from the {1.1.0.} Crystal plane spacing of boron phosphide (BP). That is, the difference ratio (= 0.07 3A / 3.3 16A) of this crystal plane interval (= 0.03A) to the {1 · 1 · 1 ·} crystal plane interval of the Si single crystal is approximately 2.3%. That is, in the non-tilted silicon {1.1.1 ·} crystal plane, for example, there is still a considerable difference in the crystal plane spacing from the {1.1 · 0 ·} crystal plane of boron phosphide. Further, the {1.1.1.1} crystal on the {1 · 1 · 1 ·} crystal surface 2c inclined at a angle of Θ degrees (0. < 0 < 90.) in the direction of Π · 1.0 ·] crystallized is crossed. The relationship between the plane 2b interval (= upper unit A) 'and the crystal surface interval (= dQ: A) of the present invention of {1.1.1 ·} crystal plane 2b is shown in FIG. 2. In the U.1.U crystal surface 2c inclined to the [1.1.0 ·] crystal direction, the {1.1.1.} Crystal surface of Si 1230405 V. The interval between the invention (6) (= d) is greater than d0 ( = 3.316A). In the [m] crystallographic direction, the parent's fork is at the {1 · 1 · 1.} Crystal surface 2 c tilted at {1 · 1.. 1} crystal surface 2b. d (A) = d0 / sin (Θ +70.5) ° (Equation (1)) As Θ increases, d will approach dQ. In accordance with the above formula (1), set 0 = 5.0. (Sin (5.0. + 70.5.) = 0.9681) Then 'will become d = 3.239A, such as {1.1 .1 consistent with boron phosphide-gallium mixed crystal (B. · 9 5 G a. 5 P) · 0 ·} Crystal plane spacing. If it is set to 0 = 9.0 ° (sin (79.5 °) = 0.9832) and d = 3.19〇A, we can obtain the {1.1.0} crystal plane spacing distance crossing according to BNQ.Q3PQ 97. } Crystal surface 2b of {1. 1.1 .1}} crystal surface 2c. If 0 is above 5 · (Γ and 9.0. Below, the difference ratio from the {1.1.0 ·} crystal plane interval of the monomer boron phosphide (BP) will also be reduced to less than ± 1.0%, which is quite suitable. In order to obtain a superior crystalline boron phosphide-based semiconductor layer with less crystal defect density. A preferred example of the embodiment of the present invention may be, for example, a crystal orientation with a tilt of 5.0 in < 1.1.〇 · > The (1.1.1.) Crystal plane of ° is set on the surface of a boron (B) -doped p-type Si single crystal substrate with a surface, and a boron phosphide-gallium mixed crystal (B ^^ GausP) doped with zinc (Zη) is used. The structure is composed of a low-temperature buffer layer and a layered structure with 5 layers of doped magnesium (% 8) doped with {1.1.0.} Crystal planes! Type 3 6 (). 95〇3 .. () The compound semiconductor element is composed of, for example ,: (-1.1.1.) Crystal plane inclined at 9.0 ° in the direction of < -1 · 1 · 0 · > is set as the surface phosphorus (P ) Doped P-type Si single crystal substrate, through the low-temperature buffer layer composed of undoped boron phosphide, and then laminated sand (S1) 1230405 V. Description of the invention (7) Doped η-type boron phosphide layer, and constitutes Laminated structure for optical device applications. If 0 is set to 7.3 ° (sin (77.8 °) = 0.9774), d can be combined with boron phosphide ( BP) of the {1.1.0 ·} crystal plane interval (= 3.209A). If Θ is set in the range of 7.3 ° ± 0.5 °, d can be converged at 3.203A (0 = 7.8 °) ) To 3.2 15A (in the case of 0 = 6.8 °), so the difference ratio between {1 · 1 · 〇.} Crystal plane interval (= 3.209A) of BP and d can be reduced to less than 0.2%, below Figure 3 shows that the {1.1.1.}-Si single crystal 1 substrate with the {1.1.1.} Crystal plane of 0 and 7.3 ° as the surface 2c is grown parallel to the surface of the substrate 1 Schematic diagram of {1.1.0.} Crystal plane 4 of boron phosphide (BP). On the {1.1.1.} Crystal surface 2c inclined at 7.3 ° from the [1.1.0 ·] crystal direction, it has 3.209 cross The {1.1.1.} Crystal plane 2b of A interval. The interval of the {1.1.1 ·} crystal plane 2b on the surface 2c is consistent with the {1.1.0.} Crystal plane 4 interval of the boron phosphide-based semiconductor layer 3. Therefore, it will promote the growth of {1.1.0.}-BP crystal layer 3. In addition, by intersecting with {1.1.1.}-Si single crystal 1 The conformity of the {1.1.1 ·} crystal plane 2b plane interval (= d) of the surface 2c, in particular, it is possible to obtain a boron phosphide semiconductor layer with excellent crystallinity with a small crystal defect density such as dislocation or lamination defects. On the surface of the silicon single crystal substrate, for example, when a low-temperature buffer layer composed of a boron phosphide-based semiconductor layer is passed, and then a boron phosphide semiconductor layer is further laminated, the gain obtained by {1.1.0.} Is not lost. Effect of the formed boron phosphide semiconductor layer. It can be said that the use of an amorphous polycrystalline low-temperature buffer layer has the advantage of obtaining 1230405 with silicon single crystal substrates and good adhesion. V. Description of the invention (8) {1 · 1.0 · B boron phosphide semiconductor layer. On the right, a {1. 1 · 1.} -Crystal plane that is inclined at an appropriate angle to the [1 · 1 · 0 ·] crystallographic direction is set on the surface of the {1 1 1} -Si substrate, and a { 1 · 1 · 0 ·}-boron phosphide-based semiconductor layer has the advantage of obtaining a composite semiconductor element with excellent characteristics. A preferred example of the embodiment of the present invention may be, for example, inclined to a crystal orientation of < 1.0.-1 > 7.0. The (1.-1.1) boron (B) doped p-type Si single crystal substrate with the crystal plane set to the surface is formed by a low-temperature buffer layer made of undoped boron phosphide (BP). A composite semiconductor element including a beryllium (Be) doped p-type BP layer composed of a {1.1.0.} Crystal plane. In particular, a crystal layer with a good crystallinity is formed by a boron phosphide layer having a band gap width of 3.0 ± 0.2 eV at room temperature. For example, a single or double heterojunction (hetero) junction structure light-emitting portion can be effectively used in a light-emitting element. Barrier layer (overlay). In addition to the light-emitting element, if the boron phosphide-based semiconductor layer of the present invention has excellent crystallinity, a light-receiving element, a pn junction diode (rectifier), and a heterojunction bipolar transistor (HBT) can be constructed. ) And other composite semiconductor devices. For example, a light-receiving element of the surface light-receiving type can be a laminated structure in which the functional layers described in (B) to (E) are sequentially laminated on a conductive substrate described in (A) below. (A) Set the antimony (Sb) -doped n-type {1.1.1.} Crystal surface with (1 · 1. · 1 ·) crystal orientation with a tilt < 1 · 1 · 0 · > of crystal orientation 7 · 3 ° -Si single crystal substrate (B) Low temperature buffer layer composed of Si-doped n-type boron phosphide (BP) and containing amorphous crystals -10- 1230405 V. Description of the invention (9) (C ) A Si-doped n-type boron phosphide layer composed of {}.;!. 〇.} _ Crystal planes mainly arranged parallel to the substrate surface of (A). (D) Cubic gallium nitride (GaN: Lattice constant = 4 ·) mainly composed of monolithic boron phosphide (Bp: Lattice constant = 4.5 3 8 Α) and less lattice mismatch. 51OA) is a p-type boron phosphide layer doped with beryllium (Be) with a local impedance GaN layer (E). This layered structure is superior in crystallinity formed on the surface of the silicon crystal due to the low degree of lattice mismatch of the GaN layer and the layered formation on the appropriately inclined (1 · 1 · 1 ·) silicon surface. On the boron phosphide layer, a GaN layer having excellent crystallinity can be formed. Furthermore, an npn junction type HBT is constituted by a laminated structure using a functional layer described in (I) to (IV) below a boron phosphide-based semiconductor layer having excellent crystallinity. (I) Antimony (Sb) -doped p that has a collector layer function and has a (-1.1.1 ·) crystal plane with a tilt of <-1.1.〇. ≫ Type {1.1 .1.}-S i single crystal substrate (Π) is a low-temperature buffer layer (m) composed of polycrystalline body containing amorphous body composed of zinc (Zn) doped p-type boron phosphide (BP) ) The base layer (IV) composed of a Be-doped p-type boron phosphide layer mainly arranged in a {1.1.0.}-Crystal plane parallel to the substrate surface (1) is composed of 5 y (Si ) Doped n-type phosphorus · boron (BP) doped emitter layer. In the above example, since beryllium with a higher positive pore concentration was added as p -11-1230405 V. Description of the invention (10) type impurities have less ion-binding properties and boron phosphide constitutes the base layer, so it can be obtained particularly A base layer composed of a low-resistance P-type conductive layer. [Function] Set the {1 .1. 1 ·} crystal surface inclined to the [1 · 1. .0.] Crystal orientation as the surface of the silicon (Si) single crystal substrate, because the angle can be crossed The {1. 1.1.} Crystal plane spacing on the {1.1 .1 ·} crystal surface of Si is consistent with the boron phosphide-based semiconductor layer, and is particularly consistent with {1.1.0.} Of the monolithic boron phosphide (BP). Since the crystal planes are spaced, the growth of the boron phosphide-based semiconductor layer composed of {1.1 · 0 ·} crystal planes is promoted. [Embodiment] (First Embodiment) In the first embodiment of the present invention, the (-1.-1.1) crystal plane set with an angle of 5.0 ° inclined to the < -1.-1 > > crystal direction is set. The case where a single crystal of silicon (Si) on the surface is used as a substrate to constitute an LED is used to describe the present invention in detail. The cross-sectional structure of the LED 1A according to the first embodiment is schematically shown in FIG. 4. The laminated structure 1B constituting the LED 1A is sequentially laminated on the substrate 101 using boron-doped p-type (-1.1.0) -silicon single crystal (silicon) as the substrate 101, and the following (2) to (4) ). Since the surface of the substrate 101 is a (-1.1.1.) Crystal plane inclined at 5.0 ° in the < -1.-1.〇. ≫ direction, the {1 1 1} crystal plane (dQ = 3.136) intersected on the surface. A) The interval (= d) is 3.272A. (1) Using boron triacetate ((C2H5) 3B) / 縢 (PH3) / hydrogen (H2) system at normal pressure MOCVD method to grow at 3 50 ° C, and the structure is mainly amorphous-12- 1230405 V. Description of the invention (11) Low-temperature buffer layer composed of polycrystalline zinc (Zη) doped with boron phosphide (BP) 1 02 (2) Use of (C2H5) 3B / trimethylindium ((CH3) 3In ) / PH3 / H2 is a normal-pressure MOCVD method. It is grown at 85CTC. It is doped with p-type boron phosphide-indium mixed crystal (B ^ ΙΝ ..... / lattice constant = 4.62 8 A). ) Layer of the lower barrier layer 103. As the Mg doping source, a bicyclic dienyl magnesium (molecular formula: (bis- (C5H5) 2Mg)) is used. (3) Using Ga (tri) gallium ((CH3) 3Ga) / (CH3) 3In / ammonia (NH3) / H2) atmospheric pressure MOCVD method, grows at 850 ° C mainly by cubic silicon (Si) doped n-type GaQ.75In. A light-emitting layer 104 composed of a 25N layer (lattice constant = 4.628A) (carrier gas concentration and 6 × 1017 cm-3, thickness and 120 nm). (4) Using the (C2H5) 3B / PH3 / H2 series atmospheric MOCVD method, grown at 400 ° C mainly by silicon-doped n-type boron phosphide (BPP) with a band gap of 3.leV at room temperature. An amorphous upper barrier layer 105 is formed. Since the boron phosphide-indium mixed crystal (B ^ Iηα ^ ρ) layer constituting the lower barrier layer 103 is provided through the low-temperature buffer layer 102, a continuous film is formed so as not to be peeled from the low-temperature buffer layer 102. In addition, the lower barrier layer 103 will form a crystalline layer composed of BQ 93InQ () 7P {1 .; L0.} Crystal plane. This is formed by forming (-1.1.1.) Single crystals of Si- {1 · 1 · 1 ·} crystal planes which intersect with each other at a distance consistent with the {1.1.0.} Crystal plane interval. Using the cross-section TEM method to observe the crystalline structure, the interior of the BQ 93InQ () 7P layer will not cause dislocation or lamination defect density, especially no increase was found. At the center of the upper barrier layer 105, an ohmic surface electrode 106 composed of a gold-tin (Au.Sn) circular electrode (diameter = 120 // m) is provided. p-type Si-based -13- 1230405 V. Description of the invention (12) Almost the entire back surface of the plate 101 is provided with an ohmic back electrode 107 made of aluminum (A1) to constitute LED1A. The formed blue L E D 1 A has the characteristics described in the following items (a) to (d). (a) Luminous center wavelength: 460nm (b) Brightness: 7 millicandles (c) Forward voltage: 3.0 volts (V) (forward current = 20mA) (d) Reverse voltage: 5V (reverse current = 10 // A) Furthermore, the half-width chirp of the luminescence spectrum (so-called: FWHM) is 20nm, which is a superior monochromatic luminescence. The {111} -Si single crystal, which is 5.0 degrees oblique to the [Π0] direction, is used as the substrate, and the resulting room temperature band gap is about 3.10 volts. 7P) The lower barrier layer 10 has excellent crystallinity and therefore contributes to the high-brightness LED 1 A. (Second Embodiment) In a second embodiment of the present invention, a silicon (1.-1.1) crystal plane having an angle of 7.3 ° inclined to the < 1 · -1 · 〇 > crystal direction is set as the surface silicon ( A Si) single crystal is used as a substrate and a Schottky junction field effect transistor (MESFET) is constructed as an example, and the present invention will be specifically described. The cross-sectional structure and pattern of the MESFET 2A in the second embodiment are shown in FIG. 5. The layered structure 2B constituting the MESFET 2A is laminated on the undoped high-resistance (1.-1.1) -silicon single crystal (silicon) substrate 101 in the following order (1) to (4) Functional layer. Since the surface of the substrate 101 is a (1 · -1 · 1 ·) crystal plane inclined at 7.3 ° in the < 1.-1.〇. ≫ direction, the {1 · 1 · 1 ·} crystal plane intersecting on the surface (DQ = 3.l36A) The interval (= d) is -14-1230405 V. Description of the invention (13) 3.209A. (1) The-(G-2H5) 3B / PH3 / H2 series atmospheric MOCVD method is used to grow at 350 ° C to form a polycrystalline non-doped and high-resistance phosphating based on amorphous. Low temperature buffer layer 10 made of boron (BP) (2) Similarly, using (C2H5) 3B / PH3 / H2 normal pressure MOCVD method, it grows at 85 (TC) and is doped with oxygen (0). Impedance (resistance at room temperature and 104 Ω · οπι) buffer layer 108 composed of PB layer (lattice constant = 4 · 5 3 8A) layer. The oxygen doping source is triethoxyboron (Molecular formula: (c2h5 〇) 3B). (3) Using the (CH3) 3Ga / NH3 / H2 series atmospheric MOCVD method at 85 0 ° C to grow a cubic undoped n-type GaQ.94InQ.Q6N layer (lattice constant = 4.538A) composed of an operating layer 10 (carrying gas concentration and 2 X 1017cnT3, thickness and 40nm). (4) Using (C2H5) 3B / PH3 / H2 system at normal pressure MOCVD method, at 400 ° C The lower growth mainly consists of a non-doped n-type BP layer with a band gap of 3. leV at room temperature. The contact layer for forming an amorphous Kentky gate 110 ° constitutes a high-impedance buffer layer 108. Layer of boron phosphide (BP) formed by the {1.1.0.} Crystal plane The crystalline layer is composed because the surface Si {1 · 1.. 1.} Lattice plane spacing is consistent with the {1.1.1.0 ·} crystal plane spacing (d = 3.209A) of the BP {1.1. 1.}-Si single crystal set substrate, so the cross-section TEM method is used to observe the crystal structure, and the dislocation density inside the 108 layer of the high-resistance buffer layer is measured to be lower than about 1 X 105 cm · 2. Using a well-known lithography (Photoetching) technology, as shown in the cross-section pattern in Figure 5-15-1230405 V. Description of the invention (14), is limited to the area where the gate electrode 11 1 is to be formed, and the contact layer 110 is removed. Second, in the same area On the surface of the exposed operating layer 109, titanium (Ti) and aluminum (A1) are sequentially vacuum-deposited by a general electron beam vapor deposition mechanism. In this way, the side contacting the operating layer 109 is set to titanium (Ti ), The surface layer is set to a double-layer Schottky contact gate 111 of aluminum (A1). The electrode length of the gate 1 1 1 is set to about 2.5 // m. The gate 1 1 1 is sandwiched and faces each other. On the surface of the disposed n-type BP contact layer 110, an ohmic source electrode 112 and a drain 113 are provided. The source electrode 112 and the drain electrode 113 The two-ohm electrode is not in contact with the operating layer 109, and may be composed of any three-layer structure of gold-nickel alloy (Au95% by weight + Ge5% by weight), nickel (Ni), and gold (Au). Between source 112 and drain 113, when + 20V source-drain voltage (= VDS) is applied, MESFET2A will show the following flow characteristics. 〇) Source / drain current (ID s): 2.5 m A (b) Mutual conductance (gm): 20 mm Siemens (mS) / mm (c) Pinch-off voltage: _10.0V. This is particularly because the surface is a {1. 1 · 1 ·} · S i single crystal substrate 1 〇1, which is inclined at a crystal orientation of 7.3 ° in the [1.1.0.] Crystal orientation, and is used as The substrate 101 has excellent crystallinity and a high-resistance {1.1.0.}-BP layer constitutes the buffer layer 108. Therefore, it has the effect of preventing IDS leakage (1 eak) from occurring inside the buffer layer 108. [Effects of the Invention] According to the present invention, a boron phosphide (BP) -based semiconductor can be appropriately obtained. 16-1230405 V. Description of the invention (15) The layer 'particularly obtains a {1.1. 〇 ·} crystal plane { 1.1.0.}-Boron phosphide-based semiconductor layer. Because the {1 · 1 · 1 ·} crystal plane inclined at an appropriate angle in the {1.1.0.} Direction is set to the surface {1 · 1 · 1 ·} -Si single crystal as the substrate ', the composition is more complex For semiconductor devices, the use of a boron phosphide-based semiconductor layer having excellent crystallinity can provide a composite semiconductor device having excellent light emission monochromaticity. In addition, according to the present invention, for example, the {1 · 1 · 0 ·} crystal planes of boron phosphide (BP) are intersected at the same interval, and {1 · 1 1.}-S i single crystal as substrate 'Because it uses a boron phosphide layer with excellent crystallinity and high resistance to form a field-effect transistor, it can provide a MESFET with excellent clamping characteristics. [Brief description of the drawing] Fig. 1 is a cross-sectional view of the {1.1.1.}-Si single-crystal cross section with the {1.1 · 1 ·} crystal plane as the surface. Figure 2 is a {1 · 1 · 1 ·} -crystalline plane with an angle of 0 in the {1 · 1 · 0 ·} direction set to 0 as the surface {1.1.1 ·} -silicon single crystal cross section Illustration. Figure 3 shows an angle of 7.3 when tilted in the {1.1.0 ·} direction. On the surface, a growth pattern cross section of {l.i.o.}-Boron phosphide-based semiconductor layer is grown. Fig. 4 is a schematic sectional view of the LED described in the first embodiment. FIG. 5 is a cross-sectional schematic diagram of a MESFET described in the second embodiment. [Description of element symbols] -17-1230405 V. Description of the invention (16) 1 ... {lll} -Si single crystal substrate 1 A · · · LED 1 B, 2 B ... Laminated structure 2A ... MESFET 2 a ... {1.1.1.} Crystal plane 2b that forms the Si single crystal surface {b.1.1.1.} That intersects the formation surface {1 1 1} -Si crystal plane 2c of the crystal plane ... {1 1 1} -Si crystal surface 3 inclined to 0 ° in the [1 10] direction 3 ... {1.1.0.}-Boron phosphide semiconductor layer 4 ... {1 · 1 · 〇.}-Crystal plane 101 of boron oxide ... Single crystal substrate 102 ... Low temperature buffer layer 03 ... Lower barrier layer 104 ... Light emitting layer 1 0 5 ... Top barrier layer 1 0 6 ... Surface electrode 1 0 7 ... back electrode 108 ... high-impedance buffer layer 1 09 ... GalnN operating layer 1 10 ... BP contact layer 111 ... Ti / Al alarm 112 ... AuGe / Ni / Au source 113 ... AuGe / Ni / Au Drain pole 18-