200414569 玖、發明說明： (一） 發明所屬之技術領域 本發明是關於在結晶基板上具有瓜族氮化物半導體 (AlxGaYlnux + wNiOSXd，〇<YSl 以及 0<X + YS1)結晶層， 具備接觸電阻小的歐姆性電極之IE族氮化物半導體元件。 (二） 先前技術 m族氮化物半導體元件的一例習知以來已知有氮化鎵 (GaN)系發光二極體（LED)或雷射二極體（LD)以及肖特基 (Schot tky)接觸型場效型電晶體（MESFET)(例如參照專利文 獻1)。這些元件是以具備由氮化鋁/鎵/銦（AlaGabIneN:0S a，b,cSl，a + b + c = l)混晶（mixed crystal)等構成的功能層 的疊層構造體爲基礎而構成（例如參照專利文獻2 )。例如包 含以在室溫的帶隙（band gap)爲約3 · 4eV的GaN的氮化鎵/ 銦混晶（GabIneN:0<b，c<l，b + c = l)係當作短波長LED或LD 用途的發光層利用（例如參照專利文獻3 )。在構成疊層構造 體的一部分的功能層配設歐姆性接觸的歐姆性電極（◦ hm i c electrode)而形成有元件。例如在η形的氮化鎵（GaN)電子 供給層的表面上配設使鈦（T i )/鋁（A 1 )重疊的歐姆性源極 (source)以及汲極（drain)電極而形成有高遷移率 (mob Π i t y )型的場效型電晶體（例如參照文獻1 )。 而且，構成如上述的m族氮化物半導體元件的 AlaGabIneN(0$a，b,cSl, a + b + c = l)混晶層習知係以藍寶石 (s a p p h i r e ) ( a - A 1 20 3 )爲基板而沉積（例如參照專利文獻4 ) 。但是，藍寶石與 AlaGablnel^UO^ajjSl，a + b + c = l)混晶 200414569 等的晶格的失配（m i s m a t c h)大。例如藍寶石與纖鋅礦 (%111^2丨^)結晶型（]—的晶格失配度約16%的話爲大（參照 文獻2 ) °医1此’例如在成長於藍寶石基板上的氮化鎵層的 內部起因於兩者間的大晶格失配，達到包含有約1 X丨〇 5個 / cm2左右的多量的差排（d i s丨〇ca t i 0n )(參照文獻3 )。 【專利文獻1】美國專利第6，06 9，〇21號說明書 【專利文獻2】日本特開平i〇_ 562〇2號公報 【專利文獻3】日本特公昭5 5 - 3 8 3 4號公報 【專利文獻4】日本特開平丨〇 _丨〇 7 3丨5號公報 【文獻1】赤崎勇編著[Advanced Electronic Ι-21ΙΠ族氮 化物半導體]初版（股）培風館1999年12月8日，ρ·288- 289 [文獻 2] (Isamu AKASAKI，Hiroshi AMANO，Yasuo KOIDE, Kazumasa HIRAMATSU，and Nobuhiko SAWAKI )、(EFFECTS OF AIN BUFFER LAYER ON CRYSTALL0GR0PHIC STRUCTURE AND ON ELECTRICAL AND OPTICAL PROPERTIES OF GaN AND Gal-XA1XN(0<X^0.4) FILMS GROWN ON SAPPHIRE SUBSTRATE BY M0VPE)(Journal of Crystal Growth) 1 998 年（荷蘭）第 98 卷，p · 209-219 【文獻3】赤崎勇編著 [Advanced Electronic I - 211Π族氮 化物半導體]初版（股）培風館 1 9 9 9年12月8日， p.211-213 (三）發明內容 但是，如例如在六方晶（hexagona 1 )纖鋅礦結晶型的 -6 - 200414569200414569 (1) Description of the invention: (1) Technical field to which the invention belongs The present invention relates to a crystalline layer of a guar nitride semiconductor (AlxGaYlnux + wNiOSXd, 0 < YSl and 0 < X + YS1) on a crystalline substrate, and has contact resistance Group IE nitride semiconductor device with small ohmic electrode. (2) An example of the m-type nitride semiconductor device of the prior art has been known since the gallium nitride (GaN) -based light emitting diode (LED) or laser diode (LD) and Schottky (Schot tky) Contact type field effect transistor (MESFET) (for example, refer to Patent Document 1). These elements are based on a laminated structure including a functional layer composed of aluminum nitride / gallium / indium (AlaGabIneN: 0S a, b, cSl, a + b + c = l), and the like. Structure (for example, refer to Patent Document 2). For example, a gallium nitride / indium mixed crystal (GabIneN: 0 < b, c < l, b + c = l) including GaN with a band gap of about 3.4 eV at room temperature is regarded as a short wavelength Use of a light-emitting layer for LED or LD applications (see, for example, Patent Document 3). An element is formed by disposing an ohmic electrode (◦ hm i c electrode) in the functional layer constituting a part of the laminated structure. For example, an n-shaped gallium nitride (GaN) electron supply layer is formed with an ohmic source and a drain electrode formed by overlapping titanium (T i) / aluminum (A 1) on the surface. A field-effect transistor of a high mobility (mob Π ity) type (for example, refer to Reference 1). In addition, the AlaGabIneN (0 $ a, b, cSl, a + b + c = l) mixed crystal layer constituting the m-type nitride semiconductor device as described above is conventionally made of sapphire (a-A 1 20 3) It is deposited for a substrate (for example, refer to Patent Document 4). However, sapphire and AlaGablnel ^ UO ^ ajjSl, a + b + c = l) mixed crystal 200414569 and other lattice mismatches (m i s m a t c h) are large. For example, the sapphire and wurtzite (% 111 ^ 2 丨 ^) crystal form (]-is about 16% if the lattice mismatch is large (Ref. 2). 1) This example is nitrogen grown on a sapphire substrate. The inside of the gallium layer is caused by the large lattice mismatch between the two, reaching a large number of differential rows (dis 丨 〇ca ti 0n) containing about 1 × o05 / cm2 (see reference 3). Patent Document 1] US Patent No. 6,06 9,002 [Patent Document 2] Japanese Patent Application Laid-Open No. i0_562〇2 [Patent Document 3] Japanese Patent Publication No. 5 5-3 8 3 4 [ Patent Document 4] Japanese Patent Application No. 丨 〇_ 丨 〇7 3 丨 5 [Document 1] Edited by Akasaki Yong [Advanced Electronic Ι-21ΙΠ Group Nitride Semiconductor] First Edition (Share) Peifeng Pavilion December 8, 1999, ρ · 288- 289 [Document 2] (Isamu AKASAKI, Hiroshi AMANO, Yasuo KOIDE, Kazumasa HIRAMATSU, and Nobuhiko SAWAKI), (EFFECTS OF AIN BUFFER LAYER ON CRYSTALL0GR0PHIC STRUCTURE AND ON ELECTRICAL AND OPTICAL PROPERTIES OF GaN AND Gal-XA; ^ 0.4) FILMS GROWN ON SAPPHIRE SUBSTRATE BY M0VPE) (Journal of (Crystal Growth) 1998 (Netherlands) Volume 98, p. 209-219 [Document 3] Akasaki edited [Advanced Electronic I-211Π Group Nitride Semiconductor] First Edition (shares) Peifeng Pavilion December 9, 1999 , P. 211-213 (3) Summary of the Invention However, for example, in the hexagona 1-wurtzite crystal type of -6-200414569
GaN的室溫的帶隙爲約3 . 4eV的話爲高，需配設歐姆性接觸 電極的m族氮化物半導體（AlaGabIncN:0 S a,b，c S 1， a + b + c = l )混晶層一般係帶隙高。 因此，很難得到接觸電阻（c ο n t a c t r e s i s t a n c e )十分 低的歐姆性電極。再者，在成長於藍寶石基板上的A1 aGabIncN 結晶層中，因在結晶內經由以高密度存在的差排而發生元 件動作電流的短路，故有無法形成崩潰電壓（breakdown vo 1 t age )特性優良的歐姆性電極的問題點。 本發明乃鑒於相關的習知技術的問題點所進行的創作 φ ’其課題爲提供具備接觸電阻低、不伴隨局部崩潰的歐姆 性電極的m族氮化物半導體元件。 本發明者們銳意檢討應解決上述課題的結果，發現藉 由在ΙΠ族氮化物半導體結晶層上配設低差排密度、結晶性 優良的磷化硼結晶層，接觸於該磷化硼結晶層的表面而配 置歐姆性電極以解決上述課題，到達完成本發明。 即本發明係提供： (1 )、一種ΙΠ族氮化物半導體元件，具備結晶基板、在 φ 同結晶基板上氣相成長的導電性的ΠΙ族氮化物半導體 (AlxGaYlnHx + uUgXsl，0<YS1 以及 〇<X + YSl)結晶層、 歐姆性電極，其特徵爲： 在該m族氮化物半導體結晶層與該歐姆性電極的中間 配設有導電性的磷化硼結晶層，接觸於該磷化硼結晶層具 備有歐姆性電極， (2 )、如上述（1)所述之m族氮化物半導體元件，其中在 -7 - 200414569 該m族氮化物半導體結晶層與該磷化硼結晶層的中間配設 有包含硼與磷的非晶質層， (3)、如上述（1)或（2)所述之m族氮化物半導體元件， 其中該磷化硼結晶層係由故意未添加雜質的非摻雜的導電 層構成’且呈現與該m族氮化物半導體層相同的傳導類型 (4 )、如上述（1 )至（3 )中任一項所述之瓜族氮化物半導 體元件，其中在該瓜族氮化物半導體結晶層的{ 0 . 0 . 0 . 1 }-結晶面側配設有該磷化硼結晶層，該磷化硼結晶層爲導電 φ 性的{ 1 1 1 }-結晶層， (5 )、如上述（1 )至（4 )中任一項所述之m族氮化物半導 體元件，其中在該磷化硼結晶層的內部，在磷化硼結晶層 的< 1 1 1 > -結晶方向包含有疊層缺陷，或包含有以U 1 1卜結 晶面爲雙晶面的雙晶， (6 )、如上述（1 )至（5 )中任一項所述之m族氮化物半導 體元件，其中該磷化硼結晶層的內部的貫通差排以及參差 (misf i t )差排的合計的密度爲1χ1〇4個/cm2以下。 φ (7 )、如上述（1 )至（6 )中任一項所述之ΙΠ族氮化物半導 體元件的製造方法’其中在該結晶基板上藉由有機金屬化 學的氣相沉積法使該m族氮化物半導體結晶層與該磷化硕月 結晶層形成， (8)、一種發光二極體’係由如上述（1)至（6)中任一項 所述之瓜族氮化物半導體元件構成’其特徵爲P n接合型的 雙異質（double hetero)連接構造。 一 8 一 200414569 (四）實施方式 以下參照圖說明本發明的實施形態。此外，本實施形 態係用以說明本發明的要旨，只要不特別限定就非限定本 發明者。 第1圖是顯示與本發明有關的m族氮化物半導體元件的 一實施形態的剖面圖。 如第1圖所示，本實施形態的m族氮化物半導體元件1 係在略立方體狀的基板ιοί上疊層有疊層構造體11而構成 。基板1 〇 1係使用以{〇. 〇. 〇. 1 )結晶面爲表面的藍寶石結晶 。疊層構造體1 1係依次疊層有：由η型GaN構成的下部覆 蓋（clad)層102、η型磷化硼層103、由η型Gauoln 〇.10N 構成的發光層104、由p型GaN層構成的上部覆蓋層1〇5以 及p型磷化硼層106而構成。而且，發光層104、上部覆蓋 層105以及p型磷化硼層106的各一部分被連續除去，接 觸於露出的η型磷化硼層1 03的表面的一部分而配設有η 型歐姆性電極107。而且，接觸於ρ型磷化硼層1〇6的表面 而配設有Ρ型歐姆性電極1 〇 8。 如以上，m族氮化物半導體元件1係由：下部覆蓋層10 2 、由η型磷化硼層103以及η型歐姆性電極1〇7構成的n 型下層部21、發光層104、上部覆蓋層105、由P型磷化硼 層1 0 6以及ρ型歐姆性電極1 〇 8構成的ρ型上部層2 0構成 〇 如上述的構成的瓜族氮化物半導體元件1成爲p n接合 型雙重異質（DH:Double Hetero)構造的LED。 200414569 本實施形態的m族氮化物半導體元件1特別是以與m族 氮化物半導體的晶格失配大的單結晶爲基板丨〇】，適合使用 於使瓜族氮化物半導體結晶層的下部覆蓋層1 02成長的情 形。因此，使ΙΠ族氮化物半導體結晶層成膜用的基板對於 利用習知的砷化鎵（GaAs)、磷化鎵（Gap)、立方晶或六方晶 的碳化矽（S i C )、藍寶石（a - A 1 203單結晶）等的氧化物單結 晶以及矽（S i )單結晶（矽）等的情形特別有效。因對於成長 瓜族氮化物半導體結晶層較佳的溫度一般爲高溫，故耐熱 性優良的S i C、a - A 1 20 3、S i結晶等當作基板較佳。 而且，基板1 0 1例如使用以{ 1 〇 〇 }-或{ 1 1 〇卜結晶面爲 表面的立方晶閃鋅礦結晶型的單結晶較佳。若使用這種基 板1 0 1則可使以表面的面方位爲{ 〇 · 〇 . 〇 . 1 }或{ 1 · 1 . _ 2 . 0 }的 瓜族氮化物半導體結晶層沉積於基板上。以{ 〇 . 〇 . 〇 .丨丨或 { 1 · 1 . - 2 · 0 }結晶面爲表面的m族氮化物半導體層可適合使 用於用以沉積後述的磷化硼層。 而且’ II族氮化物半導體元件1的特徵係分別使磷化硼 層103、106接觸於p型的I[族氮化物半導體層1〇2、ι〇5 的雙方而配設。磷化硼層1 〇 3 ' 1 〇 6係當作配設接觸電阻特 低的歐姆性電極1 0 7、1 0 8用的導電層而發揮功能。爲了形 成接觸電阻低的η型或p型的歐姆性電極，配設電極的半 導體層以載子（carrier)濃度爲lxl〇18cm·3，更佳爲 1 x 1 0 c m 3以上的低電阻結晶層，以及避免來自基板或瓜族 風化物層的差排的傳播（p r 〇 p a g a t i ο η )，低的差排密度的結 晶層較佳。幾乎無像磷化硼（BP )或砷化硼（BA s )等的離子結 200414569 合性’若使用共有結晶性的半導體結晶的話，可形成載子 濃度高的η型以及p型的低電阻的導電層。而且，在這些 化合物半導體結晶中即使爲故意不添加雜質的非摻雜 (undope )狀態也能形成這種高載子濃度的半導體層。 特別是如本實施形態的DI族氮化物半導體元件1，配設 位於將來自發光層1 0 4的發光取出到外部的方向（在第1圖 所舉例說明的瓜族氮化物半導體元件1，由發光層1 04朝上 部覆蓋層1 0 5的方向）的歐姆性電極1 〇 8的結晶層1 0 6爲不 吸收發光可充分地透射到外部的禁止帶大的結晶層，即由 磷化硼結晶層構成者最佳。再者，在LED中爲了得到作爲 朝外部的發光透射層的作用，帶隙更大的磷化硼爲適合的 構成材料。 上述的m族氮化物半導體元件1可如以下而製造。首先 在基板1 〇 1的表面上例如藉由有機金屬化學的氣相沉積法 (M0CVD)手段沉積氮化鎵（GaN)等的皿族氮化物半導體層， 作爲下部覆蓋層1 〇 2。對於在基板表面上用以使ΠΙ族氮化物 半導體層成長的其他手段，可舉鹵素（halogen)法、氫化物 (hydride)法或分子線嘉晶（ePitaxial)(MBE)手段。然後依 次以相同的成長手段形成η型磷化硼層103、由η型GaQ.9()In 〇 ι〇Ν構成的發光層1〇4、由p型GaN層構成的上部覆蓋層105 以及P型磷化硼層1 06 °若以相同的成長手段形成各層 1 0 2〜1 0 6則可省力地、簡便地形成疊層構造體。完成疊層構 造體1 1的形成後，連續除去其一部分的發光層1 0 4、上部 覆蓋層105以及P型磷化硼層106的各一部分’使n型磷 200414569 化硼層1 0 3的表面露出。然後，在露出的n型磷化硼層1〇3 的一部分區域上配設η型歐姆性電極1 0 7，接觸於上部覆蓋 層10 5上的ρ型磷化硼層1 〇 6的表面，配置ρ型歐姆性電 極108，製造ρη接合型雙重異質（DH)構造的LED之ΠΙ族氮 化物半導體元件1。 磷化硼層103以及106可藉由上述的氣相成長手段形 成。例如可以三乙基硼（分子式：（C2H5)3B) /磷化氫 (phosphine)(分子式：PH3)爲原料，藉由常壓（略大氣壓）或 減壓MOCVD手段形成。具體上，如果依照常壓MOCVD手段 ，令基板溫度爲約1 0 0 0 °C〜1 2 0 0 °C的溫度，且令供給到成長 反應系的原料的濃度比率（PH3/(C2H5)3B)即所謂的v/IΠ比率 爲例如約1 0 0 0的話，可形成非摻雜ρ型的磷化硼層。若令 基板溫度爲7 5 0 °C〜約1 0 0 0 °C的話，對於得到非摻雜n型的 磷化硼層較佳。與傳導類型無關，形成於GaN等的Π族氮 化物半導體層上的磷化硼層具有防止傳播到內在於GaN等 的Μ族氮化物半導體層的參差差排（misfi t dislQcatiQr〇 或貫通差排的上層之效果。 內在於上述的ΙΠ族氮化物半導體層的參差差排例如可藉 由包含基板101、下部覆蓋層102以及磷化硼層1〇3的部分 的剖面TEM (透射電子顯微鏡）像而觀察。起因於與藍寶石基 板101的晶格失配，在構成基板101與下部覆蓋層102的GaN 層的接合界面101a發生多量的參差差排。伴隨著GaN層的 層厚的增加，每一參差差排的單位面積的數目即所謂的差 排密度減少的在與磷化硼層103的接合界面1〇23的正下方 200414569 的區域依然爲約1 x 1 05個/ cm2的高密度。但是，差排的延 伸被在與磷化硼層1 〇 3的接合界面1 0 2 a阻止。因此，朝磷 化硼層103的內部看不到差排的侵入/傳播。即異質（異種） 接合在ΠΙ族氮化物半導體層的磷化硼層發揮阻止來自m族氮 化物半導體層的差排的傳播的能力。 一般，在爲了不使崩潰電壓不良顯著地發生起見，令 差排密度爲1 X 1 〇4個/ cm2較佳，惟如果依照本實施形態的ΙΠ 族氮化物半導體元件1，如上述可形成差排密度爲1 X 1 04個 /cm2以下的低差排密度的磷化硼層。 而且，在下部覆蓋層102及/或上部覆蓋層1〇5使用的 例如接觸於像GaN的Π族氮化物半導體結晶層的{ 〇 . 〇 . 〇 . 1 }-結晶面’以{ 1 1 1卜磷化硼結晶層當作磷化硼結晶層1 〇 3及/ 或106配設較佳。 適合於磷化硼結晶層成長的閃鋅礦結晶單體量的磷化 硼的晶格常數爲0 · 4 5 8nm。其{ 1 10}-晶格面的間隔與纖鋅礦 結晶型GaN的a軸晶格常數（0.319nm)大致一致。而且，磷 化硼結晶的{ 1 1 1 }-晶格面的間隔與纖鋅礦結晶型GaN的c 軸晶格常數（0 · 5 2 9 n m )的半値大致一致。因此，形成於g a N 的{ 0 . 0 · 0 · 1 }-結晶表面上的{ 111 }-磷化硼結晶層特別是成 爲起因於晶格的失配的參差差排少的良質的結晶層。 再者’彳/口者< 1 1 1〉- f'n晶方位包含疊層缺陷（s t a c ^ i n g f au 1 t )的磷化硼層特別是可當作參差差排少的良質的磷化 硼結晶層而利用。而且，也能適合使用於包含以{ i 1丨）_結 晶面爲雙晶面的{ 1 1 1 }-雙晶之磷化硼層。因疊層缺陷 -13- 200414569 (s t a c k 1 n g f a u 1 t )或雙晶具有吸收參差差排的作用，故在 磷化硼層的內部差排幾乎不發生，可形成不引起局部崩潰 的歐姆性電極。包含疊層缺陷或雙晶的磷化硼層在7 50 t 〜1 2 0 0 °C的基板溫度範圍，設定使其成長的速度（成長速度） 爲每分10nm以上較佳。 此外，雖然未配設於本實施形態，惟在瓜族氮化物半導 體結晶層與磷化硼結晶層的中間可配設包含硼與磷的非晶 質層。藉由配設包含硼與磷的非晶質層，可得到具有連續 性的磷化硼層。乃因構成非晶質層的硼或磷在形成磷化硼 φ 結晶層時成爲提供[成長核]，可對磷化硼結晶層的圓滑的 成長促進貢獻。此時，非晶質層的層厚爲2〜50 nm較佳。若 層厚超過50nm則單結晶的磷化硼結晶層的形成被阻礙不佳 。而且，在未滿2nm的層厚中，不到達均等地被覆m族氮 化物半導體層的表面的全面，即因在瓜族氮化物半導體層 的表面無法均勻地形成[成長核]，無法安定得到具有連續 性的平坦表面的磷化硼層，故不佳。包含硼與磷的非晶質 層例如可藉由MOCVD手段在溫度2 5 0°C〜1 200X：的範圍中，鲁 令V / m比率爲2〜5 0的低比率而得到。是否爲非晶質層係可 藉由X線或電子線繞射法等方式調查。而且，其層厚例如 可藉由剖面TEM技法等正確地實測。 設置歐姆性電極而配設的磷化硼層的傳導類型係令與 接合於磷化硼層的]Π族氮化物半導體層的傳導類型相同。 例如接觸於接合於η型瓜族氮化物半導體層而配設的n型 磷化硼層而配設η型歐姆性電極。 一 1 4一 200414569 其次顯示第二實施形態。在本實施形態中成爲上層部20 爲像第2圖所示的構成。具體上，接合於配設於η型Π族 氮化物半導體層1 1 2上的p型磷化硼層111，且接觸於也接 合於η型ΠΙ族氮化物半導體層1 1 2而配設的η型磷化硼層Π 〇 ，配設有π型歐姆性電極1 0 7。 在此構成中，依照Ρ型磷化硼層1 1 1與η型磷化硼層1 1 〇 的ρη接合，可得到由η型歐姆性電極1 0 7朝正下方的η型 m族氮化物半導體層1 1 2的元件動作電流的短路的流通被 阻止，遍及η型ΙΠ族氮化物半導體層112的廣範圍，可平 鲁 面地擴散動作電流的優點。具備由與這種p型以及η型磷 化硼層的接合構成構成的電流狹窄構造的歐姆性電極1 07 可優勢地利用於構成ΠΙ族氮化物半導體LD。對於發揮低接 觸電阻的歐姆性電極或電流狹窄作用，磷化硼層的層厚爲 50nm以上較佳。而且，以5 00nm以下較佳。 而且，磷化硼層1 1 1、磷化硼層1 1 〇、歐姆性電極1 0 7 以及ΠΙ族氮化物半導體層1 1 2的傳導類型與本實施形態相 反也可以。 φ [實施例] 以下說明本發明的實施例，惟本發明的範圍並非限定 於這些實施例。 (第一實施例） 在本貫施例中製造具備氮化鎵（(3 a N )層與憐化硼層的異 質接合的LED。第3圖是顯示本實施例的LED2的剖面模式 圖。在第3圖中針對與第1圖或第2圖所記載者相同的構 - 1 5 - 200414569 成女：素，附加同一^符號來揭不。 基板1 0 1係使用以（0 . 0 . 0 . 1 )-結晶面爲表面的藍寶石 單結晶，在（〇·〇.〇·!)表面上藉由三甲基鎵 (NH〇原料系常壓M0CVD手段，沉積^型 GaN層的下部覆蓋 層1〇2。據此，得到以{〇 . 〇 . 〇 . 1 }-結晶面爲表面的氮化鎵（GaN) 層。下部覆蓋層102的層厚爲2.8><l(r4cm(=2.8//m)，載子 ί辰度爲 2xl〇18cm·3。 在下部覆蓋層1 02上沉積包含硼與磷的非摻雜的非晶 質層109。非晶質層109係使用（C2H5)3B/PH3/H2系常壓MOCVD 手段，以1 0 2 5 °C沉積。層厚以12nm。在非晶質層109上使 用（C2H5)3B/PH3/H2系常壓MOCVD手段，以l〇25°C沉積磷化 硼結晶層1 0 3。磷化硼層1 0 3係非摻雜、令載子濃度爲 2xl019cnr3的n型層，令其層厚爲I50nm。 在憐化砸，層 103上藉由（CH3)3Ga/二甲基姻（分子式 :(CH3)3In/NH3/H2 系常壓 MOC VD 手段，以 8 5 0 °C 使由 Ga〇.9()In〇.i〇N構成的發光層104熱相成長。令其層厚爲50nm ，令載子濃度爲約3xl018cm_3。在發光層104上以上述的 (CH3)3Ga/NH3/H2常壓MOCVD手段使由p型GaN構成的上部 覆蓋層105氣相成長。令上部覆蓋層105的層厚爲150nm。 構成上部覆蓋層105的GaN層的載子濃度爲約6xl 017cnr3。 完成上部覆蓋層1 0 5的成長後，藉由剖面TEM技法調 查：構成疊層體的下部覆蓋層102、非晶質層109、磷化硼 層1 03以及發光層1 04的內部的結晶學的構造。由制限視 野電子線繞射技法，配設於基板1 0 1的（0 . 0 . 0 . 1 )·藍寶石 200414569 結晶面上的下部覆蓋層102( GaN層）爲{0 . 0 · 0 · 1卜結晶層， 而且，下部覆蓋層102(GaN層）上的磷化硼層1〇3爲{111卜 結晶層。而且，在高分解能明視野對比像中顯示在與藍寶 石基板1 0 1的接合界面1 〇 1 a的附近的下部覆蓋層1 〇 2存在 約5M011個/ cm2的多量的參差差排。在與下部覆蓋層1〇2 的非晶質層109的接合界面102a的附近的區域，差排密度 減少到約5χ1 09個/ cm2。而且，來自下部覆蓋層102的差排 在與非晶質層109的接合界面102a，阻止非晶質層1〇9以 及磷化硼層1 0 3的侵入到內部。因此，在磷化硼層1 0 3幾 乎看不到參差差排。另一方面，在磷化硼層103的內部存 在沿著{ 1 1 1 )-結晶方位的疊層缺陷或雙晶。這些疊層缺陷 或雙晶係由與下部覆蓋層102的接合界面102a發生。因藉 由這些疊層缺陷或雙晶使差排被吸收，故判斷在磷化硼層 103的內部差排幾乎消失。 而且，磷化硼層1 0 3的疊層缺陷或雙晶係一部分侵入 上層的Gao.9oIno.ioN發光層104的內部。但是，由在{111}-磷化硼層1 0 3的表面交叉的{ 1 1 0 }-結晶面的晶格面間隔與 構成發光層104的Gao.^InmN的a軸晶格常數的整合性 的良好度，在發光層1 0 4的內部幾乎看不到差排的存在。 其次，利用選擇圖案形成（p a t t e r n i n g )技術以及電漿 蝕刻（p 1 a s m a e t c h i n g )技術削除構成上部覆蓋層1 Ο 5的G a N 層與發光層1 0 4的一部分的區域。據此，使η型磷化硼層1 〇 3 的表面露出。其次，在露出的η型磷化硼層1 0 3的表面配 置由金/鍺合金（Au95重量％/Ge5重量％)構成的η型歐姆性 200414569 電極107。An/Ge歐姆性電極107的接觸電阻降低到約6χ1 0·6 Ω / cm2。順便一提，直接接觸同樣的載子濃度的η型GaN層 而配設的Au/Ge歐姆性電極的接觸電阻爲大約l(T3Q/cm2 左右。另一方面，在保留的上部覆蓋層105的表面配設氧 化鎳（N i 0 ) /金（A U )疊層構造的p型歐姆性電極1 0 8，構成ρ η 接合型DH構造的LED2。 確認了在η型以及ρ型的歐姆性電極1 0 7、1 0 8之間於 順方向流通 2 0毫安培（m A )的動作電流，一邊裁斷成約 3 · 5 X 1 0·2 c m的正方形的LED晶片2的發光特性。以下整理 所得到的發光特性。 (1 )發光色：青紫 (2) 發光中心波長：約4 3 0 (nm) (3 )亮度（晶片狀態）：約7 ( m c d ) (4 )順方向電壓：約3 . 8 ( V )(但是，令順方向電流爲20mA 的情形） (5)逆方向電壓：12V(但是，令逆方向電流爲ΐ〇μΑ的 情形） 而且，因使η型歐姆性電極1 〇 7接觸於低的差排密度 的磷化硼層1 03而配設，故朝下部的GaN層的短路的動作 電流的流通被避免，可廣範圍地擴散動作電流到下部覆蓋 層102。因此，在LED2中也確認了自發光層104的略全面 帶來發光係來自近視野發光像。 (第二實施例） 在本實施例中配置η型以及ρ型的歐姆性電極的雙方 -18- 200414569 於磷化硼層上，製造led。 第4圖是顯示本實施例的LED3的剖面模式圖。針對與 在第1圖至第3圖中任一圖所記載的構成要素相同的構成 要素，附加同一符號來揭示。 在與第一實施例的記載相同的條件下，在{ 〇 . 〇 . 〇 . 1 }-藍寶石基板1 〇 1上依次沉積在第一實施例記載的各層 102〜105。然後在p型上部覆蓋層1〇5上沉積非摻雜η型的 磷化硼層110。η型磷化硼層110係使用（C2H5)3B/PH3/H2系 常壓MOCVD手段，以8 5 0 °C沉積。令載子濃度爲lxl019cm-3 ，令其層厚爲120 ηπι。在完成η型磷化硼層110的成長後， 限於形成Ρ型歐姆性電極1 0 8的預定的正下方的區域，使η 型磷化硼層1 1 0殘存成圓形。殘存的η型磷化硼層1 1 0的 平面積係以對圓型的ρ型歐姆性電極1 0 8的底面積1 . 2倍 。形成Ρ型歐姆性電極1 08的預定的區域外的η型磷化硼 層1 1 0係藉由電漿鈾刻手段除去，使下層的ρ型上部覆蓋 層105的表面露出。 然後，用以被覆殘存的η型磷化硼層1 1 0以及露出的ρ 型上部覆蓋層1 0 5的表面而沉積非摻雜的ρ型磷化硼層1 1 1 。Ρ型磷化硼層111也藉由與上述相同的MOCVD手段，以1025 °(：使其成長。令ρ型磷化硼層1 1 1的載子濃度爲2xl019cnr3 ，令層厚爲200nm。 其次，限於形成η型歐姆性電極1 0 8的預定的區域’ 藉由選擇圖案形成技術以及電漿蝕刻技術除去Ρ型磷化硼 層111、上部覆蓋層105以及發光層104。除去後，在露出 -19- 200414569 的η型磷化硼層1 〇 3的表面配設Α ιι / G e合金的η型歐姆性 電極1 0 7。而且，在保留的η型磷化硼層Π 0的上方配設接 觸於？型_化硼層111的表面，由金/鈹合金（八1199重量％/；661 重量％)構成的直徑爲1.3xl(T2cm( = 130//m)的圓形的ρ型歐 姆性電極1 0 8。圓形的p型歐姆性電極1 〇 8係與殘存的n型 磷化硼層1 1 0的中心一致而配設。據此，構成ρη接合型DH 構造的LED3。ρ型歐姆性電極1〇8的接觸電阻爲5Μ0·6Ω / cm2 ο 如果依照利用電子線繞射法以及剖面ΤΕΜ技法的觀察 ，在接合於構成上部覆蓋層105的ρ型GaN層的表面而配 設的η型磷化硼層1 1 〇、接合於n型磷化硼層1 1 〇的ρ型磷 化硼層1 1 1的內部幾乎看不到參差差排，差排密度明顯地 在1 X 104個/ cm2以下。另一方面，在平行於磷化硼的 <丨丨1:>_ 結晶方向存在疊層缺陷或雙晶。因此，η型以及ρ型歐姆性 電極107、108成爲形成參差差排極低的磷化硼層1〇3、111 〇 確認了在η型以及ρ型的歐姆性電極1 〇 7、1 0 8之間於 順方向流通 2 0毫安培（m A)的動作電流，令一邊爲約 4 · 〇x l(T2cm的正方形的LED晶片3的發光特性。以下整理 所得到的發光特性。 U )發光色：青紫 (2)發光中心波長：約440 (nm) (3 )売度（晶片狀態）：約9 ( m c d )The band gap of GaN at room temperature is about 3.4 eV, which is high, and an m-type nitride semiconductor (AlaGabIncN: 0 S a, b, c S 1, a + b + c = l) needs to be provided with an ohmic contact electrode. The mixed crystal layer generally has a high band gap. Therefore, it is difficult to obtain an ohmic electrode having a very low contact resistance (c n t a c t r e s i s t a n c e). In addition, in the A1 aGabIncN crystal layer grown on a sapphire substrate, a short-circuit of an element operating current occurs in a crystal through a differential row having a high density, and therefore, a breakdown voltage (breakdown vo 1 t age) characteristic cannot be formed. Problems with excellent ohmic electrodes. The present invention has been made in view of the problems of the related art, and its object is to provide an m-type nitride semiconductor device having an ohmic electrode with low contact resistance and no local breakdown. The present inventors earnestly reviewed the results that should solve the above problems, and found that by disposing a boron phosphide crystal layer with low differential density and excellent crystallinity on the group III nitride semiconductor crystal layer, the boron phosphide crystal layer was contacted. An ohmic electrode is disposed on the surface to solve the above-mentioned problems, and the present invention has been completed. That is, the present invention provides: (1) a group III nitride semiconductor device including a crystalline substrate, and a group III nitride semiconductor (AlxGaYlnHx + uUgXsl, 0 < YS1, and YS1) having a crystalline substrate and a vapor phase-grown conductivity on a φ isocrystalline substrate. < X + YSl) a crystal layer and an ohmic electrode, characterized in that a conductive boron phosphide crystal layer is arranged between the m group nitride semiconductor crystal layer and the ohmic electrode, and is in contact with the phosphating The boron crystal layer is provided with an ohmic electrode. (2) The m-nitride semiconductor element according to the above (1), wherein the m-nitride semiconductor crystal layer and the boron phosphide crystal layer are between −7 and 200414569. An amorphous layer containing boron and phosphorus is disposed in the middle. (3) The m-type nitride semiconductor device described in (1) or (2) above, wherein the boron phosphide crystal layer is formed by intentionally adding no impurities. Is composed of a non-doped conductive layer, and exhibits the same conductivity type (4) as that of the m-group nitride semiconductor layer, as described in any one of the above (1) to (3), a melon nitride semiconductor device, Wherein {0. 0. 0.1}-The boron phosphide crystal layer is arranged on the crystal plane side, and the boron phosphide crystal layer is a {1 1 1} -crystal layer with electrical conductivity φ, (5), as described in (1) to (4) above. The m-nitride semiconductor device according to any one of the above), wherein within the boron phosphide crystal layer, the < 1 1 1 > in the boron phosphide crystal layer contains a lamination defect, or (6) The group m nitride semiconductor device according to any one of (1) to (5) above, wherein the boron phosphide crystals The total density of the through-difference rows and the misf it rows in the layer is 1 × 104 pieces / cm 2 or less. φ (7), the method for manufacturing a group III nitride semiconductor device according to any one of (1) to (6) above, wherein the m is formed on the crystalline substrate by a vapor deposition method of organometallic chemistry A group nitride semiconductor crystal layer and the phosphide crystal layer are formed. (8) A light-emitting diode is composed of the group nitride semiconductor device described in any one of (1) to (6) The structure is characterized by a double hetero connection structure of a P n junction type. 1 8 1 200414569 (4) Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this embodiment mode is used to explain the gist of the present invention, and the present inventor is not limited as long as it is not particularly limited. Fig. 1 is a sectional view showing an embodiment of a group m nitride semiconductor device according to the present invention. As shown in FIG. 1, the m-type nitride semiconductor element 1 of this embodiment is configured by laminating a laminated structure 11 on a substantially cubic substrate. The substrate 101 is made of sapphire crystal having a crystal surface of {〇. 〇. 〇. 1) as a surface. The multilayer structure 1 1 is laminated in this order: a lower clad layer 102 made of n-type GaN, an n-type boron phosphide layer 103, a light-emitting layer 104 made of n-type Gauoln 0.10N, and a p-type An upper cladding layer 105 composed of a GaN layer and a p-type boron phosphide layer 106 are formed. In addition, each part of the light emitting layer 104, the upper cover layer 105, and the p-type boron phosphide layer 106 is continuously removed, and an n-type ohmic electrode is disposed in contact with a part of the surface of the exposed n-type boron phosphide layer 103. 107. Further, a P-type ohmic electrode 108 is disposed in contact with the surface of the p-type boron phosphide layer 106. As described above, the m-type nitride semiconductor device 1 is composed of the lower cover layer 10 2, the n-type lower layer portion 21 composed of the n-type boron phosphide layer 103 and the n-type ohmic electrode 107, the light-emitting layer 104, and the upper layer. The layer 105, the p-type upper layer 20 composed of the p-type boron phosphide layer 106 and the p-type ohmic electrode 10 are configured. The melon nitride semiconductor device 1 configured as described above becomes a pn-junction dual heterogeneity. (DH: Double Hetero) LED. 200414569 The m-group nitride semiconductor element 1 of this embodiment is based on a single crystal having a large lattice mismatch with the m-group nitride semiconductor, and is suitable for covering the lower part of the crystalline layer of a melon-nitride semiconductor. Tier 1 02 growth situation. Therefore, the substrate for forming a group III nitride semiconductor crystal layer is made of conventional gallium arsenide (GaAs), gallium phosphide (Gap), cubic or hexagonal silicon carbide (S i C), sapphire ( a-A 1 203 single crystal) is particularly effective in the case of oxide single crystals and silicon (S i) single crystals (silicon). Since the preferred temperature for growing the crystalline layer of the melons nitride semiconductor is generally high temperature, S i C, a-A 1 20, S i crystals, etc., which are excellent in heat resistance, are preferred as the substrate. Further, as the substrate 101, for example, it is preferable to use a cubic single crystal of the sphalerite crystal type having a {100}-or {1 100 crystalline surface as a surface. If such a substrate 101 is used, a guar nitride semiconductor crystal layer having a surface orientation of {〇 · 〇. 〇. 1} or {1 · 1.. _ 2. 0} can be deposited on the substrate. The m-group nitride semiconductor layer having a {〇. 〇 .〇. 丨 丨 or {1 · 1..-2 · 0} crystal surface as a surface can be suitably used for depositing a boron phosphide layer described later. In addition, the characteristic of the 'II-nitride semiconductor element 1 is that the boron phosphide layers 103 and 106 are arranged in contact with both of the p-type I [group nitride semiconductor layer 102 and ι05]. The boron phosphide layer 10 3 '106 is used as a conductive layer provided with ohmic electrodes 107 and 108 having extremely low contact resistance. In order to form an n-type or p-type ohmic electrode with low contact resistance, the semiconductor layer provided with the electrode has a low-resistance crystal with a carrier concentration of 1 × 1018 cm · 3, more preferably 1 × 10 cm 3 or more. Layer, and to avoid the propagation of differential rows (pr opagati ο η) from the substrate or the melon weathering layer, a crystalline layer with a low differential row density is preferred. Almost no ionic junctions like boron phosphide (BP) or boron arsenide (BA s) 200414569 Synthesize 'If semiconductor crystals with common crystallinity are used, η-type and p-type low resistance with high carrier concentration can be formed Conductive layer. Moreover, such a semiconductor layer with a high carrier concentration can be formed in these compound semiconductor crystals even in an undoped state where no impurities are intentionally added. In particular, the DI group nitride semiconductor device 1 according to the present embodiment is disposed in a direction for taking out light emitted from the light emitting layer 104 to the outside (the guar nitride semiconductor device 1 illustrated in FIG. 1 is formed by The luminescent layer 1 04 is in the direction of the upper cladding layer 105). The crystalline layer 10 of 10 is an crystalline layer 106 that does not absorb light and can fully transmit to the outside. It is a crystalline layer with a large forbidden band, that is, boron phosphide. The crystal layer is the best. Furthermore, in order to obtain the function as an external light-emitting transmission layer in an LED, boron phosphide having a larger band gap is a suitable constituent material. The m-type nitride semiconductor device 1 described above can be manufactured as follows. First, a substrate nitride semiconductor layer such as gallium nitride (GaN) is deposited on the surface of the substrate 101 by, for example, an organometallic chemical vapor deposition (MOCVD) method, as the lower cover layer 102. As other methods for growing the group III nitride semiconductor layer on the substrate surface, a halogen method, a hydride method, or a molecular wire Jiaejing (MBE) method can be mentioned. Then, an n-type boron phosphide layer 103, a light-emitting layer 104 composed of n-type GaQ.9 () In OM, an upper cover layer 105 composed of a p-type GaN layer, and P If the boron phosphide layer 1 06 ° is formed by the same growth means of each layer 102 to 106, a multilayer structure can be formed with ease and effort. After the formation of the laminated structure 11 is completed, a part of the light emitting layer 104, the upper cladding layer 105, and the P-type boron phosphide layer 106 are successively removed. The surface is exposed. Then, an n-type ohmic electrode 1 107 is arranged on a part of the exposed n-type boron phosphide layer 103, and contacts the surface of the p-type boron phosphide layer 106 on the upper cover layer 105. The p-type ohmic electrode 108 is arranged to manufacture a group III nitride semiconductor element 1 of a LED with a p-n junction double heterostructure (DH) structure. The boron phosphide layers 103 and 106 can be formed by the above-mentioned vapor phase growth means. For example, triethylboron (molecular formula: (C2H5) 3B) / phosphine (molecular formula: PH3) can be used as a raw material, and formed by atmospheric pressure (slightly atmospheric pressure) or reduced pressure MOCVD. Specifically, if the atmospheric temperature MOCVD method is used, the substrate temperature is set to a temperature of about 100 ° C to 12 0 ° C, and the concentration ratio of the raw materials supplied to the growth reaction system (PH3 / (C2H5) 3B ), That is, a so-called v / IΠ ratio of about 100, for example, can form an undoped p-type boron phosphide layer. If the substrate temperature is set to 750 ° C to 100 ° C, it is preferable to obtain an undoped n-type boron phosphide layer. Irrespective of the conductivity type, the boron phosphide layer formed on a group III nitride semiconductor layer such as GaN has a misfi t dislQcatiQr0 or a through differential row that prevents propagation to a group M nitride semiconductor layer that contains GaN or the like. The unevenness of the above-mentioned group III nitride semiconductor layer is, for example, a cross-section TEM (transmission electron microscope) image of a portion including the substrate 101, the lower cover layer 102, and the boron phosphide layer 103. Observation. Due to the lattice mismatch with the sapphire substrate 101, a large number of uneven rows occur at the bonding interface 101a of the GaN layer constituting the substrate 101 and the lower cladding layer 102. With the increase of the layer thickness of the GaN layer, each The area of the number of staggered rows per unit area, which is the so-called reduced row density, which is directly below the junction interface 1023 with the boron phosphide layer 103, 200414569, still has a high density of about 1 x 105 cells / cm2. The extension of the differential row is prevented by the bonding interface 10 2 a with the boron phosphide layer 103. Therefore, no invasion / propagation of the differential row can be seen toward the inside of the boron phosphide layer 103. That is, heterogeneous (heterogeneous) bonding In ΠΙ The boron phosphide layer of the nitride semiconductor layer exhibits the ability to prevent the propagation of the differential rows from the m-type nitride semiconductor layer. Generally, the differential row density is set to 1 × 1 so as not to cause the breakdown voltage failure to occur significantly. 4 / cm2 is preferred, but if the group III nitride semiconductor device 1 according to this embodiment is used, a boron phosphide layer with a low differential density of 1 × 104 / cm2 or less can be formed as described above. For the lower cladding layer 102 and / or the upper cladding layer 105, for example, {〇. 〇. 〇. 1} -crystal plane of contact with a group III nitride semiconductor crystal layer like GaN is represented by {1 1 1 卜The boron phosphide crystal layer is preferably disposed as the boron phosphide crystal layer 103 and / or 106. The lattice constant of the amount of boron phosphide of the sphalerite crystal unit suitable for the growth of the boron phosphide crystal layer is 0. · 4 5 8nm. The interval of the {1 10} -lattice plane is approximately the same as the a-axis lattice constant (0.319nm) of wurtzite crystalline GaN. Moreover, the {1 1 1} -crystal of boron phosphide crystals The interval between the lattice planes is approximately the same as the half unitary of the c-axis lattice constant (0 · 5 2 9 nm) of wurtzite crystalline GaN. The {0. 0 · 0 · 1} -boron phosphide crystal layer on ga N is particularly a good crystal layer with little uneven row due to lattice mismatch. Furthermore, '彳 / 口 者 < 1 1 1〉-boron phosphide layer with f'n crystal orientation containing lamination defects (stac ^ ingf au 1 t), especially as a good boron phosphide crystal layer with few staggered rows While using. Furthermore, it can also be suitably used for a boron phosphide layer containing {1 1 1} -twin-crystal having a {i 1 丨) _ crystalline plane as a bi-crystalline plane. Due to the stacking defect -13- 200414569 (stack 1 ngfau 1 t) or the double crystal has the function of absorbing staggered differential rows, the internal differential rows hardly occur in the boron phosphide layer, and an ohmic electrode can be formed without causing local collapse. . It is preferable to set the growth rate (growth rate) of the boron phosphide layer containing lamination defects or twin crystals at a substrate temperature range of 7 50 t to 12 0 ° C (growth rate) to 10 nm or more per minute. In addition, although not provided in this embodiment, an amorphous layer containing boron and phosphorus may be disposed between the crystalline layer of the melons nitride semiconductor and the crystal layer of boron phosphide. By providing an amorphous layer containing boron and phosphorus, a continuous boron phosphide layer can be obtained. It is because boron or phosphorus constituting the amorphous layer becomes a [growth core] when forming a boron phosphide φ crystal layer, and can contribute to the smooth growth promotion of the boron phosphide crystal layer. In this case, the thickness of the amorphous layer is preferably 2 to 50 nm. If the layer thickness exceeds 50 nm, the formation of a single-crystal boron phosphide crystal layer is hindered poorly. In addition, in a layer thickness of less than 2 nm, the entire surface of the m-group nitride semiconductor layer is not uniformly covered, that is, [growth nuclei] cannot be formed uniformly on the surface of the melon-nitride semiconductor layer, which cannot be obtained in a stable manner. A boron phosphide layer with a continuous flat surface is not good. An amorphous layer containing boron and phosphorus can be obtained, for example, by a MOCVD method at a low V / m ratio of 2 to 50 in a temperature range of 250 to 1200X :. Whether it is an amorphous layer can be investigated by X-ray or electron diffraction methods. The layer thickness can be accurately measured by, for example, a cross-section TEM technique. The conductivity type of the boron phosphide layer provided with the ohmic electrode is the same as that of the group III nitride semiconductor layer bonded to the boron phosphide layer. For example, an n-type ohmic electrode is disposed in contact with an n-type boron phosphide layer provided to be bonded to the n-type melon nitride semiconductor layer. 1 1 4 1 200414569 The second embodiment is shown next. In the present embodiment, the upper layer portion 20 has a structure as shown in FIG. 2. Specifically, the p-type boron phosphide layer 111 disposed on the n-type III nitride semiconductor layer 1 1 2 is bonded to the p-type boron phosphide layer 111 disposed on the n-type III nitride semiconductor layer 1 1 2. The n-type boron phosphide layer Π 0 is provided with a π-type ohmic electrode 107. In this configuration, in accordance with the ρη bonding of the p-type boron phosphide layer 1 1 1 and the n-type boron phosphide layer 1 1 0, an n-type m group nitride directly facing the n-type ohmic electrode 107 can be obtained. The short-circuiting of the element operating current of the semiconductor layer 1 12 is prevented, and the operating current can be diffused smoothly over a wide range of the n-type III semiconductor semiconductor layer 112. The ohmic electrode 107 having a current narrow structure formed by bonding to such p-type and n-type boron phosphide layers can be advantageously used to form a group III nitride semiconductor LD. For an ohmic electrode exhibiting a low contact resistance or a current narrowing effect, the thickness of the boron phosphide layer is preferably 50 nm or more. Furthermore, it is preferably at most 500 nm. The conductivity types of the boron phosphide layer 1 1 1, the boron phosphide layer 1 10, the ohmic electrode 10 7, and the group III nitride semiconductor layer 1 1 2 may be opposite to those of the present embodiment. [Examples] Examples of the present invention will be described below, but the scope of the present invention is not limited to these examples. (First Embodiment) In this embodiment, an LED having a heterojunction of a gallium nitride ((3 a N)) layer and a boron phosphor layer is manufactured. FIG. 3 is a schematic cross-sectional view showing the LED 2 of this embodiment. In Figure 3, the same structure as that described in Figure 1 or Figure 2 is used.-15-200414569 Adult woman: Prime, the same ^ symbol is added to expose it. The substrate 1 0 1 is used (0. 0. 0.1) -The sapphire crystal is a single crystal on the surface, and the lower surface of the GaN layer is deposited on the (〇 · 〇.〇 ·!) Surface by means of trimethylgallium (NH0 raw material normal pressure MOCVD method). Layer 102. Based on this, a gallium nitride (GaN) layer having a surface of {〇. 〇. 〇. 1} -crystal is obtained. The thickness of the lower cladding layer 102 is 2.8 > < l (r4cm ( = 2.8 // m), and the carrier density is 2 × 1018 cm · 3. A non-doped amorphous layer 109 containing boron and phosphorus is deposited on the lower cover layer 102. The amorphous layer 109 is used ( C2H5) 3B / PH3 / H2 atmospheric pressure MOCVD method, deposited at 10 2 5 ° C. Layer thickness is 12nm. Use (C2H5) 3B / PH3 / H2 atmospheric pressure MOCVD method on the amorphous layer 109 to Crystallized boron phosphide layer 103 at 105 ° C. Boron phosphide 1 0 3 is an undoped n-type layer with a carrier concentration of 2xl019cnr3, and its layer thickness is I50nm. On the substrate, the layer 103 is formed by (CH3) 3Ga / dimethyl marriage (Molecular formula: (CH3 ) 3In / NH3 / H2 is a atmospheric pressure MOC VD method, and the light-emitting layer 104 composed of Ga 0.9 (InIn..io) is grown thermally at 850 ° C. Let its layer thickness be 50 nm and let The carrier concentration is about 3 × 1018 cm_3. The upper cover layer 105 made of p-type GaN is vapor-phase grown on the light-emitting layer 104 by the above-mentioned (CH3) 3Ga / NH3 / H2 atmospheric pressure MOCVD method. The thickness of the upper cover layer 105 is increased. It is 150 nm. The carrier concentration of the GaN layer constituting the upper cladding layer 105 is approximately 6 × l 017cnr3. After the growth of the upper cladding layer 105 is completed, investigation is performed by a cross-section TEM technique: the lower cladding layer 102 constituting the laminated body, the amorphous The crystallographic structure inside the mass layer 109, the boron phosphide layer 103, and the light emitting layer 104. It is disposed on the substrate 101 (0. 0. 0. 1) by a limited field electron beam diffraction technique. The lower cladding layer 102 (GaN layer) on the sapphire 200414569 crystal surface is {0. 0 · 0 · 1 b crystal layer, and the boron phosphide layer 1 on the lower cladding layer 102 (GaN layer) is 1 3 is a {111 b crystal layer. In addition, a high resolution bright field contrast image shows that there is a large amount of about 5M011 pieces / cm2 of the lower cover layer 1 02 near the bonding interface 1 01 a with the sapphire substrate 1 0 1 a. The uneven row. In the area near the bonding interface 102a with the amorphous layer 109 of the lower cladding layer 102, the difference in row density was reduced to about 5 x 10 09 / cm2. Further, the difference from the lower cladding layer 102 is at the joint interface 102a with the amorphous layer 109, preventing the amorphous layer 109 and the boron phosphide layer 103 from entering into the interior. Therefore, almost no staggered rows are seen in the boron phosphide layer 103. On the other hand, in the interior of the boron phosphide layer 103, there are lamination defects or twin crystals along the {1 1 1) -crystalline orientation. These lamination defects or double crystal systems occur at the joint interface 102a with the lower cladding layer 102. Since the differential rows are absorbed by these stacked defects or twin crystals, it is judged that the internal differential rows in the boron phosphide layer 103 almost disappear. In addition, part of the laminated defect of the boron phosphide layer 103 or the twin crystal system penetrates into the upper Gao.9oIno.ioN light emitting layer 104. However, the integration of the lattice plane spacing of the {1 1 0} -crystal plane intersecting with the surface of the {111} -boron phosphide layer 103 and the a-axis lattice constant of Gao. ^ InmN constituting the light-emitting layer 104 In terms of the goodness of the properties, the existence of poor alignment is hardly seen inside the light emitting layer 104. Next, a part of the G a N layer and the light emitting layer 104 constituting the upper cladding layer 105 is removed by using a selective pattern formation (p a t t r r n i n g) technique and a plasma etching (p 1 a sm a e t c h i n g) technique. Accordingly, the surface of the n-type boron phosphide layer 103 is exposed. Next, an n-type ohmic 200414569 electrode 107 made of a gold / germanium alloy (Au95% by weight / Ge5% by weight) was disposed on the surface of the exposed n-type boron phosphide layer 103. The contact resistance of the An / Ge ohmic electrode 107 is reduced to about 6x1 0 · 6 Ω / cm2. By the way, the contact resistance of an Au / Ge ohmic electrode configured to directly contact an n-type GaN layer with the same carrier concentration is about l (T3Q / cm2. On the other hand, the On the surface, a p-type ohmic electrode 1 0 8 of a nickel oxide (N i 0) / gold (AU) laminated structure is configured to constitute a ρ η junction type DH structure LED2. The η-type and ρ-type ohmic electrodes were confirmed. An operating current of 20 milliamps (m A) flows in a forward direction between 1 0, 7 and 10, and the light emitting characteristics of the LED chip 2 which is cut into a square of about 3 · 5 X 1 · 2 · 2 cm are cut. (1) Luminous color: cyan (2) Luminous center wavelength: about 4 3 0 (nm) (3) Brightness (wafer state): about 7 (mcd) (4) forward voltage: about 3. 8 (V) (However, when the forward current is 20mA) (5) Reverse voltage: 12V (However, the reverse current is ΐ〇μΑ) In addition, the η-type ohmic electrode 1 〇7 It is arranged in contact with the boron phosphide layer 103 having a low differential discharge density, so that a short-circuit operating current flow to the lower GaN layer can be avoided, and The operating current is diffused to the lower cover layer 102 in a wide range. Therefore, it is also confirmed in LED2 that the self-luminous layer 104 slightly brings the luminescence system from the near-field luminescence image. (Second Embodiment) In this embodiment, η is configured. Both of the ohmic electrodes of the type and the p-type are manufactured on the boron phosphide layer to produce LEDs. Fig. 4 is a schematic cross-sectional view showing the LED 3 of this embodiment. Figs. The same components as those described in any figure are denoted by the same reference numerals. Under the same conditions as those described in the first embodiment, {〇. 〇. 〇. 1}-sapphire substrate 1 〇1 in order Deposited on each of the layers 102 to 105 described in the first embodiment. Then, an undoped n-type boron phosphide layer 110 is deposited on the p-type upper cladding layer 105. The n-type boron phosphide layer 110 uses (C2H5) 3B / PH3 / H2 is an atmospheric pressure MOCVD method and is deposited at 850 ° C. The carrier concentration is lxl019cm-3 and its layer thickness is 120 ηπ. After the growth of the η-type boron phosphide layer 110 is completed, it is limited to the formation A region directly below the P-type ohmic electrode 108 is a n-type boron phosphide layer 1 10 remains circular. The planar area of the remaining n-type boron phosphide layer 1 1 0 is 1.2 times the bottom area of the circular p-type ohmic electrode 108. The P-type ohmic electrode 1 is formed. The n-type boron phosphide layer 1 10 outside the predetermined area of 08 is removed by plasma uranium etching, and the surface of the lower p-type upper cladding layer 105 is exposed. Then, a non-doped p-type boron phosphide layer 1 1 1 is deposited to cover the surface of the remaining n-type boron phosphide layer 1 10 and the exposed p-type upper cladding layer 105. The P-type boron phosphide layer 111 is also grown by the same MOCVD method as described above at 1025 ° (:). Let the carrier concentration of the p-type boron phosphide layer 1 1 1 be 2 × l019cnr3 and the layer thickness be 200 nm. Next It is limited to a predetermined area where the n-type ohmic electrode 108 is formed. 'The P-type boron phosphide layer 111, the upper cover layer 105, and the light-emitting layer 104 are removed by a selective patterning technique and a plasma etching technique. -19- 200414569 The surface of the n-type boron phosphide layer 1 〇3 is provided with an η / ohm alloy n-type ohmic electrode 1 07. Furthermore, the remaining n-type boron phosphide layer Π 0 is disposed on the surface. A circular p-type having a diameter of 1.3xl (T2cm (= 130 // m)) made of a gold / beryllium alloy (eight 1199% by weight; 661% by weight) made on the surface of the? -Type boronized layer 111 is assumed. The ohmic electrode 108. The circular p-type ohmic electrode 108 is arranged in accordance with the center of the remaining n-type boron phosphide layer 1 10. According to this, an LED 3 with a ρη junction type DH structure is formed. The contact resistance of the ρ-type ohmic electrode 108 is 5M0 · 6Ω / cm2 ο if the observation using the electron diffraction method and the cross-section TEM method is observed An n-type boron phosphide layer 1 1 0 disposed on the surface of the p-type GaN layer constituting the upper cladding layer 105 and a p-type boron phosphide layer 1 1 1 bonded to the n-type boron phosphide layer 1 1 0 Almost no staggered rows can be seen inside, and the density of the rows is obviously below 1 X 104 / cm2. On the other hand, there are lamination defects in the < 丨 丨 1: > _ parallel to the boron phosphide Or double crystal. Therefore, the η-type and ρ-type ohmic electrodes 107 and 108 are formed as boron phosphide layers 103 and 111 with extremely low staggered rows. It has been confirmed that the η-type and ρ-type ohmic electrodes 107 are formed. An operating current of 20 milliamps (m A) flows in the forward direction between 10 and 108, so that one side has a light emitting characteristic of a square LED chip 3 of about 4.0 × 1 (T2 cm). The obtained light emitting characteristics are summarized below. U) Emission color: cyan (2) emission center wavelength: about 440 (nm) (3) degree (wafer state): about 9 (mcd)
(4 )順方向電壓：約3 . 6 ( V )(但是，令順方向電流爲20mA -20- 200414569 的情形） (5)逆方向電壓：15V(但是，令逆方向電流爲10//A的 情形） 因以使η型以及p型的歐姆性電極1 07、1 08的雙方接 觸於低差排密度的磷化硼層103、1 1 1而配設的構成，故LED3 也不發生局部崩潰，特別是成爲崩潰電壓特性優良者。而 且，因以在Ρ型歐姆性電極108的下方埋設由η型以及ρ 型的磷化硼層1 1 0、Π 1構成的ρη接合構造的構成，故避 免由Ρ型歐姆性電極1 0 8朝正下方的上部覆蓋層1 0 5的短 φ 路的流通，並且經由舖設於Ρ型覆蓋層1 05的略全面的ρ 型磷化硼層1 1 1，動作電流可擴散到上部覆蓋層1 〇 5的略全 面。因此，成爲由LED3的發光層104的略全面得到發光。 再者，配設Ρ型歐姆性電極1 08的磷化硼層1 1 1因在室溫 具有約3.OeV的帶隙，故不遮蔽來自發光層104的發光， 對於充分地透射到外部有效。 【發明的功效】 如以上的說明，在本發明的ΠΙ族氮化物半導體元件，φ 因在]Π族氮化物半導體結晶層與歐姆性電極的中間配設有 磷化硼結晶層，故可阻止自m族氮化物半導體結晶層傳播 的差排的侵入，或吸收差排。因此，藉由接觸於磷化硼結 晶層配設歐姆性電極，可形成局部崩潰少且接觸電阻低的 歐姆性電極，可提供崩潰電壓特性優良的m族氮化物半導 體發光元件。 (五）圖式簡單說明 - 2 1 - 200414569 第1圖是顯示本發明的ΙΠ族氮化物半導體元件的一實施 形態的剖面圖。 第2圖是顯示本發明的m族氮化物半導體元件的上層部 的第二實施形態的剖面圖。 第3圖是第一實施例所述的發光二極體的剖面模式圖 〇 第4圖是第二實施例所述的發光二極體的剖面模式圖(4) Forward voltage: about 3.6 (V) (However, let the forward current be 20mA -20-200414569) (5) Reverse voltage: 15V (However, let the reverse current be 10 // A In the case of the configuration in which both the n-type and p-type ohmic electrodes 107 and 108 are in contact with the boron phosphide layers 103 and 111 of low differential density, LED3 does not occur locally. Crashes, especially those with excellent breakdown voltage characteristics. Furthermore, since the p-type junction structure composed of n-type and p-type boron phosphide layers 1 10 and Π 1 is buried under the p-type ohmic electrode 108, the p-type ohmic electrode 108 is avoided. The flow of short φ path toward the upper cover layer 105 directly below, and via the p-type boron phosphide layer 1 1 1 laid on the P-type cover layer 105, the operating current can diffuse to the upper cover layer 1. 〇5 is slightly comprehensive. Therefore, the light emission from the light-emitting layer 104 of the LED 3 is almost completely obtained. In addition, the boron phosphide layer 1 1 1 provided with the P-type ohmic electrode 1 08 has a band gap of about 3.0 eV at room temperature, so it does not shield the light emission from the light emitting layer 104, and is effective for sufficiently transmitting to the outside. . [Effect of the Invention] As explained above, in the III-nitride semiconductor device of the present invention, since φ is provided with a boron phosphide crystal layer between the III-nitride semiconductor crystal layer and the ohmic electrode, it can be prevented. Invasion or absorption of the differential rows propagating from the crystal group of the m-group nitride semiconductor. Therefore, by disposing the ohmic electrode in contact with the boron phosphide crystal layer, an ohmic electrode with less local breakdown and low contact resistance can be formed, and an m-type nitride semiconductor light-emitting device having excellent breakdown voltage characteristics can be provided. (V) Brief Description of Drawings-2 1-200414569 Fig. 1 is a sectional view showing an embodiment of a group III nitride semiconductor device according to the present invention. Fig. 2 is a sectional view showing a second embodiment of the upper layer portion of the m-type nitride semiconductor device according to the present invention. FIG. 3 is a schematic cross-sectional view of the light-emitting diode according to the first embodiment. FIG. 4 is a schematic cross-sectional view of the light-emitting diode according to the second embodiment.
【符號說明】 1 :瓜族氮化物半導體元件 1 1 :疊層構造體 2 0 :上層部 2 1 :下層部 1 0 1 :基板 101a、102a:接合界面 1 0 2 :下部覆蓋層[Description of Symbols] 1: Melon nitride semiconductor device 1 1: Laminate structure 2 0: Upper layer portion 2 1: Lower layer portion 1 0 1: Substrate 101a, 102a: Joint interface 1 0 2: Lower cover layer
1 0 3、1 0 6、1 1 0、1 1 1 :磷化硼層 104:發光層 1 0 5 :上部覆蓋層 1 07、108 :歐姆性電極 1 0 9 :非晶質層 112: ΙΠ族氮化物半導體層 -22 -1 0 3, 1 0 6, 1 1 0, 1 1 1: Boron phosphide layer 104: Light emitting layer 1 0 5: Upper cover layer 1 07, 108: Ohmic electrode 1 0 9: Amorphous layer 112: ΙΠ Group nitride semiconductor layer-22-