JP2000174342A - Nitride semiconductor light-emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain high brightness nitride semiconductor light-emitting element by laying a clad layer in diffusion properties of element working current on a low temperature buffer layer having requirements for imparting a light- emitting part constituting layer. SOLUTION: A nitride gallium GaN buffer layer 20 is formed on the junction interface 10a on a sapphire substrate 10, and an n-type clad layer 30 is deposited thereon. The n-type clad layer 30 is formed by sequentially laminating an undoped n-type III nitride semiconductor crystal layer 30a, a doped crystal layer 30b and a high carrier concentration crystal layer 30c. A light-emitting layer 40 of polyphase structure is deposited on the n-type clad layer 30, and the light-emitting layer 40 comprises a main phase S and a plurality of dependent phases T having different indium composition ratio. Furthermore, a p-type clad layer 60 of III nitride semiconductor is deposited on the light-emitting layer 40, thus constituting a light-emitting part of double heterostructure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a light emitting region (area).
To obtain a nitride semiconductor light-emitting device that can emit short-wavelength visible light or ultraviolet light with high intensity.

[0002]

2. Description of the Related Art In a nitride semiconductor light emitting device which emits short-wavelength light in a red-orange band to an ultraviolet band, a light-emitting portion has a pn junction type double heterostructure in which a light-emitting layer is sandwiched between an n-type and a p-type cladding layer. (Double Hetero: DH) junction structure (Japanese Patent Laid-Open No. 6-2602).
No. 83). The light emitting layer is practically n-type gallium nitride.
It is composed of indium (Ga _Y In _{1 -Y} N: 0 ≦ Y ≦ 1) (see Japanese Patent Publication No. 55-3834). By adjusting the indium composition ratio (= 1-Y), a forbidden band width suitable for obtaining light emission from the near ultraviolet band from about 360 nanometers (nm) to about 560 nm to the short wavelength visible light band can be obtained. It is.

[0003] Ga _Y In _1-Y N (0 ≦ Y ≦
If the constituent requirements of 1) are omitted from the crystallographic structure, there is a conventional example in which an active layer (light emitting layer or well layer) is formed from Ga _Y In _1-Y N having a uniform and uniform indium composition. (See JP-A-9-36430). _{Conversely, Ga Y In 1-Y N} (0 multiphase structure composed of a plurality of phases (domain or phase) of different indium concentration
.Ltoreq.Y.ltoreq.1) to form a light-emitting layer is also known (see JP-A-10-56202). A polyphase structure is a main phase (mat) that occupies a large area spatially.
Rix phase) and a plurality of subordinate phases subordinately present in the main phase. Ga
_Y In _1-Y N is originally a material that easily causes phase separation,
On the contrary, there is an advantage that Ga _Y In _1-Y N having a multi-phase structure is easily formed and a film is easily formed (Appl. Phys. Le).
tt. , 70 (8) (1997), pp. 981-983).

Conventionally, the n-type and p-type cladding layers constituting the light-emitting portion of the DH structure with the light-emitting layer interposed therebetween are conventionally formed of aluminum gallium nitride (Al _X Ga _{1 -X} N: 0 ≦ X ≦ 1). (Jpn. J. Appl.
Phys. , 32 (1993), pages L8-L11). The n-type cladding layer is exclusively made of n-type gallium nitride (Ga) doped with an n-type impurity such as silicon (Si).
N). Conventionally, an n-type cladding layer is formed of Al _x Ga ₁ -xN (resistivity including silicon (Si) of 0.3 ohm-cm (Ω · cm) to 8 × 10 ⁻³ Ω · cm. 0 ≦ X ≦ 1) (see Japanese Patent No. 2623466). On the other hand, the p-type cladding layer is usually made of Al doped with magnesium (Mg).
_X Ga ₁ -XN (0 ≦ X ≦ 1) (see Japanese Patent Application Laid-Open No. 10-214999).

[0005] The DH structure light-emitting portion having the above-described structure is generally formed on a single crystal substrate which does not have a sufficiently good lattice matching relationship with the group III nitride semiconductor crystal. Generally, alumina (Al ₂ O ₃ ) single crystal (sapphire) is used as a substrate. However, taking gallium nitride (GaN) as an example, the lattice mismatch with sapphire reaches a little over 13% even in consideration of the orientation. For this reason, the lower cladding layer disposed below the light emitting layer is not directly deposited on the surface of the sapphire substrate, but rather is formed of Al _C Ga _{1 -C} N (0 ≦ C
The conventional technical means is to form a film through a buffer layer composed of ≦ 1), a so-called low-temperature buffer layer.

[0006]

The factors which affect the light emission intensity from the light emitting layer include those of the light emitting layer and other constituent layers of the light emitting portion which are strongly influenced by the amount of impurities, crystal defect density, and the like. It is well known that there is crystal quality.

In the vertical direction, when the constituent layers of the DH light emitting portion including the lower cladding layer are deposited on the low-temperature buffer layer for reducing the lattice mismatch with the substrate, the mismatch with the lattice mismatch substrate is sufficiently improved. At present, it has not been eased. That is, in the conventional technology, the propagation of misfit dislocations and crystal defects to the light emitting portion constituting layer caused by lattice mismatch at the bonding interface between the substrate such as sapphire and the low-temperature buffer layer is sufficiently avoided. Therefore, there is a problem in sufficiently improving the crystallinity of the constituent layers.

The main cause of the inconvenience of the prior art, which hinders the improvement of the crystallinity of the light emitting portion constituent layer, is that the constituent layer is formed on the low temperature buffer layer at a temperature higher than the film forming temperature. Exposure of the buffer layer to high temperatures results in loss of the low temperature buffer layer. In other words, the loss of the low-temperature buffer layer exposes the substrate surface that has a lattice mismatch.

Under such circumstances, the crystal quality of the light-emitting portion constituting layer grown on the low-temperature buffer layer, for example, the lower cladding layer, is naturally deteriorated due to propagation of crystal defects based on lattice mismatch. Become. Therefore, for example, when the device operating current is diffused over the entire surface of the light emitting layer bonded to the lower clad layer, the problem that the current does not spread over a wide range due to the presence of crystal defects and the light emitting region is not sufficiently expanded. is there.

[0010] The crystallinity of the light emitting portion constituting layer deposited on the low temperature buffer layer depends on the ability of the low temperature buffer layer to reduce lattice mismatch between the light emitting portion constituting layer and the single crystal substrate. If it is intended to obtain a high-brightness nitride semiconductor light-emitting device by means of expanding the light-emitting region, therefore, the surface layer region on the bonding surface side with the light-emitting layer has a high carrier concentration simply on the low-temperature buffer layer. It is difficult to achieve a sufficient measure only by stacking the n-type cladding layers.

An object of the present invention is to form a light emitting portion having a structure effective for diffusing an element operating current in a wide range of a light emitting layer from a group III nitride semiconductor crystal layer having excellent crystallinity, particularly It is to clarify the constituent requirements for the buffer layer.

[0012]

That is, the present invention provides a low-temperature buffer layer having a requirement to provide a light-emitting portion constituting layer having excellent crystallinity, and has excellent diffusion of an element operating current on the buffer layer. It is an object of the present invention to obtain a high-luminance nitride semiconductor light-emitting device by laying a clad layer having the above structure and expanding a light-emitting area.

According to the present invention for achieving this object, a nitride semiconductor light emitting device according to the first aspect of the present invention includes a single crystal substrate and the single crystal deposited on the single crystal substrate. A buffer layer comprising a group III nitride semiconductor and a buffer layer comprising a group III nitride semiconductor including a region in which a region near a bonding interface with a substrate is mainly composed of a single crystal and including a region in which a hexagonal phase crystal and a cubic phase crystal coexist thereabove; Undoped n-type II deposited in contact with
An undoped crystal layer made of a group I nitride semiconductor, and an n-type group III nitride semiconductor deposited on the undoped crystal layer and doped with an n-type impurity and having a carrier concentration higher than that of the undoped crystal layer. A doping crystal layer;
A high carrier concentration crystal layer made of an n-type group III nitride semiconductor having a higher carrier concentration than the main phase of the multi-phase structure light emitting layer deposited on the doping crystal layer; A multi-phase structure luminescent layer composed of an n-type indium-containing group III compound semiconductor having a multi-phase structure and composed of a main phase and a dependent phase having different indium composition ratios deposited thereon and the multi-phase structure luminescent layer. And a formed p-type clad layer made of a group III nitride semiconductor.

According to a second aspect of the present invention, there is provided a nitride semiconductor light emitting device according to the first aspect of the present invention, wherein an n-type light emitting device is provided between the multi-phase light emitting layer and the p-type cladding layer. II
An n-type intervening layer made of a group I nitride semiconductor crystal is provided. According to a third aspect of the present invention, in the nitride semiconductor light emitting device according to the second aspect of the present invention, the n-type intermediate layer has a conduction band side with a main phase constituting the multiphase structure light emitting layer. Is made of an n-type group III nitride semiconductor crystal having a band discontinuity of not less than 0.3 electron volts (eV) and not more than 1.0 eV and a carrier concentration of not more than 5 × 10 ¹⁷ cm ^-3. Is what you do.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Each constituent layer of a nitride semiconductor light emitting device according to the present invention is mainly made of metal organic chemical vapor deposition (MO).
(CVD method). A first feature of the buffer layer described in the first embodiment according to the invention described in claim 1 of the present application is that a region near a bonding surface with a substrate is mainly formed of a single crystal. Al _C which is made of amorphous or amorphous including polycrystal like conventional low temperature buffer layer
It differs from the low-temperature buffer layer made of Ga _{1 -C} N (0 ≦ C ≦ 1) in its constituent requirements (see JP-A-2-229476). This is because a single crystal has a stronger mutual bonding force of constituent atoms than a conventional amorphous body. Therefore, if the surface of the substrate on which the group III nitride semiconductor crystal layer is to be deposited is covered with a single crystal layer as in the present embodiment, even when the substrate is exposed to a higher temperature, the group III nitride semiconductor The probability of exposing the surface of the substrate that is not in a lattice matching relationship with the crystal layer is reduced. That is, the effect of relaxing the lattice mismatch between the substrate material and the group III nitride semiconductor crystal can be more reliably achieved,
This can contribute to obtaining a group III nitride semiconductor crystal layer having excellent crystallinity. Whether or not the vicinity of the bonding interface with the substrate crystal is a single crystal region can be generally confirmed by a technique such as lattice image observation using a transmission electron microscope (TEM).

The buffer layer according to the present invention is made of aluminum / gallium / indium nitride (Al _x Ga _y I
n _1-XY N: 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0.7 ≦ X + Y
.Ltoreq.1). It is desirable that the composition ratio of indium (In) be suppressed to 0.3 or less. This is because a high indium composition ratio impairs the flatness of the layer due to the generation of indium droplets. Means for constructing a buffer layer mainly composed of a single crystal in a region near a bonding interface with a single crystal substrate from such a material has already been disclosed by the present inventor (Japanese Patent Application Laid-Open No. 10-22224). reference). The temperature for forming the buffer layer is preferably about 400 ° C. to about 500 ° C. The layer thickness is desirably in the range of about 5 nm to 30 nm. A thin layer having a thickness of less than about 5 nm lacks continuity in the first place and may not sufficiently cover the substrate surface. When the thickness exceeds about 30 to 50 nm, columnar (column-shaped) crystals having a pyramid at the top become vigorous, which results in the flatness of the surface of the upper layer being reduced.

A second feature of the buffer layer of the present invention is that a region in which a cubic crystal phase and a hexagonal crystal phase coexist above a region near a bonding interface in the buffer layer (heterophase crystal coexistence). Region). FIG. 6 shows an example of the buffer layer of the present invention with respect to a gallium nitride (GaN) buffer layer 20 deposited on a (0001) -sapphire substrate 10.
It is a mimetic diagram of a section TEM (transmission electron microscope) image given in order to show the form of the above coexistence. The region 10b near the bonding interface 10a with the substrate 10 is mainly made of a single crystal as described above. The layer thickness of the region 10b may be about several nm corresponding to the thickness of one to several lattices, and may correspond to about half of the layer thickness of the buffer layer 20. Crystal phase C consisting of cubic
Is composed of a cubic crystal such as a zinc-blend type. The crystal phase H composed of a hexagonal crystal is a phase composed of a wurtzite-type hexagonal crystal (phase or domain). The crystal phase C and the crystal phase H are
There may be a case where a heterophase coexistence region W1 is formed adjacent to each other. Further, there may be a case where the crystal phase C and the crystal phase H are alternately layered to form the hetero-phase crystal region W2, which is preferable for the present invention. The main reason that W2 is preferred is that
This is because the alternating multilayer structure of the phases C and H can exert an effect of alleviating lattice distortion. At the interface where different phases of the crystal phase C and the crystal phase H are layered, [1] of the cubic lattice
This is because stacking faults tend to occur mainly in the [11] direction, and these crystal defects are effective in alleviating lattice distortion and the like.

In order to form the region W2 in the coexisting regions W1 and W2, which is particularly effective in alleviating strain and the like, the V of the group III constituent element must be reduced when the buffer layer 20 is formed. It is necessary to precisely control the supply ratio of the group element raw material, that is, the so-called V / III ratio. In particular, it is necessary to set the V / III ratio on the high ratio side of, for example, 1.5 × 10 ⁴ or more. On the low ratio side of about 1 to 2 × 10 ³ , for example, gallium (Ga) droplets are likely to be generated, and a hexagonal nitride semiconductor crystal is likely to grow through the Ga droplets. It is.

FIG. 7 shows an n-type clad comprising the buffer layer 20 and an undoped crystal layer, a doped crystal layer and a high carrier concentration layer deposited on the buffer layer 20 according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view conceptually showing an internal configuration of a layer 30. In the n-type lower cladding layer 30 deposited on the buffer layer 20, a region where the junction with the buffer layer 20 is formed is not intentionally doped with an impurity.
Undoped layer of a group III nitride semiconductor
pe) The crystal layer 30a is arranged. For example, high concentration doped silicon (Si), which is a typical n-type impurity, II
When the group I nitride semiconductor crystal layer is provided directly in contact with the buffer layer 20, cracks are generated in the buffer layer 20 due to shrinkage of the buffer layer 20 due to incorporation of Si into the buffer layer 20. Failure occurs. A continuous growth layer is not deposited on the buffer layer 20 that has lost continuity due to the generation of cracks. In the case of the cladding layer lacking continuity, the flow resistance of the device operating current increases, and therefore, the expansion of the device operating current, which is effective for expanding the light emitting region, cannot be sufficiently achieved, which is disadvantageous. In order to avoid such a situation, according to the present invention, as described above, the undoped n-type group III nitride semiconductor crystal layer 30a not doped with impurities such as Si is used as the buffer layer 2.
0 as the first deposited layer.

The region near the bonding interface 10a with the substrate 10 is constituted by a single crystal region, and measures are taken to prevent the surface of the substrate from being exposed. Buffer layer 2 provided with coexistence regions W1 and W2
0 and the undoped n-type group III nitride semiconductor crystal layer 30a provided on the buffer layer 20 and bonded to the buffer layer 20, a group III nitride semiconductor crystal layer having particularly excellent crystallinity can be deposited. . It is desirable that the thickness of the undoped crystal layer 30a be smaller than that of a later-described doped crystal layer 30b.
This is because if the thickness is larger than the doping crystal layer 30b, the flow resistance of the device operating current may increase. While the thickness of the doped crystal layer 30b is approximately 2 to 5 μm, the thickness of the undoped crystal layer 30a is generally 2 μm.
It is desirable to keep the thickness below about 1 μm, and a layer thickness of about 1 μm is suitable.

Next, as shown in FIG. 7, an n-type doping crystal layer 30b doped with an n-type impurity is deposited on the undoped group III nitride semiconductor crystal layer 30a. Unlike the case of the buffer layer 20 deposited at a low temperature, the undoped crystal layer 3 formed at a higher temperature, usually around about 1000 ° C.
The surface of Oa is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ^−3.
Even when depositing the doping crystal layer 30b doped with Si that provides a certain carrier concentration, erosion is rare. Therefore, a crystal layer having excellent conductivity can be deposited. In particular, the doped crystal layer 30b having a high carrier concentration exceeding the carrier concentration of the undoped crystal layer 30a has excellent crystallinity and phase due to being deposited on the buffer layer 20 and the undoped crystal layer 30a of the present embodiment. In addition, it can contribute to providing an n-type ohmic electrode having low contact resistance.

Further, in the first embodiment of the present invention, the high carrier concentration crystal layer 30c is formed on the doping crystal layer 30b.
Is provided. The high carrier concentration crystal layer 3
The carrier concentration of 0c is assumed to exceed the carrier concentration of the main phase S of the light emitting layer 40 having a multi-phase structure deposited on the high carrier concentration crystal layer 30c. The main phase S is directly under the light emitting layer 40.
By disposing the low-resistance crystal layer 30c having a high carrier concentration exceeding the carrier concentration of the above, the device operating current can be diffused over a wide range of the light emitting layer 40. That is, an effect of extending the light emitting area (region) is obtained. The light emitting layer 40 having a multiphase structure is composed of a main phase S having a different indium composition ratio and a plurality of subordinate phases T. The dependent phase T is usually in the form of microcrystals and is scattered in the main phase S. The contact surface with the high carrier concentration crystal layer 30c is in a state where the main phase S occupies the whole. Therefore, the carrier concentration of the high carrier concentration crystal layer 30c is determined based on the carrier concentration of the main phase S.

The high carrier concentration crystal layer 30c is formed in about 1 × 1
When it is necessary to form a group III nitride semiconductor crystal layer having a high carrier concentration exceeding 0 ²⁰ cm ^-3 , unnecessary increase in the layer thickness is avoided. This is because an increase in the layer thickness causes deterioration of the surface state. It is desirable that the layer thickness be approximately 2 nm or more and about 20 nm or less.

The high carrier concentration crystal layer 30c is made of n-type Al
_{X Ga Y In 1-XY N} (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦
X + Y ≦ 1). Also, a general formula such as gallium arsenide nitride (GaN _1-D As _D : 0 ≦ D <1) such as Al _X G
_{a Y In 1-XY N 1} -D Q D (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,
It can be composed of an n-type group III nitride semiconductor material represented by 0 ≦ X + Y ≦ 1, 0 ≦ D <1, and Q is a group V element other than nitrogen). In particular, the main phase S constituting the multi-phase structure light emitting layer 40
High carrier concentration crystal layer 3 made of substantially the same material as
0c is a crystal layer of excellent quality with few crystal defects such as mis-fit dislocations due to mutual good lattice matching between the high carrier concentration crystal layer and the light emitting layer;
This effectively acts as a current spreading layer. Further, it is not preferable that the high carrier concentration crystal layer 30c be made of a material having a band gap smaller than the main phase S. Therefore, the composition ratio of the constituent elements of the above-mentioned materials is naturally limited in order to maintain the magnitude relation of the band gap. The high carrier concentration crystal layer 30c has a smaller band gap than the doping crystal layer 30b, and preferably has a conduction band discontinuity (offset) with the constituent material of the main phase S of about 0.2 eV or less. It is preferred to be composed of a material that is

FIG. 8B is a diagram for conceptually explaining the potential structure on the conduction band CB side of each of the constituent layers 30a, 30b and 30c constituting the n-type clad layer 30. FIG. 8A shows the magnitude relationship between the carrier concentrations CCa, CCb, and CCc between the constituent layers, together with the carrier concentration CCs of the main phase S. Undoped crystal layer 30
a and the doping crystal layer 30b may be made of a group III nitride semiconductor material having the same forbidden band width (ΔEg) a and (ΔEg) b. However, the carrier concentration CCb of the doping crystal layer 30b is higher than the carrier concentration CCa of the undoped crystal layer 30a.
That is, it is necessary to hold the magnitude relationship of CCb> CCa. The high carrier concentration crystal layer 30c has a carrier concentration CCc higher than the carrier concentration CCb of the doping crystal layer 30b (CCc> CCb), and the forbidden band width (ΔEg) c of the high carrier concentration crystal layer 30c is small. The forbidden band width (ΔEg) b of the doping crystal layer 30b is smaller ((ΔEg) c <(ΔEg) b) or equal to both ((ΔEg) c = (ΔEg) b). It is preferable to use a material that generates a band offset OF on the conduction band CB side lower than the main phase S of (ΔEg) s by about 0.2 eV or less.

Therefore, according to the first embodiment, n
The most preferable configuration of the shaped cladding layer 30 is that at least three layers composed of an undoped crystal layer, a doped crystal layer and a high carrier concentration layer having different carrier concentrations are provided between the buffer layer 20 and the light emitting layer 40. From the light emitting layer 40
And at the same time, the forbidden band widths (ΔEg) a, (ΔEg) b, and (ΔEg) c of the at least three layers are set in the direction, Contrary to the case of the carrier concentration, the configuration is such that it becomes equal or lower sequentially. In summary, the carrier concentrations CCa, CCb. CCc is changed in at least three steps, and the band gap is reduced in contrast to the increase in the carrier concentration. The simple structure in which three layers having different carrier concentrations are simply laminated is different from that in the first embodiment. Not (U
nighted State Patent 5,729,
029). In the first embodiment, on the high carrier concentration crystal layer 30c, a multi-phase structure composed of a main phase and a sub phase having different indium composition ratios is joined to the high carrier concentration crystal layer. By depositing a multi-phase light emitting layer 40 made of an n-type indium-containing group III compound semiconductor and further depositing a p-type cladding layer 60 made of a group III nitride semiconductor on the multi-phase light emitting layer, A light emitting section having a junction type double hetero structure is formed. Thereby, a high output nitride semiconductor light emitting device can be obtained.

In the second embodiment according to the second or third aspect of the present invention, as shown in FIG. 9, an n-type III layer is provided between the multi-phase structure light emitting layer 40 and the p-type cladding layer 60.
It is preferable to adopt a configuration in which an n-type intervening layer 50 made of a group III nitride semiconductor crystal is interposed. The n-type intervening layer 50 has the band gap of the main phase S of the multi-phase structure light emitting layer 40 (ΔE
g) A group III nitride semiconductor material larger than s.

If the n-type intervening layer 50 is made of a group III nitride semiconductor material having a band gap larger than that of the main phase S, the light emitted from the multi-phase structured light emitting layer 40 is not absorbed but efficiently emitted to the outside. Released well. However, if the n-type intervening layer 50 is made of a material having an extremely large band gap, the light emitting layer 4
Although it is convenient to transmit the light emitted from 0 to the outside, it disadvantageously increases the forward voltage. Therefore, considering the “confinement” of carriers in the light emitting layer 40, the n-type intervening layer 50 reduces the band discontinuity (band offset amount) on the conduction band CB side with respect to the main phase S, preferably to zero. It is preferably made of a group III nitride semiconductor material having a voltage of not less than 2 eV and less than 2 eV, preferably, not less than 0.3 eV and not more than 1.0 eV. The conduction band CB
(Off-set) amount OFn of the side band
Is obtained by multiplying the difference between the band gap of the material constituting the n-type intermediate layer 50 and the band gap of the main phase of the multi-phase structure light emitting layer by the offset ratio on the conduction band CB side (Mat. Res. So).
c. Symp. Proc. , Vol. 395 (199
6), pages 123 to 134).

The n-type intermediate layer 50 is composed of a high-purity, low-carrier-concentration thin layer whose carrier concentration is equal to or lower than the carrier concentration CCs of the main phase S. n-type intermediate layer 50
Is preferably 5 × 10 ¹⁷ cm ⁻³ or less. Suitable layer thicknesses range from about 2 nm to about 20 nm. Relatively high resistance at low carrier concentration III
In order to form the n-type intervening layer 50 from a group III nitride semiconductor layer,
An increase in the layer thickness undesirably causes an increase in the forward voltage (so-called Vf) and an increase in the calorific value of the light emitting element. Conversely, if the layer is extremely thin, the continuity of the layer is impaired, the layers are intermittently connected, and there is an inconvenience that local "confinement" of the carrier is incomplete. n-type intermediate layer 50
Represents aluminum gallium nitride (Al _x Ga _{1 -x} N:
0 ≦ X ≦ 1) or Al _X Ga _Y In _1-XY N _1-D Q _D (0
≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ X + Y ≦ 1, 0 ≦ D <1, and Q is a Group V element other than nitrogen).

When the n-type intervening layer 50 is deposited with the steepness of the composition at the bonding interface 40 a with the multi-phase structure light emitting layer 40, the n-type intervening layer 50 is formed in a region near the bonding interface 40 a in the multi-phase structure light emitting layer 40. It functions to create the low potential portion LPc of the conduction band CB. FIG. 10 is a potential configuration diagram for explaining this situation. For example, by adopting the growth interruption method (edited by Optical Technology Research Institute, "Basic Technology of Opto-Electronic Integrated Circuits" (Ohm Co., Ltd., August 20, 1989, first edition, first printing), pp. 197-204. If the composition steepness at the bonding interface 40a is achieved, the region in the multi-phase light emitting layer 40 near the bonding interface 40a between the multi-phase light emitting layer 40 and the n-type intervening layer 50 will have conduction. A low potential region LPc is formed in which the band CB is bent to the Fermi-level F side. This conduction band C
Electrons e supplied from the n-type cladding layer 30 are captured in the low potential region LPc on the B side. The presence of this localized electron e results in highly efficient radiative recombination.

In order to efficiently introduce and store the electrons e from the n-type cladding layer 30 side into the low potential region LPc efficiently, the band gap of the n-type cladding layer 30 is set to the multi-phase structure light emitting layer 40. It is preferable to adopt a configuration in which the temperature is gradually decreased toward the surface. Explaining with reference to FIG.
The shape cladding layer 30 has a band gap (ΔEg)
a, (ΔEg) b, (ΔEg) c is (ΔEg) c <(Δ
It is best to include the undoped crystal layer 30a, the doping crystal layer 30b, and the high carrier concentration layer forming layer 30c that maintain the relationship of Eg) b <(ΔEg) a.

Light emitting diode (LED) according to the present invention
Alternatively, for a light emitting element such as a laser diode (LD), an appropriate processing is performed on the laminated structure having the configuration described in the first or second embodiment, and n-type and p-type ohmic electrodes are laid. Can be formed. When the n-type ohmic electrode is provided in contact with the doping crystal layer 30b or the high carrier concentration crystal layer 30c, an ohmic electrode with low contact resistance can be formed.

[0033]

In the buffer layer according to the first aspect, a region near the interface with the substrate crystal is formed of a single crystal, and a hetero-phase coexisting region capable of absorbing crystal strain is included above the single crystal. It functions to improve the crystallinity of each layer constituting the n-type clad layer to be deposited.

Further, the undoped crystal layer bonded to the buffer layer according to the first aspect is made of an undoped group III nitride semiconductor crystal, so that it has an effect of avoiding loss of the buffer layer due to impurity doping. Has the effect of improving the crystallinity of the crystal layer deposited thereon. Also,
The doping crystal layer is a low-resistance layer having excellent crystallinity and an appropriate carrier concentration and excellent conductivity, and is suitable for forming an n-type ohmic electrode having low contact resistance.

Further, the high carrier concentration crystal layer according to claim 1 is laminated with a buffer layer, an undoped crystal layer, and a doping crystal layer interposed therebetween, so that both the crystallinity and the conductivity are excellent. In addition, it can function as a current diffusion layer capable of expanding a light emitting region (light emitting area).

The n-type intermediate layer according to the second aspect has a function of forming a low potential region on the conduction band side of the multi-phase structure light emitting layer and accumulating electrons in the low potential region.

[0037]

EXAMPLES (Example 1) Hereinafter, the content of the present invention will be specifically described by taking as an example a case of manufacturing an LED having the configuration of the first embodiment according to the first aspect of the present invention. I do. Each constituent layer of the LED of Example 1 was formed by metal organic chemical vapor deposition (MOCVD). FIG. 1 schematically illustrates a planar structure of an LED 1A configured from the laminated structure 1B manufactured in the first embodiment. FIG. 2 is a schematic diagram showing a cross-sectional structure of a central portion of the LED 1A along the broken line AA 'in FIG.

The laminated structure 1B is made of sapphire (α-Al
₂ O ₃ single crystal) is used as the substrate 101. On the (0001) surface of the sapphire substrate 101, a buffer layer 102 made of undoped GaN was deposited using trimethylgallium ((CH ₃ ) ₃ Ga) and liquefied ammonia as raw materials. The GaN buffer layer 102 has a deposition temperature of 430 ° C.
The film was formed by normal pressure (atmospheric pressure) MOCVD with the V / III ratio set to 1.6 × 10 ⁴ . Thus, the region near the bonding interface 101a with the sapphire substrate 101 was formed as the buffer layer 102 mainly composed of single crystal. Above the single crystal region in the buffer layer, a region where heterophase crystals coexist is included. The upper region of the buffer layer 102 having a thickness of about 17 nm was mainly an amorphous region.

On the buffer layer 102, a carrier concentration of about 3
An undoped GaN layer of × 10 ¹⁷ cm ⁻³ was deposited as the first constituent layer 103 a of the n-type cladding layer 103.
The first constituent layer 103a was formed at 1050 ° C., and the thickness was 0.8 μm. This first constituent layer 103a corresponds to an undoped crystal layer.

On the first constituent layer 103a, an n-type GaN layer doped with Si and having a carrier concentration of about 4 × 10 ¹⁸ cm ⁻³ was laminated as a second n-type clad layer constituent layer 103b. The thickness of the Si doping layer 103b was about 2.5 μm. This second constituent layer 103b corresponds to a doping crystal layer.

Subsequently, a carrier concentration of about 8 × 1 is formed on the second constituent layer 103b by doping with Si.
High carrier concentration layer 10 made of GaN of 0 ¹⁹ cm ^-3
3c was deposited. The layer thickness of the high carrier concentration layer 103c was about 1.5 nm. This high carrier concentration layer 103c corresponds to a high carrier concentration crystal layer. The above three constituent layers 103
The n-type cladding layer 103 was composed of a, 103b, and 103c.

On the n-cladding layer 103, an n-type light-emitting layer 104 having a multiphase structure in which the main phase is n-type Ga _0.88 In _0.12 N
Was deposited. The carrier concentration of the main phase of the light emitting layer 104 was about 2 × 10 ¹⁸ cm ⁻³ . The layer thickness of the main phase is about 6 nm, and the layer thickness of the main phase is substantially equal to the layer thickness of the light emitting layer 104. This light emitting layer 104 corresponds to a multi-phase structure light emitting layer.

A p-type upper cladding layer 106 was directly bonded on the light emitting layer 104 having a multi-phase structure. This p-type cladding layer 106 is Mg-doped p-type Al _x Ga ₁ -xN in which the Al composition is graded so that the Al composition becomes 0.12 at the junction interface with the light emitting layer 104 and becomes 0 at the surface. It was composed of layers (X = 0.12 → 0, layer thickness = 300 nm, carrier concentration = 2 × 10 ¹⁷ cm ⁻³ ).

A patterning technique based on a general photolithography technique and an argon (A)
r) / Methane (CH ₄ ) / Hydrogen (H ₂ ) A process for forming an element (chip) is performed by using a plasma etching technique or the like using a mixed gas to obtain a substantially square LED 1A having a side of about 320 μm. did. The p-type ohmic electrode 107 for constituting the LED 1A is made of Mg-doped Al _x Ga
A pedestal electrode 107a having a two-layer structure in which the side in contact with the surface of the p-type cladding layer 106 made of a _1- XN composition gradient layer is made of a gold-zinc alloy (Au 95% by weight, Zn 5% by weight) and the upper layer is made of Au. And a translucent electrode 107b made of a conductive titanium nitride (TiN) thin film. The n-type ohmic electrode 108 was placed in contact with one constituent layer 103b of the lower clad layer 103 whose upper portion was removed by plasma etching and exposed. The n-type ohmic electrode 108 was made of aluminum (Al).

An operating current of 20 mA was passed in the forward direction between the p-type ohmic electrode 107 and the n-type ohmic electrode 108 of the LED 1A, and blue light emission having a center emission wavelength of 440 nm was obtained. The appearance of a subordinate spectrum accompanying the main emission spectrum was not recognized, so that the half width of the spectrum was as good as about 9 nm. In addition, the light emitting region spread over substantially the entire surface of the light emitting layer having a plane area of about 4 × 10 ⁻⁴ cm ⁻² after the etching process. Thus, the light emission intensity measured by a general integrating sphere is about 21 microwatts (μ
W).

Example 2 In Example 2, the content of the present invention will be specifically described by taking as an example the case of manufacturing an LED having the second embodiment according to the second or third aspect of the present invention. Will be explained. Laminated structure 2B produced in Example 2
FIG. 3 schematically shows a planar structure of the LED 2 </ b> A configured from the above. FIG. 4 shows an LED along a broken line BB ′ in FIG.
2A schematically illustrates a cross-sectional structure of a central portion of 2A.

The buffer layer 102 deposited in the same manner as in Example 1 is mainly formed of a single crystal in the vicinity of the bonding interface 101a with the sapphire substrate 101, and is provided with a hetero-phase crystal coexisting region.
An undoped n-type Ga _0.98 In _0.02 N undoped crystal layer having a carrier concentration of about 6 × 10 ¹⁷ cm ⁻³ was deposited thereon as the first n-type cladding layer constituting layer 103a. The layer thickness of the first constituent layer 103a was about 0.1 μm. On the first constituent layer 103a, n-type G is doped with Si to have a carrier concentration of about 3 × 10 ¹⁸ cm ^−3.
A doping crystal layer made of a _0.97 In _0.03 N was laminated as the second constituent layer 103b of the n-type cladding layer 103. The layer thickness of the second constituent layer 103b is about 3.5 μm
And Further, on the second constituent layer 103b, an Si-doped n-type G-type layer having a carrier concentration of about 6 × 10 ¹⁹ cm ⁻³
a High carrier concentration crystal layer 1 composed of a _0.96 In _0.04 N
03c was arranged. The thickness of the high carrier concentration crystal layer 103c was set to about 10 nm. The above three constituent layers 103
The n-type cladding layer 103 was formed by laminating a, 103b and 103c.

On the n-type cladding layer 103, a high carrier
Ga same as concentration crystal layer 103c_0.96In_0.04From N
Undoped, n-type multiphase light emission with phase S
Layer 104 was deposited. The light-emitting layer 104 is made of indium
Ga whose average composition is 0.10 _0.90In_0.10N.
The carrier concentration of the light emitting layer 104 is about 4 × 10¹⁷cm^-3age
Was. The layer thickness of the main phase S is about 5 nm,
Is substantially equal to the layer thickness of the light emitting layer 104.

An undoped n-type Al _0.15 having an aluminum composition ratio of 0.15 is formed on the multi-phase structure light emitting layer 104.
An n-type intermediate layer 105 made of Ga _0.85 N crystal was deposited.
The carrier concentration of the n-type intermediate layer 105 is about 1 × 10 ¹⁷ c
m ⁻³ and the layer thickness was about 12 nm. Laminated structure 2B
Was formed by a general atmospheric pressure MOCVD method, but in particular, between the formation of the light emitting layer 104 and the n-type intervening layer 105, the bonding interface 104a was sharpened. Interrupted for 5 minutes. From the analysis results of the indium atom concentration distribution in the depth direction by a general SIMS analysis method,
The transition distance from the junction interface 104a into the n-type intervening layer 105 required for the indium atom concentration to decrease by two orders of magnitude from the average concentration of the light emitting layer 104 was shown to be about 10 nm. With the steepness of the junction interface 104a, the conduction band was bent in a region near the junction interface 104a with the n-type intervening layer 105 in the light emitting layer 104, thereby forming a low potential region sufficient for accumulating electrons.

On the n-type intervening layer 105, the aluminum composition is 0.20 at the joint interface with the n-type intervening layer 105,
It is made of Mg-doped p-type Al _x Ga ₁ -xN (X = 0.20 → 0) in which the aluminum composition is graded almost linearly so that it becomes 0 while the layer thickness reaches about 100 nm. A p-type cladding layer was deposited as upper cladding layer 106.

Thereafter, the laminated structure 2B was cooled stepwise. First, after the formation of the p-type cladding layer 106 is completed at 1050 ° C., it is first cooled to 950 ° C. at a rate of 40 ° C./min, and then cooled from 950 ° C. to 650 ° C. at a rate of 10 ° C./min. did. By this cooling means, n-type Ga having an average composition of indium constituting the light emitting layer 104 of 0.10 is used.
_0.90 In _0.10 N is composed of two phases: a main phase S composed of Ga _0.96 In _0.04 N and a dependent phase T composed of substantially spherical or hemispherical microcrystals having an indium composition ratio of about 12 to 15%. It became a multi-phase structure. FIG. 5 shows the light emitting layer 10 described above.
4 shows a cross-sectional transmission TEM image showing the internal crystal structure of Sample No. 4.
It can be seen that the dependent phase T containing indium richer is scattered inside the layered main phase S. It was also recognized that an area U including distortion was formed at the boundary between the main phase S and the subordinate phase T.

Then, using the laminated structure 2B manufactured as described above, the LED 2A
Was prepared. P-type and n-type electrodes 107 of LED 2A,
A forward voltage of about 3.5 V is applied between 108 and 20 mA
Through the forward current of about 480 n
m, short-wavelength visible light in the blue-green band was obtained. The transition energy giving this center emission wavelength (= 480 nm) is 2.58 eV in theory according to the photon theory. Light emitting layer 104
The intrinsic band gap at room temperature of Ga _0.90 In _0.10 N is about 3.2 eV (see Japanese Patent Publication No. 55-3834), and the corresponding wavelength is about 388 nm. That is, as described in the second embodiment, the hetero-junction structure of the light-emitting portion of the LED 2A, which is configured to particularly improve the steepness of the composition at the bonding interface 104a between the light-emitting layer 104 and the n-type intermediate layer 105, is as follows. The transition energy of the light emitting layer 104 is reduced by about 0.62 eV as compared with the original band gap (about 3.2 eV), so that the energy of the material forming the light emitting layer 104 is lower than the original band gap energy. Light emission was simply obtained. In addition, a region that emits light reaches almost the entire region of the light emitting layer 104,
For this reason, the light emission intensity of the LED measured in the chip state was as high as about 26 μW.

[0053]

According to the nitride semiconductor light emitting device according to the first aspect of the present invention, by depositing an n-type cladding layer on a buffer layer having a unique crystal structure,
Since the n-type cladding layer is composed of the n-type group III nitride semiconductor layer having excellent crystallinity, the operating current is diffused over a wide range, and therefore, the light-emitting region is extended, and high-luminance short-wavelength visible light is emitted. A nitride semiconductor light emitting device is obtained.

According to the nitride semiconductor light emitting device according to the second and third aspects of the present invention, the n-type intervening layer is joined to the n-type multi-phase structure light emitting layer, and the junction interface in the light emitting layer is formed. Nitride semiconductors with excellent emission intensity, especially those that emit relatively long wavelength visible light, because they create a band configuration in which the conduction band is bent to the lower potential side in the nearby region and localize electrons. A light emitting element is obtained.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of an LED according to a first embodiment.

FIG. 2 is a schematic cross-sectional view taken along line AA ′ of the LED in FIG.

FIG. 3 is a schematic plan view of an LED according to a second embodiment.

FIG. 4 is a schematic cross-sectional view along the line BB ′ of the LED in FIG. 3;

FIG. 5 is a cross-sectional view showing an internal crystal structure of a light emitting layer having a multi-phase structure of an LED according to Example 2.

FIG. 6 is a cross-sectional view showing an internal configuration of a buffer layer according to the present invention.

FIG. 7 is a cross-sectional view showing a configuration of an n-type cladding layer according to the present invention.

FIG. 8A is a diagram showing the relationship between the carrier concentration of each constituent layer of the n-type cladding layer and the main phase of the multi-phase structure light emitting layer according to the present invention. (A) is a diagram showing the relationship between the bandgap of each constituent layer of the n-type cladding layer according to the present invention and the main phase of the multi-phase light emitting layer.

FIG. 9 is a sectional view showing an arrangement of an n-type intervening layer according to the present invention.

FIG. 10 is a diagram showing a band potential structure of a light emitting portion of a light emitting device provided by an n-type intervening layer according to the present invention.

[Explanation of symbols]

Reference Signs List 1A, 2A LED 1B, 2B laminated structure 10 substrate 10a bonding interface between substrate and buffer layer 10b region near bonding interface between substrate and buffer layer 20 buffer layer 30 n-cladding layer 30a undoped crystal constituting n-cladding layer Layer 30b Impurity-doped crystal layer forming n-type cladding layer 30c High carrier concentration crystal layer forming n-type cladding layer 40 Multi-phase structure light-emitting layer 40a Junction interface between multi-phase structure light-emitting layer and n-type intermediate layer 50 n-type Intervening layer 60 p-type cladding layer 101 crystal substrate 101a bonding interface between substrate and buffer layer 102 buffer layer 103 n-type cladding layer 103a undoped crystal layer forming n-type cladding layer 103b impurity-doping crystal layer forming n-type cladding layer 103c High carrier concentration crystal layer constituting n-type cladding layer 104 Multi-phase structure light emitting layer 1 4a Junction interface between multiphase structure light emitting layer and n-type intervening layer 105 n-type intervening layer 106 p-type cladding layer 107 p-type ohmic electrode 107a pedestal electrode 107b translucent electrode 108 n-type ohmic electrode CB conduction band CCa n-type cladding Carrier concentration of the undoped crystal layer constituting the layer CCb Carrier concentration of the impurity-doped crystal layer constituting the n-type cladding layer CCc Carrier concentration of the high carrier concentration crystal layer constituting the n-type cladding layer CCs Main phase of the multi-phase light emitting layer (ΔEg) a Bandgap of undoped crystal layer (ΔEg) b Bandgap of impurity-doped crystal layer (ΔEg) c Bandgap of high carrier concentration crystal layer (ΔEg) s Main body of multi-phase structure light emitting layer Phase band gap C Crystal region composed of cubic crystal H Crystal region composed of hexagonal crystal W1 Hexagonal crystal with cubic crystal phase Heterogeneous crystal coexistence region where crystal phases are adjacent to each other W2 Heterogeneous crystal coexistence region where cubic crystal phase and hexagonal crystal phase are overlaid e Electron F Fermi level LPc Low potential portion of conduction band OF Multiphase structure light emitting layer Band offset on the conduction band between the main phase and the high carrier concentration layer of OFn Band offset on the conduction band between the main phase and the intervening layer of the multi-layer structure light emitting layer S Main phase T Dependent layer U Strain region

Claims (3)

[Claims] 1. A single crystal substrate, and a region deposited on the single crystal substrate and near a bonding interface with the single crystal substrate is mainly composed of a single crystal, and a hexagonal phase crystal and a cubic crystal are formed above the single crystal. II including regions where phase crystals coexist
A buffer layer made of a group I nitride semiconductor, an undoped n-type crystal layer made of an undoped n-type group III nitride semiconductor deposited on the buffer layer, and an n-type impurity deposited on the undoped crystal layer. A doping crystal layer made of an n-type group III nitride semiconductor having a carrier concentration higher than that of the undoped crystal layer; and a doping crystal layer deposited on the doping crystal layer, A high carrier concentration crystal layer made of an n-type group III nitride semiconductor having a high carrier concentration, and a main phase and a sub phase having different indium composition ratios deposited and bonded to the high carrier concentration crystal layer;
A nitride comprising a multi-phase structure light emitting layer composed of an n-type indium-containing group III compound semiconductor having a multi-phase structure and a p-type cladding layer composed of a group III nitride semiconductor formed on the multi-phase structure light emitting layer Semiconductor light emitting device. 2. An n-type group III nitride semiconductor crystal between the multi-phase structure light emitting layer and the p-type cladding layer.
The nitride semiconductor light-emitting device according to claim 1, wherein a shaped intervening layer is disposed. 3. The n-type intervening layer has a band discontinuity on the conduction band side with the main phase constituting the multi-phase structure light emitting layer of 0.
N-type with a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ or less at ³ eV or more and 1.0 eV or less.
3. The nitride semiconductor light emitting device according to claim 2, comprising a group III nitride semiconductor crystal.