1228311 五、發明說明（1) 本發明係有關於一種半導體裝置（semiconductor d e v i c e )之製造流程’特別是一種防止未著陸（偏離式）介 層孔（unlanded via)產生毒化（p〇ison)的方法。 當半導體裝置的尺寸持續地縮小，金屬内導線（m e七a 1 interconnect)之RC延遲會大幅影響高速元件（high speed dev i ce )的性能。因此，高速元件慢慢地以低介電常數之 介電材料取代原有之二氧化石夕介電材料。其中，HSQ (hydrogen silesquioxane)介電材料（介電常數約為3)具 有高熱穩定性、良好之填溝能力、以及低漏電之特性/所 以經常被應於金屬間介電材料（interietal dieUctr ic ;IMD)。另一適當的低介電常數之介電材料例如為摻氟矽 玻璃（F-doped silicate glass ;FSG)。 以下利用第1A圖至第1D圖以說明習知技術，其亦即在 金屬之間形成HSQ介電材料的例子。 其麻^ ％參照第U®，其顯示形成有金屬導線12的石夕 ^瘊in二面圖。金屬導線12表面形成有防反射層14。而矽 基底^亡方形成有HSQ介電材料層16 ;以及氧化層Η。 宰20，U參照第㈣，利用傳統微影製程形成光阻圖 開口。 光阻圖案20具有露出後續欲形成介層孔位置的 110當 =—請參照第1B圖以及lc圖，利用上述光阻圖案 介層孔22為止罩幕p進行、電聚式#刻步驟直到形成未著陸 案20。由於上之、二* =溼蝕刻方式剝除（striP)光阻圖 、述之一連串蝕刻步驟使HSQ介電材料丨6之微1228311 V. Description of the invention (1) The present invention relates to a manufacturing process of a semiconductor device (especially a method for preventing poisoning from unlanded vias). . When the size of a semiconductor device is continuously reduced, the RC delay of a metal inner conductor (me VIIa 1 interconnect) will greatly affect the performance of a high speed device (high speed device). Therefore, high-speed devices are slowly replacing the original SiO2 dielectric materials with dielectric materials with low dielectric constants. Among them, the HSQ (hydrogen silesquioxane) dielectric material (dielectric constant is about 3) has high thermal stability, good trench filling ability, and low leakage characteristics / so it is often applied to intermetal dielectric materials (interietal dieUctr ic; IMD). Another suitable low-k dielectric material is, for example, F-doped silicate glass (FSG). 1A to 1D are used to explain the conventional technique, which is an example of forming an HSQ dielectric material between metals. Refer to the U® for its hemp%, which shows a two-sided view of the stone lining with the metal wire 12 formed. An anti-reflection layer 14 is formed on the surface of the metal wire 12. On the silicon substrate, an HSQ dielectric material layer 16 and an oxide layer 氧化 are formed. Zai 20, U refers to the first step, using a traditional lithography process to form a photoresist opening. The photoresist pattern 20 has 110 when the position of the subsequent via hole is to be formed =-please refer to FIG. 1B and the lc diagram, and use the above-mentioned photoresist pattern via 22 to perform a mask p-type step until it is formed. Unlanded case 20. Because of the above, two * = wet etching stripping (striP) photoresist patterns, one of the series of etching steps described above makes the HSQ dielectric material very small.
第4頁 1228311Page 4 1228311
孔隙受損，造成酸液殘留在介層孔内，會腐蝕露出之金屬 導線12表面，最後造成介層孔22之毒化現象。 再者，請參照第1 D圖，利用化學氣相沈積法在含鎢氣 體的存在下，將鎢材料填入介層孔22内，以構成鎢插塞24 。毒化之介層孔22，無法形成結構完整之鎢插塞，在金屬 導線12側壁以及鎢插塞24之界面，會產生如符號26所示之 孔隙或是結構脆弱之處，而造成斷路的疑慮，此將大幅影 響高速元件之性能及可靠性。 根據上述目的，本發明提供一種防止未著陸介層孔露 出之金屬導線腐蝕的方法，適用於形成有金屬導線之半導 體基底，上述方法包括下列步驟：（a)在上述形成有金屬 導線之半導體基底上形成—HSQ或FS(;介電材料層；（b)選 擇性蝕刻上述HSQ或FSG介電材料層，以形成一露出部分上 述金屬導線的介層孔，上述介層孔係未著陸介層孔；以及 (c)在上述露出之金屬導線表面形成一氧化保護薄層。 上述防止金屬導線腐蝕的方法，其中金屬導線選自鋁、銘銅合金、銅金屬構成之族群。The pores are damaged, causing the acid solution to remain in the interstitial pores, which will corrode the surface of the exposed metal wires 12, and finally cause the poisoning of the interstitial holes 22. Further, referring to FIG. 1D, a tungsten material is filled into the interlayer hole 22 by a chemical vapor deposition method in the presence of a tungsten-containing gas to form a tungsten plug 24. The poisoned interlayer hole 22 cannot form a structurally complete tungsten plug. At the interface of the side wall of the metal wire 12 and the tungsten plug 24, pores or structural weaknesses as shown by symbol 26 will be generated, causing the possibility of disconnection. This will greatly affect the performance and reliability of high-speed components. According to the above object, the present invention provides a method for preventing corrosion of a metal wire exposed by an unlanded via hole, which is suitable for a semiconductor substrate formed with a metal wire. The method includes the following steps: (a) the semiconductor substrate with the metal wire formed on the semiconductor substrate; -HSQ or FS (; dielectric material layer; (b) selectively etch the above-mentioned HSQ or FSG dielectric material layer to form a via hole exposing a part of the metal wire, the via hole is an unlanded dielectric layer Holes; and (c) forming an oxidation protection thin layer on the exposed surface of the metal wire. The method for preventing corrosion of the metal wire, wherein the metal wire is selected from the group consisting of aluminum, copper alloy, and copper metal.
在 上 露出 述防止金屬導線腐蝕的方法，其中氧化保護薄層係 之金屬導線施以lo電襞處理法所形成。 再者，上述防止金屬導線腐蝕的方法，其中H2〇電漿 二理步驟係在20〜3 0(TC的溫度下以及〇5t〇rr〜5t〇rr的愚 力下完成。The method for preventing the corrosion of the metal wire is described above, wherein the metal wire of the oxidation protection thin layer system is formed by applying a galvanic treatment. Furthermore, in the method for preventing the corrosion of the metal wire, the H2O plasma two-step process is completed at a temperature of 20 ~ 30 ° C and a fool force of 05 to 0rr to 5 to 0rr.
並且，上述防止金屬導線腐蝕的 步驟係進行1 〇秒〜1 20秒。 方法，其中電漿處理 1228311 五、發明說明（4) 實施例 f參照第2 A圖〜第2E圖，其為根據本發明較佳實施例 在未著陸介層孔内形成鎢插塞之製造流程剖面圖。 首先，明參知、第2 A圖，其顯示形成有例如紹、|呂銅合 金或是銅構成之金屬導線1〇2的半導體基底1〇〇剖面圖。金 屬導線102表面最好形成一例如氮化鈦（TiN)之防反射層 104，以防止後續微影製程（photolithography)之曝光步 驟產生光線反射等不良效應。而半導體基底1〇〇上方形成 有HSQ介電材料層1〇6 ;以及氧化層1〇8。 接著’請參照第2 B圖，利用傳統微影製程形成光阻圖 案11 0 ’上述光阻圖案1丨〇具有露出後續欲形成介層孔位置 的開口。 然後，請參照第2B圖以及2C圖，利用上述光阻圖案 11 0當作#刻罩幕，並且施以非等向性電漿蝕刻法以蝕刻 未被光阻圖案11〇遮蔽之氧化層1〇8以及jjsq介電材料層1 〇6 直到形成路出金屬線102的介層孔112為止。其次，例如 利用座钱刻方式（w e t e t ch i ng )以剝除（s t r i p )光阻圖案 110 °上述介層孔112為露出金屬導線之側壁（side wall) 的未著陸（偏離式）之介層孔。 之後，請參照第2D圖，在例如20 °C〜300 °C的溫度下以> 及0· 5torr〜5 torr的壓力下進行〇2電漿處理，用以在金屬 導線102表面形成氧化保護薄層1 〇2a，上述氧化保護薄層 10 2a例如為氧化鋁層、鋁銅氧化層、或是氧化銅層等。另 外’較佳之H20電漿處理條件例如使用500〜20 00W的功率，In addition, the step of preventing the corrosion of the metal wire is performed for 10 seconds to 120 seconds. Method in which plasma treatment is performed 1228311 V. Description of the invention (4) Embodiment f refers to FIGS. 2A to 2E, which is a manufacturing process for forming a tungsten plug in an unlanded via hole according to a preferred embodiment of the present invention. Sectional view. First, referring to FIG. 2A, FIG. 2A shows a cross-sectional view of a semiconductor substrate 100 on which a metal wire 102 made of, for example, copper, copper, or copper is formed. An anti-reflection layer 104, such as titanium nitride (TiN), is preferably formed on the surface of the metal wire 102 to prevent adverse effects such as light reflection from subsequent exposure steps in photolithography. An HSQ dielectric material layer 106 and an oxide layer 108 are formed over the semiconductor substrate 100. Next, referring to FIG. 2B, a photoresist pattern 11 0 is formed by a conventional lithography process. The photoresist pattern 1 丨 above has an opening that exposes the position of a via hole to be formed later. Then, referring to FIG. 2B and FIG. 2C, the above photoresist pattern 11 0 is used as the # engraving mask, and an anisotropic plasma etching method is applied to etch the oxide layer 1 not masked by the photoresist pattern 110. 〇8 and jjsq dielectric material layer 106 until the via hole 112 of the exit metal line 102 is formed. Secondly, for example, using a wet engraving method to strip the photoresist pattern 110 ° The above-mentioned interlayer hole 112 is an unlanded (deviation) interlayer that exposes the side wall of the metal wire. hole. After that, please refer to FIG. 2D, and perform plasma treatment at a temperature of, for example, 20 ° C to 300 ° C and a pressure of 0.5 Torr to 5 Torr to form an oxidation protection on the surface of the metal wire 102. The thin layer 102a, and the above-mentioned oxidation protection thin layer 102a are, for example, an aluminum oxide layer, an aluminum copper oxide layer, or a copper oxide layer. In addition, the preferred H20 plasma processing conditions use, for example, a power of 500 ~ 200 00W,
第7頁 1228311 五、發明說明（5) 進行10秒〜120秒鐘。再者，亦可加入可保護HSQ介電材料 層106的氮氣（N2)，此時較佳112〇以及N2的流量比為100〜 1〇0〇3(^111/1〇〇〜1〇〇〇3(：(：111。藉由游離態或是自由基態之112〇 ’有利於氧化保護薄層1 〇2a的形成。而氮氣是輔助氣體， 並非必要成份。 再者，請參照第2E圖，利用化學氣相沈積法在含鎢氣 體的存在下，將鎢材料填入未著陸介層孔112内，以構成 鎢插塞1 2 0。 後續 法形成介 上述 然而本發 取代之。 明不於此 介電材料 發明 本發 在鋁、鋁 可避免使 即，防止 插塞。 再利用前述方 根據傳統技術繼續形成金屬導線 層孔’以完成多重金屬導線製程 氧化保護薄層1 02a是施以H20電漿處理所形成， 明不限於此’亦可利用熱氧化法或是熱水浸濕法 本發明實施例以HSQ介電材料層為例，然而本發 ’本發明亦適用於使用FSG及其他低介電常數之 的情況。 之特徵與效果 ，，特徵為施行h2〇電漿處理，以快速並有效地 銅等金屬導線表面形成一氧化保護薄層，藉此， 用HSQ介電材料層所造成之介層孔毒化現象，亦 金屬導線被腐蝕，進而形成結構、功能完整的鎢 雖然本發明ρ ^ 匕从較佳實施例揭露如上，然其並非用以 5 Γ #二f，任何熟習此項技藝者’在不脫離本發明之精 才申牙口乾》圍内，者^ 田τ作更動與潤飾，因此本發明之保護範圍 1228311 五、發明說明（6) 當視後附之申請專利範圍所界定者為準。Page 7 1228311 V. Description of the invention (5) The time is from 10 seconds to 120 seconds. In addition, nitrogen (N2) that can protect the HSQ dielectric material layer 106 may also be added. At this time, it is preferable that the flow rate ratio of 112 ° and N2 is 100 to 1003 (^ 111/1100 to 100). 〇3 (:(: 111. The free state or the free radical state of 112 ′ is beneficial to the formation of the oxidative protective thin layer 102a. Nitrogen is an auxiliary gas and is not an essential component. Moreover, please refer to FIG. 2E, In the presence of a tungsten-containing gas, a tungsten material is filled with a chemical vapor deposition method into the unlanded via hole 112 to form a tungsten plug 120. The subsequent method forms the above-mentioned method, but the present invention replaces it. The invention of this dielectric material is applied to aluminum and aluminum, which can prevent the plug and prevent plugging. The foregoing method is used to continue to form a metal wire layer hole according to the conventional technology to complete the multiple metal wire process oxidation protection thin layer. 02a is applied with H20 Formed by plasma treatment, it is not limited to this. A thermal oxidation method or a hot water wet method may also be used. The embodiment of the present invention uses the HSQ dielectric material layer as an example. However, the present invention is also applicable to the use of FSG and other The case of low dielectric constant. Features and effects, It is characterized by the implementation of h20 plasma treatment to quickly and effectively form a thin oxide protection layer on the surface of metal wires such as copper, thereby using the HSQ dielectric material layer to cause poisoning of the interlayer pores and the metal wires to be corroded. Further, the structure and function of tungsten are formed. Although the invention is disclosed as above from the preferred embodiment, it is not used for 5 Γ # 二 f. Anyone skilled in this art will not apply the teeth without departing from the essence of the invention. Within the scope of "Qian", ^ Tian τ makes changes and retouches, so the scope of protection of the present invention is 1228311 V. Description of the invention (6) The scope of the attached patent application shall prevail.