五、發明說明（l) 本發明係有關於一種半導體積體電路（sen]ic〇nductc)r integrated circuit)製程’特別是一種應用於内連線 (interconnects)之雙鑲嵌結構（duai damascene)的製作 方法。 以下利用第1 A圖〜第1 F圖所示的雙鑲嵌結構製程剖面 圖’以說明習知技術。 首先，請參照第1A圖’此剖面圖顯示形成有金屬導線 12之半導體基底1〇。半導體基底1〇上方依序形成有第^蝕 刻停止層14(etchUg stop layer)、第1氧化層16、第2蝕 刻停止層18。上述第1氧化層16的介電常數（dielectric constant)大約為4。而第1飯刻停止層η、第2蝕刻停止層 18例如為氮化矽層以^“）、或是氮氧化合物層 (Si OxNy )，上述氮化矽層以及氮氧化合物的具有良好的氧 化層蝕刻阻擋能力，然而其介電常數高達78左右。 接著’請參照第1 B圖’選擇性去除上述第2蝕刻停止 層U ’以在上述金屬導線12相對位置上方形成一開口2〇 ^ 然後，請參照第1C圖，在殘留的蝕刻停止層丨8上方形 成一第2氧化層22，其可以與上述第}氧化層22的材料相 同’為介電常數大約4的氧化層（TEOS、PETE0S)。 其次，請參照第1 D圖，符號24為光阻圖案，利用上述 J :圖案24當作蝕刻罩幕，並且進行非等向蝕刻步驟，以 第1溝槽26a以及與其並列的第2溝槽26b。 之後，請參照第1E圖，例如利用濕式溶液法剝除 光阻圖案2“接著，另外形成一光阻罩幕(圖未顯示;上；V. Description of the invention (l) The present invention relates to a semiconductor integrated circuit (sen) ic integrated circuit (process) process, particularly a dual-damascene structure (duai damascene) applied to interconnects. Production Method. In the following, a cross-sectional view of a dual damascene structure process shown in Figs. 1A to 1F is used to explain the conventional technique. First, referring to FIG. 1A, this sectional view shows a semiconductor substrate 10 on which a metal wire 12 is formed. A etch stop layer 14 (etchUg stop layer), a first oxide layer 16 and a second etch stop layer 18 are sequentially formed on the semiconductor substrate 10. The dielectric constant of the first oxide layer 16 is approximately 4. The first meal stop layer η and the second etch stop layer 18 are, for example, a silicon nitride layer or a silicon oxide layer (Si OxNy). The silicon nitride layer and the nitrogen oxide layer have good properties. The oxide layer has an etch stop capability, but its dielectric constant is as high as about 78. Next, 'Please refer to FIG. 1B' to selectively remove the second etch stop layer U 'to form an opening above the relative position of the metal wire 12 2 ^ Then, referring to FIG. 1C, a second oxide layer 22 is formed over the remaining etch stop layer. The second oxide layer 22 may be the same as the material of the above-mentioned second oxide layer 22, and is an oxide layer having a dielectric constant of about 4 (TEOS, PETE0S). Secondly, please refer to Figure 1D, symbol 24 is a photoresist pattern, using the above J: pattern 24 as an etching mask, and performing an anisotropic etching step, using the first trench 26a and the first parallel trenches. 2 trench 26b. After that, please refer to FIG. 1E, for example, using a wet solution method to strip the photoresist pattern 2 "Next, a photoresist mask is formed (not shown in the figure; above;
第4頁 五、發明說明（2) 且敍刻第1氧化層1 6 ’然後再蝕刻第1蝕刻停止層14以形成 露出上述金屬導線12的接觸孔28，此時，接觸孔28與第1 溝槽26a構成一雙鑲谈結構dd。緊接著，去除上述光阻罩 幕。 最後’請參照第1 F圊，在雙鑲嵌結構dd以及第2溝槽 26b内填入金屬材料’以分別形成第1内連線3〇a以及第2内 連線30b。 然而’由於氮化矽等構成的第2蝕刻停止層丨8具有相 當高的介電常數（7~8)，此將導致第1内連線3〇a以及第2内 連線之間的電容值（capacitance)增加，進而引起導線之 間具有較大的RC時間延遲（RC time delay)，並且影響元 件之傳輸效率。 ~ 有鑑於此，本發明的目的在於提供一種雙鑲嵌結構的 製作方法，其藉由去除部分高介電常數之蝕刻停止声， 降低内連線（導線）之間的電容值。 3 根據上述目的，本發明提供一種雙鑲嵌結構 法，適用於形成有金屬導線的半導體基底，包括 驟：（a)在上述半導體基底上依序形成—第i金屬間介電 層、蝕刻停止層；（b)選擇性去除上述蝕刻停止岸， 在上述金屬導線相對位置上方形成一第丨開口以 二 欲形成第1溝槽以及第2溝槽之間形成一第2開口；後/ 留的蝕刻停止層上方形成一第2金屬間介電層；c 去除上述第2金屬間介電層，以在上述第丨開口上祀 i溝槽以及與上述第i溝槽並列的第2溝槽；以及（二5. Description of the invention on page 4 (2) and etch the first oxide layer 16 ′, and then etch the first etch stop layer 14 to form a contact hole 28 exposing the metal wire 12, and at this time, the contact hole 28 and the first The trench 26a constitutes a double damascene structure dd. Immediately after, the photoresist mask was removed. Finally, please refer to the first F 圊, and fill the double damascene structure dd and the second trench 26b with a metal material 'to form the first interconnection 30a and the second interconnection 30b, respectively. However, 'the second etch stop layer 8 composed of silicon nitride or the like has a relatively high dielectric constant (7 to 8), which will cause the capacitance between the first interconnect 30a and the second interconnect. The increased value (capacitance) causes a larger RC time delay between the wires and affects the transmission efficiency of the component. In view of this, an object of the present invention is to provide a manufacturing method of a dual damascene structure, which reduces the capacitance value between interconnects (wires) by removing part of the high dielectric constant etching stop sound. 3 According to the above object, the present invention provides a dual damascene structure method, which is suitable for forming a semiconductor substrate with metal wires, including the steps: (a) sequentially forming the i-intermetal dielectric layer and an etch stop layer on the semiconductor substrate; ; (B) selectively removing the above-mentioned etching stop shore, forming a first opening above the relative position of the metal wire to form a second opening between the second trench to be formed and a second opening between the second trench; post / remaining etching Forming a second intermetal dielectric layer above the stop layer; c removing the second intermetal dielectric layer to target the i trench and the second trench juxtaposed with the i th trench on the first opening; and (two
五、發明說明（3) 述第1開口以及上述第1溝槽蝕刻上述第1金屬間介電層以 形成一露出上述金屬導線的接觸孔’而構成一雙鑲嵌結 構。 再者，上述雙鑲嵌結構的製作方法’其中鞋刻停止層 的介電常數（k)於大於第1金屬間介電層以及第2金屬間介 電層的介電常數。再者，上述第1金屬間介電層以及上述 第2金屬間介電層係氧化層。而上述蝕刻停止層係厚度介 於500〜1500埃之間的氣化碎層或是氮氧矽化合物層。 並且，形成雙鑲嵌結構之後，更包括下列步驟：在上 述雙鑲嵌結構以及上述第2溝槽之内填入金屬材料以形成 第1内連線以及第2内連線。 為了讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： 第1A~第1F圖為’利用習知技術形成雙鑲嵌結構的製 造流程剖面示意圖。 第2A〜第2F圖為’根據本發明實施例形成雙鑲嵌結構 的製造流程剖面示意圖。 符號之說明 100〜半導體基底。 102〜金屬導線。 104〜第1餘刻停止層。 106〜第1金屬間介電層。5. Description of the invention (3) The first opening and the first trench etch the first intermetal dielectric layer to form a contact hole that exposes the metal wire to form a double damascene structure. Furthermore, in the above method of manufacturing a dual mosaic structure, the dielectric constant (k) of the shoe-stop layer is greater than that of the first intermetal dielectric layer and the second intermetal dielectric layer. The first intermetallic dielectric layer and the second intermetallic dielectric layer are oxide layers. The etch stop layer is a gasification fragment layer or a silicon oxynitride layer having a thickness between 500 and 1500 angstroms. In addition, after forming the dual damascene structure, the method further includes the following steps: filling a metal material into the dual damascene structure and the second trench to form a first interconnector and a second interconnector. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: 1A ~ 1F The picture is a schematic cross-section of the manufacturing process of forming a dual mosaic structure by using a conventional technique. 2A to 2F are schematic sectional views of a manufacturing process for forming a dual mosaic structure according to an embodiment of the present invention. Explanation of symbols 100 to semiconductor substrate. 102 ~ Metal wire. 104 ~ 1st stop layer. 106 to the first intermetal dielectric layer.
五、發明說明（4) -- 108~第2蝕刻停止層D 110a〜第1開口 。 110b〜第2開口 。 112~第2金屬間介電層。 1 1 4〜光阻圖案（蝕刻溝槽用）。 116a〜第1溝槽。 116b〜第2溝槽。 1 2 0 ~接觸孔。 DD〜雙鑲嵌結構。 1 22a〜第1内連線。 122b〜第2内連線。 實施例 以下利用第2A〜2F圖，以更詳細地說明本發明之實施 例0 首先’清參照第2 A圖’此剖面圖顯示形成有例如銅 (Cu)、鋁銅（A卜Cu)合金等材料構成的金屬導線1〇2之半導 體C例如單晶矽）基底1 〇 〇。半導體基底丨〇 〇上方依序形成有 第1蝕刻停止層1 〇 4 (視需要）、第1金屬間介電層 (inter-metal dielectric ; IMEO106、第2 蝕刻停止層 1 08。上述各層皆以傳統製程形成，其中上述第1金屬間介 電層106為介電常數（dielectric constant)大約4的氧化 層（TE0S、PETE0S)等，也可以選自其他低介電常數的摻氟 矽玻璃（FSG)、含有氫矽酸鹽類（HSQ)、含有甲基矽酸鹽類 (MSQ)等材料。而第1蝕刻停止層1〇4、第2蝕刻停止層1〇8V. Description of the invention (4)-108 to the second etch stop layer D 110a to the first opening. 110b ~ 2nd opening. 112 to the second intermetal dielectric layer. 1 1 4 to photoresist pattern (for trench etching). 116a to the first groove. 116b to the second groove. 1 2 0 ~ contact hole. DD ~ Double mosaic structure. 1 22a to the first interconnector. 122b to the second interconnection. EXAMPLES In the following, Figures 2A to 2F are used to explain Example 0 of the present invention in more detail. First, "clearly refer to Figure 2A" This cross-sectional view shows the formation of, for example, copper (Cu), aluminum copper (Ab) The semiconductor C of the metal wire 102 made of other materials (such as single crystal silicon) substrate 100. On the semiconductor substrate, a first etch stop layer 104 (optionally), a first inter-metal dielectric (IMEO106, and a second etch stop layer 108) are sequentially formed on the semiconductor substrate. The above layers are all formed by Formed by a conventional process, in which the first intermetallic dielectric layer 106 is an oxide layer (TE0S, PETE0S) having a dielectric constant of about 4, and can also be selected from other low-dielectric-constant fluorine-doped silicon glass (FSG) ), Containing hydrogen silicates (HSQ), methyl silicates (MSQ) and other materials. The first etch stop layer 104 and the second etch stop layer 108
423 T 五、發明說明（5) 例如為’利用化學氣相沈積法在適當的反應氣體存在下形 成的氮化石夕層（SisN4)、或是氮氧化合物層（Si〇xNy)，並 且’其厚度大約介於500〜1500埃之間。上述氮化矽層以及 氮氧化合物在氡化層或玻璃層蝕刻時，具有良好的阻擋能 力’然而其介電常數高達7〜8左右。 接著，請參照第2B圖’利用傳統的微影技術 (photolithography)形成光阻圖案（圖未顯示），然後以上 述光阻圖案為蝕刻罩幕，並且利用蝕刻步驟以去除未被光 阻圖案覆蓋的第2#刻停止層1〇8，以在上述金屬導線1〇2 相對位置上方形成一第1開口 11 〇 a以及在後續欲形成第1溝 槽（trench)以及第2溝槽之間形成一第2開口 ii〇b。其次， 去除上述光阻圖案。 然後’請參照第2 C圖，在殘留的蝕刻停止層丨〇 8上方 形成一第2金屬間介電層112，其可以與上述第1金屬間介 電層106的材料相同，為介電常數（dielectric cQnstant) 大約4的氧化層（TEOS、PETE0S)，或是由其他低介電常數 (low k)的摻氟妙坡璃（FSG)、含有氫石夕酸鹽類（hsq)、含 有甲基矽酸鹽類USQ)等材料構成。 其次，請參照第2D圖，符號11 4為利用傳統的微影製 程進行光阻塗佈（photoresist coating)、烘烤、曝光等 步驟所形成的光阻圖案，利用上述光阻圖案丨丨4當作蝕刻 罩幕’並且進行非等向蝕刻步驟，以在上述第1開口 11〇a 上方形成第1溝槽116a以及與上述第1溝槽〗16&並列的第2 溝槽116b。423 T V. Description of the invention (5) For example, 'It is a nitride stone layer (SisN4) or a nitrogen oxide compound layer (SiOxNy) formed by chemical vapor deposition in the presence of an appropriate reaction gas, and' its The thickness is between 500 and 1500 Angstroms. The above silicon nitride layer and the oxynitride compound have a good barrier ability when the halide layer or the glass layer is etched ', but their dielectric constants are as high as about 7-8. Then, please refer to FIG. 2B, using a conventional photolithography to form a photoresist pattern (not shown), and then use the photoresist pattern as an etching mask, and use an etching step to remove the photoresist pattern that is not covered No. 2 etch stop layer 108, to form a first opening 11a above the relative position of the metal wire 102, and to form a first trench between the subsequent trench and the second trench A second opening ii〇b. Next, the photoresist pattern is removed. Then, referring to FIG. 2C, a second intermetal dielectric layer 112 is formed over the remaining etch stop layer 08. The second intermetal dielectric layer 112 may be the same material as the first intermetal dielectric layer 106 and has a dielectric constant. (Dielectric cQnstant) Approximately 4 oxide layers (TEOS, PETE0S), or other low-k-doped fluorine-doped Miao Po glass (FSG), containing hydrogen oxalates (hsq), containing formazan Based silicates (USQ). Secondly, please refer to FIG. 2D. Symbol 11 is a photoresist pattern formed by photoresist coating, baking, and exposure using a conventional lithography process. The above photoresist pattern is used. An etching mask is used and an anisotropic etching step is performed to form a first trench 116a and a second trench 116b juxtaposed with the first trench 16 & above the first opening 110a.