TWI223872B - Manufacturing method of dual damascene structure - Google Patents

Abstract

A manufacturing method of dual damascene structure is disclosed in the present invention, in which alkali-dissolvable or water-dissolvable hole-filling material is filled into the via-hole before conducting the step of trench etching. The hole-filling material is directly developed to a certain height through the use of alkaline developer or deionized water. After that, a baking process is conducted to generate an inter-chain reaction so as to define photoresist of the trench and prevent it from generating mixture. The inner wall of the via hole and the interconnection on the substrate are protected so as to avoid the generation of bad via hole profile and punch-through caused by the damage due to etching process. Thus, it is capable of preventing fence effect when conducting the trench-etching step.

Description

1223872

FIELD OF THE INVENTION The present invention relates to a semiconductor process technology, particularly a method for manufacturing a dual damascene structure, which avoids contamination of components by the occurrence of fence effects during the definition of etching trenches and the occurrence of interlayers. Poor hole contours and erosion damage the interconnect and simplify the process steps. Relevant technical description: In the traditional interconnect process, because the via hole structure and the wire pattern are made separately, it requires separate deposition and definition maps and procedures to make the entire process step Extremely complicated, in the current trend of increasingly complicated circuit design, it will increase production time and cost, which is not conducive to the application on the production line. In order to overcome the above difficulties, a dual damascene interconnect structure is currently developed. A trench having a via hole and an interconnect pattern is first produced on the dielectric layer of the substrate, and then a The conductive layer fills the via hole and the interconnect pattern trenches, and simultaneously produces a contact plug and an interconnect structure to achieve the effect of simplifying the process steps. f for further explanation, the following will be combined with the schematic cross-section diagrams from la to lc, to understand the manufacturing method of the duai damascene structure. Referring to FIG. 1a, a semiconductor substrate 10 is provided first, and a metal interconnect (not shown), such as copper or an inscription, is formed thereon, and then an etching stop layer (stop layer) is formed according to a conventional semiconductor process. ) 1 2 'To isolate the interconnects' Next a dielectric layer 14 is formed. Next, the etch dielectric layer is defined by the conventional lithography #etch process to form a via hole.

1223872 V. Description of the invention (2) 14a. Subsequently, a bottom anti-reflection coating (BARC) 16 is coated on the dielectric layer 14 and the via 14 & to prevent the standing wave effect and the via hole when the trench is subsequently defined 丨4a Poor inner wall contours and excessive penetration of the termination layer 12 cause damage to internal wiring. The above-mentioned method is a full filling (ful 1-f i Π ing) method, that is, filling the BARC 16 in the via hole 14a. The other method is a half_fining method, that is, a half-height BARC 16 (not shown) is filled in the via hole 14a. However, it will cause the same problem as the full-fill method, so only the full-fill method will be used for explanation. Next, referring to FIG. 1b, a photolithography process is used to form a patterned photoresist 18 on the dielectric layer 4 and form an opening 18a to define a trench. Finally, referring to FIG. 1c, the exposed bottom anti-reflection layer 16 is etched by an etching process to form a trench 141 above the via 14a), and the patterned photoresist layer 18 is removed to form a dual damascene structure. . However, when the trench is left to form the trench 14b, the etching rate of the bottom anti-reflection layer 16 of the via hole 14a is slower than that of the dielectric layer 14. Therefore, when the trench 14b is formed, A fence effect occurs in the via hole 14a. That is, a fence 16a formed by the bottom anti-reflection layer 16 is formed around the opening of the via hole i4a, which is likely to cause contamination and affect the particles when the etching stop layer 12 is subsequently removed. Electrical characteristics of components. In order to improve the above-mentioned problem, another method is to replace the bottom anti-reflection layer with an i-1 i n e photoresist material. The manufacturing method of the conventional dual-inlay structure will be described below with reference to Figures 2a to 2d. Here, "the same material or structure as in Fig. 1" indicates the same reference. Please refer to section 2 a ′ for the same with the formed metal

0503-6829TWF; TSMC2001 -0764; s p i n.p t d p. 5 1223872

An interconnect (not shown) is a semiconductor substrate 10, and an etching stop layer 12, a dielectric layer 14, and a dielectric anti-reflection layer (dielectric ARC, DARC) 15 are sequentially formed on the substrate 10. Next, the dielectric & reflective layer 15 and the dielectric layer 14 are etched to form a dielectric hole 14a. Subsequently, an i-line photoresist layer 26 is coated on the dielectric anti-reflection layer 15 and the interlayer hole i4a, and an exposure step is performed. Its role is to protect the interlayer hole 14a and interconnects. Then referring to FIG. 2b, the photoresist layer 26 is etched by an oxygen plasma to leave a photoresist layer 26 having a predetermined height in the via hole 14a. Next, please refer to the figure 2 (;), through the photolithography process to form a patterned photoresist 18 on the dielectric layer and form an opening 8a to define the trench. J Finally refer to the second Figure d. The exposed dielectric anti-reflection layer 5 and the underlying dielectric layer 14 'are etched to form a trench Hb above the dielectric hole 14a, and the patterned photoresist layer 18 is removed to form a dual damascene structure. Although the above-mentioned problem of the fence effect is solved, it is still necessary to etch the main-Hne photoresist 26 and increase the process steps, which cannot effectively reduce the manufacturing cost and improve the production capacity. In view of this, the present invention provides a method for manufacturing a dual mosaic structure. Eight by filling the groove rhyme rule, fill in a m-hole that is soluble or water-soluble, to prevent the fence effect and protect the inner wall contour and connection of the interlayer hole, while simplifying the process steps. Φ Summary of the invention: The purpose of the present invention is to provide an alkali-soluble or water-soluble hole filling material element causing particulate pollution. The manufacturing method of the dual mosaic structure, 'to avoid the fence effect

^^ 6/2 V. Description of the invention (4) The method is to provide a kind of dual-mosaic structure manufacturing method to make the component = protect the internal connection and the inner wall of the interlayer hole to prevent the occurrence of the method, 2 ;;:. :: It is to provide the manufacturing ability of a double mosaic structure. In order to reduce the manufacturing cost and provide the production capacity according to the above-mentioned M ^ method, including the following; ::; "Ming provides a manufacturing termination layer with a dual damascene structure and a dielectric acoustic i-sequentially on the semiconductor substrate Form an etched surface to form a dielectric hole f dielectric layer to expose the surface of the etch stop layer; Develop this dry layer " fill a hole filling material on the electrical layer and inside the dielectric hole in the dielectric hole The internal formation has a predetermined height response; and the definition of the remaining time eight = enter the lamp and a baking process' to generate an interlinking groove to form a double inlaid two: 丄 1 layer: to form above the via hole-the trench also includes the removal of the axe ΪΪ The manufacturing method of the dual mosaic structure, the material is a step of a water-soluble two-hole material. Among them, the above-mentioned hole-filling phenethyl group: a poly-r-based propionate copolymer, a poly-based base, and a worm The polyimide of lice roots and chitosan L also use 'developing developer or deionized two: to develop. In addition, the time of baking treatment is at 30 = the temperature at which the lamp is baked at 10 (TC to 35 (TC) The scope of the knife knife and the simple description of the drying pattern: In order to make the invention above Objects, features, and advantages can be more easily 0503-6829TWF; TSMC2001 -0764; s p i n.p t d p 71,223,872

V. Description of the invention (5) Understand 'A preferred embodiment is given below, and in accordance with the accompanying drawings, the detailed description is as follows: " " The first 1 to 1C diagrams show the conventional double inlay structure Sectional schematic diagram of the manufacturing method; Figures 2a to 2d are schematic cross-sectional diagrams of another conventional dual-mosaic manufacturing method; Figures 3a to 3f are schematic diagrams of the dual-mosaic structure manufacturing according to an embodiment of the present invention Method cross-section diagram. [Symbol description] ❿ 10, 30 ~ semiconductor substrate; 12, 32 ~ etch stop layer; 14, 34 ~ dielectric layer; 14a, 34a ~ via hole; 14b, 34b ~ trench; 15, 36 ~ dielectric reactance Reflective layer; 16 ~ bottom anti-reflection layer; 16a ~ fence; 18, 38, 42 ~ photoresist layer; dust 18a, 38a, 42a ~ opening; 26 ~ i-line photoresist. Detailed description of the preferred embodiment: The double mosaic structure according to the embodiment of the present invention will be described below with reference to Figures 3a to 3f.

1223872 V. Manufacturing method of invention description (6). Shi Qiqi: Please refer to FIG. 33 first to provide a semiconductor substrate 30. For example, ―base j‖ has components and interconnections formed on it. To simplify the diagram *: Ca n’t draw-flatten the substrate. Next, a money = stop layer 32 is sequentially formed on the substrate 3 ′, such as a silicon nitride layer, a dielectric layer 34, example two; a low-dielectric material layer ', and a dielectric anti-reflection layer (hall) 36. . This; or termination layer 32 is used to isolate interconnects and lines (not shown), and the dielectric reactance 36 is used to prevent standing wave effects in subsequent lithography processes. Then, the conventional lithography process forms a patterned photoresist on the dielectric anti-reflection layer 36, and forms an opening 38a to define the via hole. 9 Next, referring to FIG. 3b, the surface of the dielectric anti-reflection layer 36 and the underlying dielectric layer 34 are etched to expose the surface of the etch stop layer 32 to form a dielectric hole 34a. Next, a hole-filling material 40 is coated on the dielectric anti-reflection layer 36 and the inside of the via 34a. In this embodiment, the hole filling material 40 is a water-soluble or water-soluble barrier agent. It has the characteristics of development and dissolution without going through the exposure step, such as polyacrylate copolymers (polyol copolymers), polymethacrylate copolymers (polymerthacrylate copolymers), and polyhydroxystyrene copolymers. (Polyhydroxystyrene copolymer), hydroxyl-containing polyimides (polyimides) and hydroxide-containing polyimide (polyimides). Next, the cavity filling material 40 is developed back with an ocular developer, such as tetramethylammonium hydroxide (TMAH) or delete ion water (DIW), so as to pass through the interlayer. Cavity filling material having a predetermined height is formed in the hole 34a

1223872 V. Description of the invention (7) The height of the material 40 ′ is controlled within the range of 1/4 to 1 times the depth of the via 34 by the development time, as shown in Figure 3 (:). Next, Please still refer to FIG. 3c. After completing the above developing step, a baking process is performed on the remaining hole filling material 40, so that the hole filling material 40 has a crosslinking reaction. This step is Prevent the hole filling material 40. In the subsequent definition of the remaining trenches, unnecessary mixed reactions with the photoresist, protect the contour of the inner wall of the via 34a, and prevent the termination layer 32 from being eroded to damage the interconnects. In this embodiment The baking temperature is controlled in the range of 100 ° C to 350 ° C and the baking time is controlled in the range of 30 seconds to 30 minutes. Next, please refer to FIG. 3d. A patterned photoresist layer 42 is formed on the antireflection layer 36 and an opening 42 is formed to define the trench. After the Pic, please refer to FIG. 3e, and use the patterned photoresist layer 42 as a mask. The etched dielectric anti-reflection layer 36 and the underlying dielectric layer 3 4 are formed to form over the dielectric hole 34a. Trench 34b, and remove the patterned photoresist layer 42 to form a dual damascene structure. Finally, please refer to FIG. 3f, after forming the damascene structure, remove the hole filling material 40 and the exposed etching in the via 34a. The termination layer 32 is exposed on the surface of the substrate 30 so as to facilitate the subsequent process of filling the metal plugs. According to the dual damascene manufacturing method of the present invention, the above-mentioned hole filling material 4 can be developed and dissolved without exposure, so compared with As for the conventional technique using i — i ne photoresist materials, the trench grooves can be directly defined after the hole-filling material has completed the cross-linking reaction. This eliminates the exposure step of the photoresist i-1 ine and the subsequent etching back to One

1223872 '— V. Description of the invention (8) Steps of a given height. Advantages (for example, anti ::, except that the same internal wiring as the use of 1ine photoresistor) at 1 o'clock, the fence effect and the protection of the inner wall of the via and the substrate and increase the production capacity of the process steps can be effective Reduction of manufacturing cost limitation ::: hair: f, the preferred embodiment is disclosed above, but it is not used by gods and sacrifice meat'a to be familiar with this skill, without departing from the spirit and fcM of the present invention, it can be used as Changes and retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.

Claims (1)

1223872 VI. Scope of patent application 1. A method of double-embedding a semiconductor layer; a method for manufacturing an embedded structure includes the following steps: an etching stop layer is sequentially formed on the substrate and a dielectric is formed to correspond to the return angle; Slot, borrow 2. Method, its steps. 3. Method, 4. Method, 5. Method, 6. Method, with its surname engraved with interstitial holes; the above-mentioned dielectric development of the above-mentioned hole-filling materials and the above-mentioned hole-filling with Yiyu are engraved to form a double application In addition, if you apply for the college, you also include if you apply for the above-mentioned eclipse, if you apply for the above-mentioned eclipse, if you apply for the above-mentioned mediation, if you apply for the above-mentioned filling, if you apply for the above-mentioned description on the dielectric layer, and for filling the hole material, the range of the dielectric inlaid profit is above The effective range is removed from the upper range and the upper range is terminated. The electric range is from the high range hole material. The upper limit range layer is exposed to the surface of the #etch stop layer, and the above-mentioned interlayer hole is coated with a hole-filling material. A step of forming a dielectric anti-reflection layer on the manufacturing dielectric layer with the predetermined row-baking process to generate a cross-linked anti-layer structure to form a trench above the dielectric hole of the dual damascene structure described in item 1. The manufacturing method of the double inlay structure described in item J; the step of filling the hole in the layered cavity. The manufacturing method of the dual damascene structure described in item = 1 is a silicon nitride layer. , The manufacturing method of the dual damascene structure described in item 1, a gasification layer or a layer of low dielectric material. The manufacturer of the double inlaid knot structure described in the above item is a flute factory, a water-soluble or alkali-soluble inhibitor. Manufacturer of the dual mosaic structure described in item 0503-6829TW; TSMC2001.〇764; spin.ptd 1223872 VI. Range of patent application / 8 The above-mentioned predetermined height is in the range of 1/4 to 1 times the depth of the above-mentioned via hole. 8 ^ The manufacturing method of the dual mosaic structure described in item 1 of the scope of the patent application '' /, wherein the baking time is in the range of 30 seconds to 30 minutes. ^ The manufacturer of the dual mosaic structure as described in item 1 of Shenqing's patent scope, '' wherein the baking temperature is in the range of 100 ° C to 350 ° C. , 10 · The manufacturing method of the dual mosaic structure as described in item 6 of Shenyan's patent scope * * The t-resistor is selected from one of the following groups: polyacrylate, polymethacrylate copolymer, Polyhydroxystyrene copolymer, polyimide with oxo radical and polyimide with hydroxide. 11, 11. The method of manufacturing a dual mosaic structure as described in item 6 of the Shen Jing patent scope ', wherein the hole filling material is developed back using an alkaline developer or deionized water. 4 rr history 0503-6829TWF; TSMC2001-0764; spin.ptd Page 13