1223813 玖、發明說明： 【發明所屬之技術領域】 本發明是關於一種低功率之靜態隨機存取記憶體單胞 (SRAM cell)，特別是指一種能以低功率方式寫入位元”0”於 5 記憶體單胞中的靜態隨機存取記憶體單胞。 【先前技術】 隨機存取記憶體（RAM) —般可分為動態隨機存取記憶體 (DRAM)與靜態隨機存取記憶體（以下簡稱SRAM)兩種，其 中由於SRAM毋需再充電恢復（refresh)動作，因此其存取速 10 度較快，常作為快取記憶體（cache memory)使用。 如圖1所示，一種以往具一寫入埠與一讀取埠的SRAM 單胞（cell)是由八個電晶體T1〜T8所構成，其中，電晶體 T1與電晶體T2是P通道金氧半場效電晶體（PMOS)，而電 晶體T3與電晶體T4則是η通道金氧半場效電晶體（NMOS) 15 。電晶體Τ1與電晶體Τ3是相互串聯在一起，即其汲極相 連而形成一節點D1，且其二者之閘極亦是相互連接，因此 構成了一個互補式金氧半（CMOS)反相器10。同理，電晶體 T2與電晶體T4亦構成一反相器20。 反相器10與反相器20是連接於一正電源（Vdd)與一接 20 地線（ground)之間，且二者是相互交叉連接，即其節點D1 、D2是各別與另一反相器之閘極連接在一起。上述兩個節 點Dl、D2的準位高低狀態即是用來表示儲存於記憶體單胞 中的資料位元狀態。 另外四個電晶體T5〜T8是所謂的存取電晶體，其中， 4 1223813 一組電晶體T5與T6是用來寫入資料，另一組電晶體T7與 電晶體Τ8是用來讀取資料，由於兩組電晶體在讀取及寫入 的狀態變化大致相同，故僅就電晶體Τ5、Τ6來說明資料寫 入的動作。 電晶體Τ5與Τ6之一端是連接於節點d 1、D2上，另 一端則連接於一正位元線（bitline)cl或一負位元線C2上， 並以一子元線（wordline)W連接於電晶體T5、T6之閘極上 。因此字元線W是用來控制電晶體Τ5、Τό之開/關，以決 定是否透過正、負位元線C1、C2來進行位元資料的寫入。 為達到快速的存取，在沒有任何寫入或讀取動作的狀 二、下正負位元線C1〜C4均會預先充電（precharge)至一 间準位。在寫入狀態時，例如寫入位元”丨，，，使正位元線以 維持一高準位狀態（Vdd)、負位元線C2放電至一低準位狀 ^因此田子元線W為高準位狀態時，即打開電晶體T5、 T6 ’進而關閉電晶體T3而打開電晶體T4，因此節點為 高準位狀態而節點D2為低準位狀態，即表示位元”丨，，已寫 入於記憶體單胞中。待寫入動作完成後，又再預充正、負 元線Cl、C2至一高準位。同理，當寫入位元，，〇，，後，節點 D1為低準位狀態而節點D2為高準位狀態。 在讀取狀態時，例如讀取位元”1”，正、負位元線C3、 C4皆預充至高準位狀態後，再使字元線R為高準位狀態， 因此打開電晶冑T7、T8，由於電晶體τ“匕時是打開而接 地，故負位兀線C4會經由電晶體Τ4放電而與正位元線〇 產生電位差，此時利用週邊電路（圖未示）來偵測，就能讀出 5 1223813 此位元。 5 10 15 、行寫入動作時，不 皆需將C1、C2 A中卜/所奴寫入之一貝料為，，0，，或τ， ’、 位兀線由高準位變為低準位（正、 負位7G線之準位互為反相束 )故§預充電壓時，由於需再壤 正、負位70線Cl、C2皆加1石丄 幵至向準位，故會消耗-定功碎 ，特別疋當所欲寫入的資料與 先的，，〇，，寫為，，1，，或由，，！，，寫為，\二5 %，例如由肩 Dl、D2的準位狀態，直全 . ^ ” ，、王電壓擺幅（swing)更會造成大量我 率的消耗。 ‘ 為了減^力率㈣耗㈣應高集積度及微型化的趨勢 ，以往提出了幾種減少功率消耗的方法。例如使用一半之 電壓擺幅來減少位⑽上電壓擺幅的變化性，但此種作注 往往會導致記憶體單胞的不穩定性。 另-種作法是如美國第6,459,611號專利案所示，利用 五個電晶體以及單一的位元線、字元線來進行資料的讀卑 與寫入’由於僅採單一的位元線，因此其功率消耗較以妇 八個電晶體型式為低，但是由於是採非對稱性之設計，赵 在寫入”1”時會遭遇相當的困難，因此其電路設計上的主邊 目的在於減少寫入”1”時之功率。1223813 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a low-power static random access memory single cell (SRAM cell), and particularly to a low-power way to write bits "0" Static random access memory cells in 5 memory cells. [Prior technology] Random access memory (RAM)-generally can be divided into dynamic random access memory (DRAM) and static random access memory (hereinafter referred to as SRAM), of which SRAM does not need to be recharged to recover ( refresh) action, so its access speed is 10 degrees faster, often used as cache memory (cache memory). As shown in FIG. 1, a conventional SRAM cell with a write port and a read port is composed of eight transistors T1 to T8. Among them, the transistor T1 and the transistor T2 are P-channel gold. Oxygen half field effect transistors (PMOS), while transistors T3 and T4 are n-channel metal oxide half field effect transistors (NMOS) 15. Transistor T1 and transistor T3 are connected in series with each other, that is, their drains are connected to form a node D1, and the gates of the two are also connected to each other, so a complementary metal-oxide-semiconductor (CMOS) inversion is formed.器 10。 10. Similarly, the transistor T2 and the transistor T4 also constitute an inverter 20. Inverter 10 and inverter 20 are connected between a positive power supply (Vdd) and a ground line connected to 20, and the two are cross-connected to each other, that is, their nodes D1 and D2 are each connected to another The gates of the inverters are connected together. The level of the two nodes D1 and D2 is used to indicate the state of the data bits stored in the memory cell. The other four transistors T5 ~ T8 are so-called access transistors. Among them, 4 1223813 a group of transistors T5 and T6 are used to write data, and another group of transistors T7 and transistor T8 are used to read data. Since the changes in the reading and writing states of the two sets of transistors are approximately the same, only the transistors T5 and T6 are used to describe the data writing operation. One end of the transistor T5 and T6 is connected to the nodes d1, D2, and the other end is connected to a positive bitline cl or a negative bitline C2, and a wordline W Connected to the gates of transistors T5 and T6. Therefore, the word line W is used to control the on / off of the transistors T5 and T6 to determine whether to write the bit data through the positive and negative bit lines C1 and C2. In order to achieve fast access, the lower positive and negative bit lines C1 ~ C4 will be precharged to a certain level in the state without any write or read action. In the writing state, for example, writing the bit ",", the positive bit line is maintained at a high level state (Vdd), and the negative bit line C2 is discharged to a low level. Therefore, Tian Ziyuan line W When it is in the high level state, the transistors T5 and T6 are turned on, and then the transistor T3 is turned off and the transistor T4 is turned on. Therefore, the node is in the high level state and the node D2 is in the low level state, which means that the bit is "丨," It has been written in the memory unit. After the writing operation is completed, the positive and negative element lines Cl and C2 are again precharged to a high level. Similarly, when the bit is written, 0, 0, the node D1 is in a low level state and the node D2 is in a high level state. When reading the state, for example, read bit "1", the positive and negative bit lines C3, C4 are precharged to the high level state, and then the word line R is set to the high level state, so the transistor is turned on. T7, T8, because the transistor τ is turned on and grounded, the negative potential line C4 will discharge through the transistor T4 to generate a potential difference with the positive bit line 0. At this time, peripheral circuits (not shown) are used to detect 5 1223813 can be read out. 5 10 15 When the row is written, it is not necessary to write one of the data in C1 and C2 A. The data is 0, 0, or τ, ', The bit line changed from high level to low level (the level of the positive and negative 7G lines are opposite to each other). Therefore, when pre-charging the voltage, the positive and negative 70 lines Cl, C2 are required. Add 1 stone to the standard level, so it will consume-fixed power is broken, especially when the data you want to write and the first ,, 0 ,, written as ,, 1 ,, or by ,,,,,,,,,, It is written as \ 25%. For example, the shoulders Dl and D2 are in the standard position, and they are full. ^ ", And the king voltage swing (swing) will cause a lot of consumption. ‘In order to reduce the power rate, power consumption, and trend of high integration and miniaturization, several methods have been proposed in the past to reduce power consumption. For example, using half the voltage swing to reduce the variability of the voltage swing on the bit, but this kind of note often leads to the instability of the memory cell. Another method is to use five transistors and a single bit line and word line to read and write data as shown in US Patent No. 6,459,611. Because only a single bit line is used, Its power consumption is lower than that of the eight transistor types, but due to the asymmetric design, Zhao will encounter considerable difficulties when writing "1", so the main purpose of his circuit design is to reduce writing Power when entering "1".
20 事實上，在快取記憶體的所存取的指令或資料中，其 位元，’0”所佔的比例遠大於位元，，丨，，的比例，例如^兑五〔20仰測試程式來實際測試，其位元，，〇，，所处^ 7U u所佔的比例約 莫佔整體資料之80%以上’故若能以較低功率的方气來寫 入”〇，，，則必然可以減少大量的功率消耗。 ” 6 1223813 【發明内容】 有鑑於以往記憶體單胞之缺點，因此本發明之目的在 於提供一種能以低功率方式寫入位元，，〇，，之靜態隨機存取記 憶體單胞。 5 &是’在—較佳實施例中，本發明之低功率之靜態隨 機存取記憶體單胞包含-第-反相器、-第二反相器、二 讀取電晶體、-開關電晶體，以及一寫入電晶體。 本發明將讀取與寫入的動作分開處理，即透過該讀取 1晶體來讀取資料’透過該寫入電晶體來寫入資料，並將 焦點放在由寫為時之動作，以降低寫人”G，，時的功率 消耗。 遠第-反相盗具有-對串接在—正電源與—接地線間 之互補式金氧半(CMOS)場效電晶體，該等場效電晶體間形 成有-第-節點。該第二反相器具有一連接於該正電源上 15 之拉昇（PUll_UP)電晶體，以及一與該拉昇電晶體相串接之拉 降(puU-down)電晶體，該拉昇電晶體與該拉降電晶體間形成 有一第二節點，該第二節點是與該等場效電晶體之間極相 連接，該拉昇電晶體與該拉降電晶體之閘極是與該第一節 點相連接。 2〇 各該讀取電晶體是分別經由一讀取位元線（bitline)與該 、第二節點其中之一相連接，該等讀取電晶體並能受 一讀取字元線（w〇rdline)之控制而開/關，以控制該等讀取位 元線與該等節點導通與否。 該開關電晶體是與該第二反相器相連接，用以控制該 7 1223813 第二反相器與該接地線相導接與否。該寫入電晶體是經由 一寫入位元線（bitline)與該第二節點相連接，該寫入電晶體 並能受一寫入字元線（wordline)之控制而開/關，以控制該寫 入位元線與該第二節點導通與否。 因此，依據上述架構，本發明亦提供一種以低功率方 式寫入位元0於一記憶體單胞中的方法，即是A)提供一與 該第二反相器之該節點相導接之寫入位元線，並B)將該寫 入位元線預充電壓至一預定準位，c)同時阻斷該第二反相 益與該接地線間之電性連接，D)最後在不改變該寫入位元 線之準位狀態下，導通該寫入位元線與該第二反相器之該 節點，使位元”0”被寫入於該記憶體單胞中。 因此，由於在寫入，，〇，，時，該寫入位元線之準位狀態不 而改變，故減少了大量的功率消耗，更佳的是，由於該第 一反相器與該接地線間之路徑已被阻斷，因此該第二反相 器之該節點的電壓可以輕易地被拉昇至高準位。由於程式 碼（包含指令、資料等）中，出現”0，，的比例甚高，因此本發 明可以有效地大幅減少記憶體在執行寫入動作時的功率消 耗。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效’在 以下配合參考圖式之—第—較佳實施例與一第二較佳實施 例的詳細說明[將可清楚的明白。要先說明的是，在第 -、第二實施例中相同的元件，是以相同的標號來表示。 參閱圖2,本發明低率功之靜態隨機存取記憶體單胞之 8 第一較佳實施例主要包含了一第一反相器丨、一第二反相器 2、一開關電晶體N3、二讀取電晶體N4、N5，以及一寫入 電晶體N6。 每一反相器1、2是由相互串接之一 p型場效電晶體ρι 、P2以及一 N型場效電晶體N1、N2所構成，且上下兩個 互補式電晶體間形成有一節點A、B。兩個反相器丨、2並 是相互父又對接，即第一反相器1之節點A是與電晶體N2 、P2之閘極相連接，而第二反相器2之節點b則是與電晶 體Nl、P1之閘極相連接。 電晶體PI、P2之源極是與正電源（Vdd)連接，因此是 作為拉昇（Pull-up)電晶體，而電晶體N1之源極則是接地 ，以作為一拉降（pull down)電晶體。特別是，本實施例中， 第二反相器2之拉降電晶體N2並不直接接地，而是透過一 開關電晶體N3再行接地，開關電晶體N3之閘極並連接於 一寫入選擇線400上，其作用將於下文中再行詳述。 二讀取電晶體N4、N5，其作用與習知技術中之電晶體 T5 Τ6相類似，惟其功能僅在進行資料的讀取，並不經由 此等電晶豸Ν4、Ν5進行資料寫入的動作。讀取電晶體m 之一端是連接於節點Α上，另一端則是連接於一第一讀取 位元線（bitline)11。相同地，節點B是藉由讀取電晶體奶 /、第一"貝取位元線12相連接。且讀取電晶體N4、N5 之閘極是共同連接於一讀取字元線（w〇rdlin^2⑻上，因此 讀取字it線200上電壓準位高低可以控制讀取電晶體似、 N5之開啟或關閉，使得節點A、B與第一、第二讀取位元 9 線11、12相導通，以進行資料的讀取。 寫入電晶體N6之一端亦與第二節點B相連接，惟其另 一，是與一寫入位元線15相連接，且寫入電晶體N6 :閘 ，疋連接於-寫入字元線綱i，能受寫入字元線3⑻上 f壓準位之高低而開啟或關閉，因此欲寫入資料至記憶體 單胞中時，是透過寫入電晶體N6將寫入位元線15上^次 料寫入於其中。 貝 乂特別強調的是寫入字元線3〇〇與寫入選擇線400的關 係，參閱圖3,此二者之準位高低在任一狀態下是互為反相 而且寫入選擇線400的準位變化必須先行於寫入字元線 3〇〇的準位變化，換言之，由週邊電路（解碼器3)發出的寫 入字凡線信號，必須先經一反向器4產生寫入選擇線之信 號，再經一反向器5還原原來的寫入字元線信號。 本發明的讀取動作，是由控制讀取字元線2〇〇、讀取位 元線11、12，以及寫入選擇線400來達成，而寫入動作則 疋控制寫入字元線300、寫入位元線丨5，以及寫入選擇線 400來達成，即把讀取、寫入動作分開處理，以下將就資料 的讀取與寫入動作分別加以說明： 讀取模式 參閱圖4，在讀取模式下，是使得寫入字元線3〇〇為一 低準位狀態，（此隱含寫入選擇線400為一高準位狀態），所 以打開了開關電晶體N3並關閉了寫入電晶體N6。圖式中 被關閉的電晶體N6是以虛線來表示。 換言之，由於寫入電晶體N6被關閉後，寫入位元線15 10 1223813 自然無法產生作用。由於開關電晶體N 3處於開啟狀態，電 晶體N2透過電晶體N3被接地，此時其整體結構等效於以 往之記憶體單胞，因此能夠透過讀取電晶體N5、N6來讀取 已儲存於記憶體單胞節點A、B上的資料，由於其讀取動作 5 與以往的記憶體單胞相同，故不再贅述。 2.窵入模式 參閱圖5，在寫入模式下，讀取字元線2〇〇為一低準位 狀恶’因此關閉了項取電晶體N4與N5，接著再使寫入字 元線300為咼準位狀態以打開寫入電晶體N6，即能使得寫 10 入位元線15與苐^一節點B相導通，以便將欲寫入之資料寫 入於§己憶體單胞中。如前所述’在寫入字元線3〇〇轉變為 高準位之前，寫入選擇線400已先行轉變為低準位狀態， 因此關閉了開關電晶體N3，故電晶體N2之源極此時並不 接地。 15 由於寫入資料時的動作與記憶體單胞中先前儲存的資 料（位元）狀態有關，因此分就下述兩個情況加以說明： ⑴寫入”1” 寫入”1”的可能情況有兩種，一種是記憶體單胞中先前 儲存的資料為” 1 ”，另一種情況則是儲存有，，〇，，。換言之，會 20 將記憶體單胞由”1”寫入為”1”，或者由，，0，，寫入為”1”。由於 前者（1—1)在寫入前後的狀態相同，各電晶體之狀態並未發 生變化，因此僅就後者加以說明。 將原先0寫入為1 ’必需將原先兩準位之節點B拉降 到低準位’而原先低準位之節點A則必需拉昇至高準位， 11 1223813 才旎完成貧料”1”的寫入。因此作法是當寫入位元線15被預 充電壓完畢後，再改變寫入位元線丨5至一低準位（約〇v)， 欠在寫入電θ曰體N6被開啟後，節點b會被放電（discharge) ，即讓流經電晶體P2之電流能通過節點B後流至寫入位元 5 線15上，因此節點B即成為低準位。 由於節點B為低準位，故連帶使得電晶體Ν1、ρι之閘 極為低準位，因此關閉了電晶體N1而開啟電晶體ρι，使 得節點A成為高準位，完成，，丨，，的寫入。 (2)寫入”〇” 1〇 寫入”〇”的可能情況亦有兩種，一種是需將記憶體單胞 由”〇”寫入為”0’’，另一種是由”1，，寫入為，，0，，。此處亦僅就後 者加以說明。 將原先的”1”寫入為”〇”，必需將原先低準位之節點B拉 昇到南準位，而原先高準位之節點A則必需拉降至低準位 15 ，因此作法為當寫入位元線15已被預充至高準位後，讓寫 入位兀線15維持在高準位狀態，待寫入電晶體N6被開啟 後，節點B即會被充電。 由此可知，寫入”〇”前，寫入位元線丨5之狀態並不需要 加以改變（與預充後相同，皆維持在高準位），因此可以大幅 20 減少寫入〇時之功率消耗，特別是，在寫入電晶體Νό被 開啟後’雖原先郎點Β為低準位，但由於開關電晶體Ν3在 吾人進行寫入動作前已被關閉，因此節點Β連接到地之線 路已被切斷，換言之，節點Β準位可被輕易地拉昇至高準 位，因此當寫入”〇”之動作完成後，對寫入位元線15再進行 12 5 預充擺幅大為降低，降低了寫入，，〇，，時的功率消耗。 門搞或：即點B已是高準位，故連帶使得電晶體N1、P1之 閘極為向準位，因此打曰 電日日體N1而關閉了電晶體ρι ’使㈣，點A成為低狗立，完成”】，，的寫入。 ^下表所不為本發明與傳統之隨機存取記憶體單胞，以 —丁串接128個單胞為一基本單位，使用π·(台積電）公 5 _35//m ，以HSPICE進行模擬測試後，所得各寫 入資斜夕肋能从a、七、·丨…▲ ^ ^ 4.92E-01 — -~~-—— --- 由表中可以得知，本發明在寫入”1，，時 以往之記憶體相差無幾，然則在寫入”〇，，時 體N3阻斷了接地路徑，因此在寫入，，0，，時 電壓準位幾乎沒有改變，其消耗功率之減少量可達97% ^ 上0 寫入狀態變化 ~—-—-___ 岁’’1”寫為，’〇 由”〇”寫為”〇” 由”1”寫為”1” 由寫為，，1 傳統SRAM 座^率消耗（Mwl 4.65E-01 4.37E-01 —-------- 4.35E-01 适i消耗（mW' 1.30E-02 ^17E-03 4.20E-01 —-— 4.64E-01 功率減少 97.21% 98.82% ---—-- 3^50%^ 5^70%^ 其功率消耗與 由於開關電晶 寫入位元線之 15 此外，由於本發明是採非對稱性之電路設計，因此在 其穩度度（靜態雜訊邊際，static n〇ise margin)上較以往的記 憶體單胞稍差，惟此點可以調整電晶體N2與電晶體N3之 寬長比值（W/L ratio)等其它製程參數來作適當補償，並不影 響本發明實際運作時之效能。 參閱圖6,所示者為本發明之第二較佳實施例，與第一 13 1223813 5 較佳實施例不同之處主要在於：第-較佳實施例所述乃〆 具有一寫入埠（_ P°rt)與—讀取埠㈣Pern)之記憶體單 胞，即其寫入與讀取動作的執行是透過不同的位元線來進 灯而本實她例所指乃是一寫入/讀取谭之記憶體單胞態樣 ，即其寫人與讀取之動作是經由相同的位元線18來進行。 本例中，其電路配置與第 僅具有一位元線18，且僅需單 一較佳實施例之差異處在於 一的讀取電晶體N5，此讀取 10 電曰曰體N5之端並與寫入電晶體N6共同連接於位元線^ 8 上，其餘元件1其動作原^里由於與前述相同，&不再資述 ，以下僅就其讀取與寫入動作作一概述。20 In fact, in the instructions or data accessed by the cache memory, the proportion of bits, '0' is much larger than the proportion of bits, ,,,,, for example, ^ to five [20 Yang test The program comes to the actual test, the bit, 〇 ,, where ^ 7U u accounts for about more than 80% of the overall data 'so if it can be written at a lower power, "0 ,, then Can certainly reduce a lot of power consumption. "6 1223813 [Summary of the invention] In view of the shortcomings of the previous memory cells, the purpose of the present invention is to provide a static random access memory cell that can write bits, 0, and 0 in a low power manner. 5 & Yes' In a preferred embodiment, the low-power static random access memory unit cell of the present invention includes a first inverter, a second inverter, a second reading transistor, and a switching circuit. The crystal and a writing transistor. The present invention separates the reading and writing actions, that is, reading data through the reading 1 crystal, 'writing data through the writing transistor, and focusing on The action of writing time is to reduce the power consumption of the writing person "G,". The far-inverter has a complementary metal-oxide-semiconductor (CMOS) field-effect transistor connected in series between the —positive power supply and —the ground wire. These field-effect transistors form a -first-node. The second inverter has a pull-up (PUll_UP) transistor connected to the positive power supply, and a puU-down transistor connected in series with the pull-up transistor. The pull-up transistor A second node is formed between the pull-down transistor and the field-effect transistor, and the gate of the pull-up transistor and the pull-down transistor are connected to the first node. The nodes are connected. 2 Each of the read transistors is connected to one of the and the second node via a read bitline, and the read transistors can be received by a read word line (wo). rdline) control to turn on or off the read bit lines and the nodes. The switching transistor is connected to the second inverter to control whether the 7 1223813 second inverter is connected to the ground line or not. The writing transistor is connected to the second node via a writing bitline, and the writing transistor can be turned on / off by the control of a writing wordline to control Whether the write bit line is conductive with the second node. Therefore, according to the above architecture, the present invention also provides a method for writing bit 0 into a memory cell in a low power manner, that is, A) providing a connection to the node of the second inverter Write the bit line, and B) precharge the write bit line to a predetermined level, c) simultaneously block the electrical connection between the second inverter and the ground line, and D) finally Without changing the standard state of the write bit line, the write bit line and the node of the second inverter are turned on, so that the bit “0” is written in the memory cell. Therefore, since the level state of the write bit line does not change at the time of writing ,, 0 ,,, a large amount of power consumption is reduced, and more preferably, because the first inverter and the ground The path between the lines has been blocked, so the voltage at the node of the second inverter can be easily pulled up to a high level. Because the proportion of "0" appears in the code (including instructions, data, etc.), the present invention can effectively reduce the power consumption of the memory when performing a write operation. [Embodiment] Related to the present invention The foregoing and other technical contents, features, and effects are described in detail below with reference to the drawings—the first preferred embodiment and a detailed description of a second preferred embodiment [will be clearly understood. What should be explained first is that -The same elements in the second embodiment are denoted by the same reference numerals. Referring to FIG. 2, the first embodiment of the static random access memory single cell of the low rate power of the present invention mainly includes a first An inverter 丨, a second inverter 2, a switching transistor N3, two reading transistors N4, N5, and a writing transistor N6. Each inverter 1, 2 is connected in series with each other. One p-type field-effect transistor ρ, P2 and one N-type field-effect transistor N1, N2, and a node A, B is formed between the upper and lower complementary transistors. The two inverters 丨, 2 and Are mutually parent and docked, that is, node A of the first inverter 1 is The gates of the crystals N2 and P2 are connected, and the node b of the second inverter 2 is connected to the gates of the transistors N1 and P1. The sources of the transistors PI and P2 are connected to the positive power supply (Vdd) Therefore, it is used as a pull-up transistor, and the source of the transistor N1 is grounded as a pull-down transistor. In particular, in this embodiment, the second inverter The pull-down transistor N2 of 2 is not directly grounded, but is grounded through a switching transistor N3. The gate of the switching transistor N3 is connected to a write selection line 400, and its role will be performed again in the following. In detail, the second reading transistor N4, N5 has the same function as the transistors T5 and T6 in the conventional technology, but its function is only for reading data, and does not pass data through these transistors N4 and N5. Write operation. One end of the read transistor m is connected to node A, and the other end is connected to a first read bitline 11. Similarly, node B is used to read the transistor The milk /, first " shell bit line 12 is connected. And the gates of the read transistors N4 and N5 are connected in common. Take the word line (w0rdlin ^ 2⑻), so reading the voltage level on the word it line 200 can control the reading transistor like, N5 on or off, so that nodes A, B and the first and second read Take bit 9 and lines 11 and 12 to conduct data reading. One end of the write transistor N6 is also connected to the second node B, but the other is connected to a write bit line 15, And write transistor N6: gate, 疋 connected to-write word line outline i, can be turned on or off by the level of f pressure level on write word line 3⑻, so to write data to the memory list In the cell, the write bit line 15 is written into the bit line 15 through the write transistor N6. Becky particularly emphasizes the relationship between the writing word line 300 and the writing selection line 400. Referring to FIG. 3, the level of the two levels is opposite to each other in any state and the writing selection line 400 The level change must precede the level change of the writing word line 300. In other words, the writing word signal line signal issued by the peripheral circuit (decoder 3) must first generate a writing selection through an inverter 4. The signal of the line is restored by the inverter 5 to the original written word line signal. The read operation of the present invention is achieved by controlling the read word line 200, the read bit lines 11, 12 and the write selection line 400, and the write operation does not control the write word line 300 , Write bit line 丨 5, and write selection line 400 to achieve, that is, the read and write actions are processed separately, the following will describe the data read and write actions separately: read mode see Figure 4 In the read mode, the write word line 300 is set to a low level state (this implicit write selection line 400 is set to a high level state), so the switching transistor N3 is turned on and turned off. Write transistor N6. The transistor N6 that is turned off in the figure is indicated by a dotted line. In other words, since the write transistor N6 is turned off, the write bit line 15 10 1223813 naturally cannot function. Since the switching transistor N 3 is on, the transistor N 2 is grounded through the transistor N 3. At this time, the overall structure is equivalent to the previous memory cell. Therefore, the stored transistors can be read by reading the transistors N 5 and N 6. Since the data on the memory cell nodes A and B is the same as the previous memory cell 5, its description is omitted. 2. Entry mode Refer to FIG. 5. In the write mode, the read word line 2000 is a low-level evil. Therefore, the power transistors N4 and N5 are turned off, and then the write word line is turned on again. 300 is in the 咼 level state to turn on the write transistor N6, that is, the write 10 bit line 15 and the 苐 ^ -node B are connected, so that the data to be written is written in the §memory cell . As mentioned earlier, before the write word line 300 has changed to a high level, the write select line 400 has already transitioned to a low level state, so the switching transistor N3 is turned off, so the source of the transistor N2 It is not grounded at this time. 15 Since the action when writing data is related to the state of the previously stored data (bits) in the memory cell, the following two situations are explained: ⑴Write "1" Possible situation of writing "1" There are two types, one is the previously stored data in the memory cell as "1", and the other is that the data is stored ,, 0 ,,. In other words, the memory cell is written from "1" to "1", or from ,, 0, to "1". Since the state of the former (1-1) is the same before and after writing, the state of each transistor has not changed, so only the latter will be described. Write the original 0 as 1 'the original two-level node B must be pulled down to the low level' and the original low-level node A must be pulled up to the high level, 11 1223813 before the poor material "1" is completed Write. Therefore, the method is to change the write bit line 15 to a low level (about 0V) after the write bit line 15 has been precharged, and the write voltage θ is turned on after the write body N6 is turned on. The node b will be discharged, that is, the current flowing through the transistor P2 can flow through the node B to the write bit 5 line 15 and thus the node B becomes a low level. Because the node B is at a low level, the gate of the transistor N1 and ρ is extremely low together. Therefore, the transistor N1 is closed and the transistor ρ is turned on, so that the node A becomes a high level. Write. (2) There are two possible situations for writing "〇" 1〇 writing "〇", one is to write the memory unit from "〇" to "0", and the other is to write "1" , Is written as ,, 0 ,,. Only the latter will be explained here. To write the original "1" as "〇", it is necessary to pull the original low level node B to the south level, and the original high level node A must be pulled to the low level 15. Therefore, the method is After the write bit line 15 has been precharged to a high level, the write bit line 15 is maintained at a high level state. After the write transistor N6 is turned on, the node B will be charged. It can be seen that before writing "0", the state of the writing bit line 丨 5 does not need to be changed (same as after precharging, all are maintained at a high level), so the time of writing 〇 can be greatly reduced by 20 Power consumption, in particular, after the writing transistor Νό is turned on, 'Although the original Lang point B was low, but because the switching transistor N3 was turned off before we wrote, the node B is connected to the ground. The line has been cut off. In other words, the node B level can be easily pulled up to a high level. Therefore, after the writing of "0" is completed, the write bit line 15 is further subjected to a 12 5 precharge swing. In order to reduce, the power consumption during writing is reduced. The door is OR: point B is already at a high level, so the gates of transistors N1 and P1 are aligned to the level. Therefore, the transistor N1 is closed and the transistor is turned off, so that point A becomes low. The writing of the dog is completed "],". ^ The following table is not the unit of the present invention and the traditional random access memory cells, and 128 cells are connected in series as a basic unit, using π · (TSMC ) Male 5 _35 // m, after simulation test with HSPICE, the obtained write data can be from a, seven, · 丨 ... ▲ ^ ^ 4.92E-01 —-~~ -—— --- by It can be seen from the table that the present invention is almost the same when writing "1," when the memory is written, but when writing "0 ,," the body N3 blocks the ground path, so when writing, "0 ,," The voltage level has hardly changed, and the reduction of its power consumption can reach 97%. ^ Above 0 changes in writing status ~ ----___ years old "1" is written as, '〇 by "〇" is written as "〇" by “1” is written as “1”. As written, 1, the traditional SRAM block rate consumption (Mwl 4.65E-01 4.37E-01 —-------- 4.35E-01 suitable consumption (mW '1.30 E-02 ^ 17E-03 4.20E-01 —-— 4.64 E-01 Power reduction 97.21% 98.82% ------ 3 ^ 50% ^ 5 ^ 70% ^ Its power consumption is 15% of the bit line due to the switching transistor writing. In addition, the present invention adopts asymmetric Circuit design, so its stability (static noise margin, static noise margin) is slightly worse than the previous memory cell, but at this point you can adjust the width and length ratio of transistor N2 and transistor N3 ( W / L ratio) and other process parameters to make appropriate compensation will not affect the performance of the present invention in actual operation. Referring to Fig. 6, the second preferred embodiment of the present invention is shown, compared with the first 13 1223813 5 The difference between the preferred embodiment is mainly that the memory unit with a write port (_ P ° rt) and a read port (Pern) described in the first preferred embodiment, that is, its write and read The execution of the action is to enter the light through different bit lines. This example refers to a single state of writing / reading Tan's memory, that is, the action of writing and reading is through the same The bit line 18 is used. In this example, the circuit configuration is different from the first bit line 18, and only a single preferred embodiment is required. In one read transistor N5, this reads the end of the transistor N5 and is connected to the bit line ^ 8 in common with the write transistor N6. The operation of the remaining elements 1 is the same as above, & No longer described, the following only outlines its read and write actions.
在項取枳式時，是使得寫入字元線300為低準位狀態 ，並使寫入選擇線400為高準位狀態，因此打開了開關電 晶體N3 ’使第二反相器2能夠接地。故使讀取字元線2〇〇 15 為高準位後，能打開讀取電晶體N5，使節點B與位元線18 相導通而進行資料的讀取，此處大致與第一較佳實施例相 同0 2〇 項取位元，’〇”時，在位元線18已被預充至高準位後，由 於節點B亦為高準位，因此位元線丨8會維原在高準位狀態 。讀取位元”1”時，由於節點B是低準位，因此被預充至高 準位的位元線18會經由電晶體N2、N3進行放電，經由位 元線18準位的變化，週邊電路就能知道所讀取之位元為，，0，， 2·寫入農立 14 1223813 與第一實_所述完全相同，㈣是在寫人，，〇”時，由 :=18之準位並不需要改變，加上節點B因為開關電 曰曰體N3被關閉之緣故，因此大幅減少了寫入，，〇，，時所需之 功率消耗。 5 综上所述，本發明採用非對稱性的記憶體單胞設計， 使得在寫人位元，，〇，，時，寫人位元線之準位狀態不需加以改 變（毋需充放電），因此降低了功率消耗，特収由於開關電 晶體N 3的作用，使得節點B更能被輕易地拉昇到高準位， 10 故減少其電壓擺幅，有效地減少了整體的功率消耗量，確 實達到本發明之目的。 ▲惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明書内容所作之簡單的等效變化與修飾，皆 應仍屬本發明專利涵蓋之範圍内。 15 【圓式簡單說明】 圖1是一電路圖，說明以往具一寫入埠與一讀取埠的 隨機存取記憶體單胞； 20 圖2是一電路圖，說明本發明低功率之靜態隨機存取 記憶體單胞的第一較佳實施例，本實施例採用一寫入埠與 一讀取埠之態樣； 圖3是一示意圖，說明控制寫入選擇線與寫入位元線 之k號互為反相的關係； 圖4是一電路圖，說明該較佳實施例在讀取模式時一 寫入電晶體被關閉而不作動，且一開關電晶體是被打開； 15 1223813 圖5是一電路圖，說明該較佳實施例在寫入模式時兩 個讀取電晶體被關閉，且該開關電晶體亦被關閉；以及 圖6是一示意圖，說明本發明低功率之靜態隨機存取 記憶體單胞的第二較佳實施例，本實施例採用一寫入/讀取 5 埠之態樣。In the term selection mode, the write word line 300 is set to a low level state, and the write select line 400 is set to a high level state. Therefore, the switching transistor N3 is turned on to enable the second inverter 2 to be enabled. Ground. Therefore, after the reading word line 200115 is at a high level, the reading transistor N5 can be turned on, and the node B is connected to the bit line 18 for data reading. This is generally better than the first. In the same embodiment, the bit number is taken as 0 2 0. When the bit line 18 has been precharged to a high level, since the node B is also a high level, the bit line 8 will be maintained at a high level. Level status. When reading bit "1", since node B is at a low level, the bit line 18 precharged to a high level will be discharged via transistors N2 and N3, and level via bit line 18 Changes, the peripheral circuit can know that the read bit is ,, 0 ,, 2 · Writing to Nongli 14 1223813 is exactly the same as that described in the first real _. The level of == 18 does not need to be changed. In addition, because node B is turned off because of the switch body N3, the power consumption required for writing,, 0, and is greatly reduced. 5 In summary, the present invention uses an asymmetric memory cell design, so that when writing human bits,, 0 ,,, the standard state of the writing human bit line does not need to be changed (no charge or discharge is required). ), So the power consumption is reduced. Due to the effect of the switching transistor N 3, the node B can be easily pulled to a high level. 10 Therefore, its voltage swing is reduced, which effectively reduces the overall power consumption. The amount does indeed achieve the purpose of the present invention. ▲ But the above are only the preferred embodiments of the present invention. When the scope of implementation of the present invention cannot be limited by this, that is, the simple equivalent changes and modifications made according to the scope of the patent application and the content of the invention specification of the present invention , All should still fall within the scope of the invention patent. 15 [Circular brief description] Figure 1 is a circuit diagram illustrating a conventional random access memory unit with a write port and a read port. 20 Figure 2 is a circuit diagram illustrating the low-power static random memory of the present invention. A first preferred embodiment of taking a memory cell, this embodiment uses a write port and a read port; FIG. 3 is a schematic diagram illustrating the control of k of a write select line and a write bit line The numbers are in inverse relation to each other; FIG. 4 is a circuit diagram illustrating that the write transistor is turned off without operation and a switching transistor is turned on in the read mode in the preferred embodiment; 15 1223813 FIG. 5 is A circuit diagram showing that the two reading transistors are turned off and the switching transistor is turned off in the write mode of the preferred embodiment; and FIG. 6 is a schematic diagram illustrating the low-power static random access memory of the present invention The second preferred embodiment of the unit cell is a write / read 5 port mode.
16 1223813 【圖式之主要元件代表符號說明】 1 第一反相器 N3 開關電晶體 2 第二反相器 N4 讀取電晶體 11 第一讀取位元線 N5 讀取電晶體 12 第二讀取位元線 N6 寫入電晶體 15 寫入位元線 P1 電晶體 200 讀取字元線 P2 拉昇電晶體 300 寫入子7G線 A 節點 400 寫入選擇線 B 節點 N1 電晶體 18 位元線 N2 拉降電晶體16 1223813 [Description of the main symbols of the diagram] 1 First inverter N3 Switch transistor 2 Second inverter N4 Read transistor 11 First read bit line N5 Read transistor 12 Second read Bit line N6 write transistor 15 write bit line P1 transistor 200 read word line P2 pull-up transistor 300 write sub 7G line A node 400 write select line B node N1 transistor 18 bits Line N2 pull-down transistor
1717