TWI480871B - Static random access memory - Google Patents

Description

Static random access memory

The present invention relates to a memory, and more particularly to a static random access memory (SRAM).

See Figure 1, "Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty and Dhiraj K. Pradhan, "A 2-Port 6T SRAM Bitcell Design with Multi-Port Capabilities at Reduced Area Overhead," Quality Electronic Design ( ISQED ) , 2010 11th International Symposium on , pp. 131-138, March 2010, discloses a conventional static random access memory comprising at least one memory unit. The memory unit has a data storage capacity of 1×32 bits, and includes thirty-two memory cells MC ₁ to MC ₃₂ and two N-type transistors 11 and 12. Each memory cell MC ₁ -MC ₃₂ includes two P-type transistors 21, 22 and four N-type transistors 23-26.

When writing "0" to memory cell MC _k (1 k 32), write word signal WW at logic high potential, complementary write word signal At a logic low potential, the write bit signal WB _{k is} at a logic low level such that the N-type transistor 25 of the memory cell MC _k is turned on and the N-type transistor 11 is not turned on, so the write bit signal WB _k is written via the memory cell MC N-type transistor 25 of memory cell _{k k} the MC point Q to a logic low level, the memory cells of the MC _k Points to a logic high level, the memory cell MC _k such that the stored value is "0."

When to be written in the memory cell MC _k to "1", write word signal WW in the logic high level, the complementary write word signal At a logic low potential, the write bit signal WB _{k is} at a logic high level such that the N-type transistor 25 of the memory cell MC _k is turned on and the N-type transistor 11 is not turned on, so the write bit signal WB _k is written via the memory cell MC N-type transistor 25 of memory cell _{k k} the MC point Q to a logic high level, the memory cells of the MC _k The point is pulled to a logic low level so that the value stored in the memory cell MC _k is "1".

When the memory cell MC _k to be read, the read signal RW characters in the logic high level, so that the N-type transistor 12 is turned on, and therefore, if the memory cell MC _k stored value is "0", the memory cell MC _k The N-type transistor 26 is turned on, so that the read bit signal RB _k that has been precharged to a logic high level is pulled to a logic low level via the N-type transistor 26 and the N-type transistor 12 of the memory cell MC _k , indicating The value read from the memory cell MC _k is "0". If the value stored in the memory cell MC _k is "1", the N-type transistor 26 of the memory cell MC _k is not turned on, and thus has been precharged to a logic high. The potential read bit signal RB _k remains at a logic high level, indicating that the value read from the memory cell MC _k is "1".

However, conventional static random access memory has the following disadvantages:

(1) It is assumed that the values stored in the memory cells MC ₁ and MC ₂ are all "0", and at this time, the N-type transistors 23 of the memory cells MC ₁ and MC ₂ are turned on. When you want to write "1" to the memory cell MC ₁ is to be written and "0" to the memory cell MC _2, the memory cell MC _1, MC ₂ N type transistor 25 are turned on, the logic high write signal WB bit memory cell MC will be N-type transistors 25, 23 and ₁ of the memory cell MC ₂ N type transistor 23 and memory cell MC to the potential of the point Q ₂ by _one. This can lead to write "1" to the memory cell MC ₁ becomes more difficult, and the value stored in the memory cell MC ₂ may also be changed.

(2) when the N-type transistor 25 of memory cell MC _k nonconductive, if the write signal WB _k bit memory cell MC _k and the point Q at a different potential, the N-type transistor 25 of memory cell MC _k alone The potential difference between the write bit signal WB _k and the Q point of the memory cell MC _k is subjected to a large leakage current to increase the static power consumption.

(3) When the N-type transistor 12 is not turned on, if the memory cell MC _k stored value is "0", the memory cell MC _k of the N-type 26 is turned crystals, so that the N-type transistor 12 alone bear reading RB _k-bit signal between the low logic level and the potential difference, resulting in large leakage current is increased static power consumption.

(4) Since the thirty-two memory cells MC ₁ to MC _{32 are} combined with an N-type transistor 12, the reading speed is slow.

Accordingly, it is an object of the present invention to provide a static random access memory that can ameliorate at least some of the disadvantages of the prior art.

Thus, the SRAM of the present invention comprises at least one memory cell. Each of the memory cells includes first to sixth connection terminals, first and second P-type transistors, and first to sixth N-type transistors. The first P-type transistor has a first end electrically connected to a first power terminal, a second end, and a control end. The first and second N-type transistors connected in series are electrically connected between the second end of the first P-type transistor and the first connection end. The first N-type transistor has a control end electrically connected to the second connection end. The second N-type transistor has a control terminal electrically connected to the control terminal of the first P-type transistor. The second P-type transistor has a first end electrically connected to the first power terminal, a second end electrically connected to the control end of the first P-type transistor, and an electrical connection to the first P-type The control end of the second end of the crystal. The third N-type transistor has a first end electrically connected to the control end of the first P-type transistor, a second end electrically connected to a second power supply end, and an electrical connection to the first P-type electric The control end of the second end of the crystal. The fourth N-type transistor has a first end electrically connected to the third connection end, a second end electrically connected to the second end of the first P-type transistor, and an electrical connection to the first connection end Control terminal. The fifth and sixth N-type transistors connected in series are electrically connected between the fourth connection end and the fifth connection end. The fifth N-type transistor has a control end electrically connected to the sixth connection end. The sixth N-type transistor has a control terminal electrically connected to the control terminal of the first P-type transistor.

For one of the first memory cells of the at least one memory cell, the first connection terminal receives a first write word signal, the second connection terminal receives a first write bit signal, and the fourth connection terminal outputs A first read bit signal, the sixth connection end receives a first read word signal.

The static random access memory further includes seventh and eighth N-type transistors. The seventh N-type transistor has a first end electrically connected to the second connection end of the first memory cell, a second end electrically connected to the third connection end of the first memory cell, and receiving a control signal The console. The eighth N-type transistor has a first end electrically connected to the fifth connection end of the first memory cell, a second end electrically connected to the second power supply end, and an electrical connection to the first memory cell The control end of the sixth connection.

The foregoing and other technical aspects, features and advantages of the present invention will be apparent from the following description of the preferred embodiments.

Referring to Figures 2 and 3, a preferred embodiment of the SRAM of the present invention includes at least one memory unit. The memory unit has a data storage capacity of 4×4 bits, and includes sixteen memory cells MC _1,1 to MC _4,4 and eight N-type transistors N ₁ toN ₈ .

Each memory cell MC _1,1 ~MC _4,4 includes first to sixth connection terminals 41 to 46, first and second P-type transistors 51, 52, and first to sixth N-type transistors 61~ 66. The first P-type transistor 51 has a first end electrically connected to a first power supply terminal 71 at a logic high potential, a second end (hereinafter referred to as a Q point), and a control terminal (hereinafter referred to as point). The first and second N-type transistors 61, 62 connected in series are electrically connected between the second end of the first P-type transistor 51 and the first connection end 41. The first N-type transistor 61 has a control terminal electrically connected to the second connection terminal 42. The second N-type transistor 62 has a control terminal electrically connected to the control terminal of the first P-type transistor 51. The second P-type transistor 52 has a first end electrically connected to the first power terminal 71, a second end electrically connected to the control end of the first P-type transistor 51, and an electrical connection to the first P-type battery. The control end of the second end of the crystal 51. The third N-type transistor 63 has a first end electrically connected to the control end of the first P-type transistor 51, a second end electrically connected to a second power supply terminal 72 at a logic low potential, and an electrical connection. To the control end of the second end of the first P-type transistor 51. The fourth N-type transistor 64 has a first end electrically connected to the third connection end 43, a second end electrically connected to the second end of the first P-type transistor 51, and an electrical connection to the first connection end The control end of 41. The fifth and sixth N-type transistors 65, 66 connected in series are electrically connected between the fourth connection end 44 and the fifth connection end 45. The fifth N-type transistor 65 has a control terminal electrically connected to the sixth connection terminal 46. The sixth N-type transistor 66 has a control terminal electrically connected to the control terminal of the first P-type transistor 51.

Memory cell MC _i,1 ~MC _i,4 (1 i The first connection terminals 41 of 4) are electrically connected together and receive an ith write word signal WW _i . The fifth terminals 45 of the memory cells MC _i,1 ~MC _i,4 are electrically connected together. The sixth terminals 46 of the memory cells MC _i,1 ~MC _i,4 are electrically coupled together and receive an ith read word signal RW _i . Memory cell MC _1,j ~MC _4,j (1 j 4) a second connection terminal 42 are electrically connected together and receiving a j-bit write signal WB _j. The third terminals 43 of the memory cells MC _1,j ~MC _4,j are electrically connected together. The fourth terminals 44 of the memory cells MC _{1, j} ~ MC _{4, j} are electrically connected together and output a j-th read bit signal RB _j .

N _j N-type transistor having an electrical connection to the memory cell MC _1, a first end of the second end 42 of the connection _j, a ₁ is electrically connected to the _third connection of the second end of the _j memory cell MC of the end 43, and A control terminal that receives a control signal CTRL.

The N-type transistor N _4+i has a first end electrically connected to the fifth connection end 45 of the memory cell MC _{i, 1} , a second end electrically connected to the second power supply end 72 , and an electrical connection to the memory The control terminal of the sixth terminal 46 of the cell MC _i,1 .

When "0" is written to the memory cell MC _i,j , the control signal CTRL is at a logic high level, the ith write word signal WW _{i is} at a logic high level, and the jth write bit signal WB _{j is} at a logic low. potential, such that the N-type transistor N _j is turned on, the memory cell MC _{i, j} of the fourth N-type transistor 64 is turned on, the memory cell MC _{i, j} of the first N-type transistor 61 is not turned on, the j-th write bit element signals WB _j N N _j-type transistor and the memory cell MC _{i, j} of the fourth N-type transistor 64 via the memory cell MC _{i, j} point Q to a logic low level, the memory cell MC _{i, j} is The point is pulled to a logic high level so that the value stored in the memory cell MC _i,j is "0".

When "1" is to be written to the memory cell MC _i,j , the control signal CTRL is at a logic high level, the ith write word signal WW _{i is} at a logic high level, and the jth write bit signal WB _{j is} at a logic high. potential, such that N _j N-type transistor is turned on, the memory cell MC _{i, j} of the fourth N-type transistor 64 is turned on, the memory cell MC _{i, j} of the first N-type transistor 61 is turned on, so the first write bit j signal WB _j N N _j-type transistor and the memory cell MC _{i, j} of the fourth N-type transistor 64 via the memory cell MC _{i, j} point Q to a logic high level, the memory cell MC _{i, j} is The point is pulled to a logic low level so that the value stored in the memory cell MC _i,j is "1". In addition, if the memory cell MC _{i,j is} originally stored with a value of "0", the second N-type transistor 62 of the memory cell MC _i,j is turned on, so the ith write word signal WW _i passes through the memory cell MC. _{i, j} and the second first N-type memory cell transistors 62, 61 to the MC _{i, j} point Q to a logic high level, the memory cell in the MC _{i, j} is The point is pulled to a logic low. Therefore, this embodiment can provide up to two paths for writing "1".

When the memory cell MC _i,j is to be read, the ith read word signal RW _{i is} at a logic high level, so that the N-type transistor N _{i+4 is} turned on, _and the fifth N-type transistor of the memory cell MC _i,j is turned on. 65 is turned on. Therefore, if the value stored in the memory cell MC _i,j is "0", the sixth N-type transistor 66 of the memory cell MC _i,j is turned on, thereby being precharged to the logic high potential j RB _j read bit signal via the memory cell MC _{i, j} of the fifth transistor and the sixth N-type and N-type transistors 65, 66 N _{i + 4} is pulled to a logic low level, represents the memory cell MC _i, The value read by _j is "0". If the value stored in the memory cell MC _i,j is "0", the sixth N-type transistor 66 of the memory cell MC _i,j is not turned on, and thus has been precharged to The logically high jth read bit signal RB _j remains at a logic high level, indicating that the value read from the memory cell MC _i,j is "1".

The static random access memory of this embodiment has the following advantages:

(1) It is possible to provide up to two paths for writing "1", making it easier to write "1". Moreover, the action of writing "1" to the memory cell MC _i,j does not affect the value stored by other memory cells.

(2) When the fourth N-type transistor 64 of the memory cell MC _i,j is not turned on, if the j-th write bit signal WB _j and the Q point of the memory cell MC _i,j are at different potentials, The N-type transistor N _j is rendered non-conductive, so that the N-type transistor N _j connected in series and the fourth N-type transistor 64 of the memory cell MC _i,j share the j-th write bit signal WB _j and the memory cell MC The potential difference between the Q points of _{i, j} to reduce leakage current, thereby reducing static power consumption. In addition, the series N-type transistor N _j and the fourth N-type transistor 64 of the memory cell MC _i,j also contribute to reducing dynamic power consumption.

(3) When the sixth N-type transistor 66 of the memory cell MC _i,j is turned on _, the fifth N-type transistor 65 of the N-type transistor N _i+4 and the memory cell MC _i,j may be eliminated. Turning on, the N-type transistor N _i+4 connected in series and the fifth N-type transistor 65 of the memory cell MC _i,j jointly receive the potential difference between the j-th read bit signal RB _j and the logic low potential, Reduce leakage current, which in turn reduces static power consumption. In addition, the series N-type transistor Ni ₊₄ and the fifth N-type transistor 65 of the memory cell MCi _,j also contribute to reducing dynamic power consumption.

(4) Since the number of memory cells MC _i,1 ~MC _{i, 4} cooperating with an N-type transistor N _i+4 is four, which is smaller than the number of conventional static random access memories used for thirty-two, Therefore, the reading speed can be increased.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

MC ₁ ~MC ₃₂ . . . Memory cell

11,12. . . N type transistor

21, 22. . . P-type transistor

23~26. . . N type transistor

MC _1,1 ~MC _4,4 . . . Memory cell

MC _i,j . . . Memory cell

N ₁ ~N ₈ . . . N type transistor

N _i+4 , N _j . . . N type transistor

41~46. . . Connection end

51, 52. . . P-type transistor

61~66. . . N type transistor

71, 72. . . Power terminal

1 is a circuit diagram illustrating a conventional static random access memory;

2 is a schematic view showing a preferred embodiment of the static random access memory of the present invention; and

Figure 3 is a circuit diagram illustrating a memory cell in accordance with a preferred embodiment of the present invention.

MC _i,j . . . Memory cell

N _i+4 , N _j . . . N type transistor

41~46. . . Connection end

51, 52. . . P-type transistor

61~66. . . N type transistor

71, 72. . . Power terminal

Claims (5)

A static random access memory comprising: at least one memory cell, each memory cell comprising: first to sixth connection terminals; a first P-type transistor having a first end electrically connected to a first power supply end a second end, and a control end; the first and second N-type transistors connected in series are electrically connected between the second end of the first P-type transistor and the first connection end, the first N The type of transistor has a control end electrically connected to the second connection end, the second N-type transistor has a control end electrically connected to the control end of the first P-type transistor; a second P-type transistor having a first end electrically connected to the first power terminal, a second end electrically connected to the control end of the first P-type transistor, and a control end electrically connected to the second end of the first P-type transistor; a third N-type transistor having a first end electrically connected to the control end of the first P-type transistor, a second end electrically connected to a second power supply end, and an electrical connection to the first P-type a control end of the second end of the transistor; a fourth N-type transistor having an electrical connection to the third connection end a first end, a second end electrically connected to the second end of the first P-type transistor, and a control end electrically connected to the first connection end; and fifth and sixth N-type transistors connected in series, the electric Connected between the fourth connection end and the fifth connection end, the fifth N-type transistor has a control end electrically connected to the sixth connection end, and the sixth N-type transistor has an electrical connection to the first a control terminal of a control terminal of a P-type transistor; for one of the first memory cells of the at least one memory cell, the first connection terminal receives a first write word signal, and the second connection terminal receives a first write In the bit signal, the fourth connection terminal outputs a first read bit signal, and the sixth connection terminal receives a first read word signal; the static random access memory further includes: a seventh N type The transistor has a first end electrically connected to the second connection end of the first memory cell, a second end electrically connected to the third connection end of the first memory cell, and a control end receiving a control signal; And an eighth N-type transistor having a fifth connection electrically connected to the first memory cell The first end, a second end electrically connected to the second power end, and a control end electrically connected to the sixth connection end of the first memory cell. The SRAM of claim 1, wherein: for one of the at least one memory cell, the first connection terminal receives a second write character signal, the first The second connection end is electrically connected to the second connection end of the first memory cell, the fourth connection end is electrically connected to the fourth connection end of the first memory cell, and the sixth connection end receives a second read word signal The second end of the seventh N-type transistor is further electrically connected to the third connection end of the second memory cell. The static random access memory according to claim 2, further comprising: a ninth N-type transistor having a first end electrically connected to the fifth connection end of the second memory cell, and an electrical connection And a second end connected to the second power terminal, and a control end electrically connected to the sixth connection end of the second memory cell. The static random access memory according to claim 1, wherein: for one of the at least one memory cell, the first connection terminal is electrically connected to the first connection of the first memory cell The second connection end receives a second write bit signal, the fourth connection end outputs a second read bit signal, and the sixth connection end is electrically connected to the sixth connection end of the first memory cell. The first end of the eighth N-type transistor is also electrically connected to the fifth connection end of the third memory cell. The static random access memory according to claim 4, further comprising: a tenth N-type transistor having a first end electrically connected to the second connection end of the third memory cell, and an electrical connection And a second end connected to the third connection end of the third memory cell, and a control end electrically connected to the control end of the seventh N-type transistor.