CN104637528A - SRAM memory unit array, SRAM memory and control method thereof - Google Patents
SRAM memory unit array, SRAM memory and control method thereof Download PDFInfo
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- CN104637528A CN104637528A CN201310552338.3A CN201310552338A CN104637528A CN 104637528 A CN104637528 A CN 104637528A CN 201310552338 A CN201310552338 A CN 201310552338A CN 104637528 A CN104637528 A CN 104637528A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Abstract
The invention provides an SRAM storage unit array, an SRAM memory, and a control method thereof. The SRAM storage unit array comprises a plurality of word line pair arranged along the row direction, wherein each word line pair comprises a write word line and a read word line; a bit line pair arranged along the row direction, wherein the bit line pair comprises a first bit line and a second bit line; a plurality of storage units arranged between the word line pairs and the bit line pair, wherein each storage unit is connected to the corresponding work line pair and bit line pair and comprises a read terminal; and a read unit, wherein the read unit comprises a read transistor and a read bit line, and the read bit line is connected to the read terminals of the plurality of storage units through the read transistor. The provided SRAM storage unit array reduces the transistor number and the stability is improved at the same time.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of SRAM memory cell array, there is the SRAM memory of this SRAM memory cell array and the control method of this SRAM memory.
Background technology
Along with the development of digital integrated circuit, storer integrated on sheet has become ingredient important in digital display circuit.SRAM(Static Random Access Memory, static RAM) become important component part indispensable in on-chip memory with the advantage of its low-power consumption, high speed.As long as SRAM can preserve data, without the need to constantly refreshing it for its power supply.
SRAM one-piece construction can be divided into memory cell array and peripheral circuit two parts.In sram, storage unit is the most basic, most important ingredient.The quantity of the storage unit comprised in array and the stability of storage unit are two key factors affecting SRAM performance.The quantity of storage unit is more, and storage capacity is higher, and the size of sram chip is larger.
But the size of sram chip increases to be disagreed for portable requirement with consumer.The main flow unit of current SRAM is 6T, as shown in Figure 1.This 6T sram cell 100 comprises two identical and cross-linked phase inverters 110,120.Bit line (BL) is connected to memory node Q1, Q2 to 130,140 by two transmission transistors (PG) 150,160.In 6T SRAM, data memory node Q1, Q2 are directly connected to bit line to upper by transmission transistor 150 and 160.In the process read, because the dividing potential drop effect between transmission transistor and pull-down transistor can make the data of memory node be interfered, in addition, the data of memory node are also easy to be subject to the impact of external noise thus may cause logic error, affect the stability of storage unit.
Existing 8T SRAM memory cell 200(is as shown in Figure 2) comprise two identical and cross-linked phase inverters 210,220.Bit line (BL) is connected to memory node Q3, sense bit line (RBL) 270 by reading transmission transistor (RPG) 280 and reading transistor (RPD) 290 is connected to memory node Q4 to 230,240 by two transmission transistors (PG) 250,260.Although the SRAM memory cell 200 of 8T structure improves stability, the quantity of transistor increases, and the size also corresponding increase of memory cell array, is unfavorable for the raising of integrated circuit integrated level and the miniaturization of chip size.
Therefore, be necessary to propose a kind of SRAM memory cell array, there is the SRAM memory of this SRAM memory cell array and the control method of this SRAM memory, to solve problems of the prior art.
Summary of the invention
In order to solve problems of the prior art, the invention provides a kind of SRAM memory cell array.This SRAM memory cell array comprises: multiple wordline pair arranged in the row direction, and described wordline is to comprising write word line and readout word line; Along the bit line pair of column direction arrangement, described bit line is to comprising the first bit line and the second bit line; Described wordline to and described bit line between multiple storage unit, each described storage unit be connected to respectively corresponding described wordline to described bit line pair, described storage unit comprises and reads end; And read unit, described in read unit and comprise a reading transistor and a sense bit line, described sense bit line is connected to the described reading end of multiple described storage unit by described reading transistor.
Preferably, described SRAM memory cell array also comprises interconnection line, and the reading end of described storage unit is connected to described interconnection line, to be connected to described reading transistor by described interconnection line.
Preferably, the grid of described reading transistor is connected to the described reading end of described storage unit; The drain electrode of described reading transistor is connected to described sense bit line; The source ground of described reading transistor.
Preferably, described reading transistor is nmos pass transistor.
Preferably, described storage unit comprises: the first phase inverter and the second phase inverter, described first phase inverter and described second phase inverter are connected between first node and Section Point, the input end of wherein said first phase inverter and the output terminal of described second phase inverter are connected to described first node, and the output terminal of described first phase inverter and the input end of described second phase inverter are connected to described Section Point; First writes transmission transistor and second writes transmission transistor, described first writes transmission transistor is connected with described first node and described Section Point respectively with the described second source electrode writing transmission transistor, drain electrode is connected with described first bit line and described second bit line respectively, and grid connects with corresponding write word line respectively; And read transmission transistor, described in read transmission transistor source electrode be connected with in described first node and described Section Point, drain electrode is connected with described reading transistor, and grid is connected with described readout word line.
Preferably, described first phase inverter comprises the first pull-up PMOS transistor and the first pulldown NMOS transistor, described second phase inverter comprises the second pull-up PMOS transistor and the second pulldown NMOS transistor, wherein said first pull-up PMOS transistor is connected with supply voltage with the source electrode of described second pull-up PMOS transistor, and the source ground of described first pulldown NMOS transistor and described second pulldown NMOS transistor; The drain electrode of described first pull-up PMOS transistor and described first pulldown NMOS transistor is connected to described first node, and the drain electrode of described second pull-up PMOS transistor and described second pulldown NMOS transistor is connected to described Section Point; The grid of described first pull-up PMOS transistor and described first pulldown NMOS transistor is connected to described Section Point, and the grid of described second pull-up PMOS transistor and described second pulldown NMOS transistor is connected to described first node.
Preferably, described first write transmission transistor, described second and write transmission transistor and described transmission transistor of reading is nmos pass transistor.
According to another aspect of the present invention, a kind of SRAM memory is also provided.Described SRAM memory comprises any one SRAM memory cell array above-mentioned.
According to a further aspect of the invention, a kind of control method based on above-mentioned SRAM memory is also provided.This control method comprises: when carrying out write operation to the selected person in multiple described storage unit, and the write word line corresponding with described selected person is set to noble potential, and peripheral circuit is delivered to described bit line to upper information as input; And when read operation is carried out to the selected person in multiple described storage unit, the readout word line corresponding with described selected person is set to noble potential, and described sense bit line is set to noble potential, to be read the information in described selected person by described sense bit line.
Preferably, described control method also comprises: the described write word line corresponding with the selected person of first in described multiple described storage unit is set to noble potential, and the described readout word line corresponding with the selected person of second in described multiple storage unit is set to noble potential, to carry out write operation to the described first selected person and to carry out read operation to the described second selected person simultaneously simultaneously.
Few according to the number of transistors that the storage unit of SRAM memory cell array of the present invention comprises, and an array storage unit only acts on multiple storage unit with a reading transistor, reduce the quantity of transistor in SRAM memory cell array, thus reduce the size of SRAM memory cell array, and then reduce the size of sram chip.Meanwhile, the write operation path in storage unit separates with read operation path, can improve β ratio and γ ratio simultaneously, and improve static noise margin, thus improve stability.
In summary of the invention, introduce the concept of a series of reduced form, this will further describe in embodiment part.Content part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection domain attempting to determine technical scheme required for protection.
Below in conjunction with accompanying drawing, describe advantages and features of the invention in detail.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the present invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the schematic diagram of existing 6T SRAM memory cell;
Fig. 2 is the schematic diagram of existing 8T SRAM memory cell;
Fig. 3 is the schematic diagram of SRAM memory cell array according to an embodiment of the invention; And
Fig. 4 is the schematic diagram of the SRAM memory cell in the SRAM memory cell array shown in Fig. 3.
Embodiment
Next, by reference to the accompanying drawings the present invention will more intactly be described, shown in the drawings of embodiments of the invention.But the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other elements or layer time, its can directly on other elements or layer, with it adjacent, connect or be coupled to other elements or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other elements or layer time, then there is not element between two parties or layer.In the accompanying drawings, for the sake of clarity, the size in Ceng He district and relative size may be exaggerated.And use the element that identical Reference numeral represents identical.
According to an aspect of the present invention, a kind of SRAM memory cell array is provided.As shown in Figure 3, SRAM memory cell array 300 comprises: multiple wordline arranged in the row direction to, along the bit line of column direction arrangement to, multiple storage unit 310 and read unit 320.Here only the array comprising an array storage unit 310 is described.The such memory cell array of multiple row 300 can be comprised in each SRAM memory.Multiple such memory cell array 300 along line direction arrangement or otherwise can arrange.
The wordline of this memory cell array 300 is to comprising write word line (WWL) 330 and readout word line (RWL) 340, and bit line is to comprising the first bit line (BL) 350 and the second bit line (BLB) 360.The quantity of storage unit 310 corresponds to the right quantity of wordline, is also the quantity of write word line 330 or readout word line 340.Each storage unit 310 be connected to each wordline to and bit line between.As shown in Figure 3, storage unit 310 is connected to write word line 330 and readout word line 340 and between the first bit line 350 and the second bit line 360.Each storage unit 310 comprises writing end and reading holds, and write end is connected to the first bit line 350 and the second bit line 360, and reading end is connected to reads unit 320.The current potential of write word line 330 and readout word line 340 can be set to noble potential or electronegative potential, for selecting corresponding storage unit 310, controls write operation and the read operation of corresponding storage unit 310.According to one embodiment of present invention, one in write word line 330 can be set to noble potential, and other write word lines 330 can be set to electronegative potential, now the storage unit 310 corresponding to the write word line 330 with this noble potential can carry out write operation.First bit line 350 and the second bit line 360 can receive the voltage of peripheral circuit (not shown) transmission as input, thus by information write storage unit 310.
Read unit 320 and comprise a reading transistor 321 and a sense bit line (RBL) 322, this sense bit line 322 is connected to the reading end of multiple storage unit 310 by reading transistor 321.The plurality of storage unit 310 is positioned at same row.Therefore, just can realize the read operation of multiple storage unit 310 by means of only a reading transistor 321, the number of transistors of SRAM memory cell array can be reduced, thus the size of SRAM memory cell array can be reduced, and then reduce the size of sram chip.In this embodiment provided by the invention, when needs carry out read operation, the storage unit 310 of carrying out read operation is needed by readout word line 340 is selected, such as will the readout word line 340 of storage unit 310 correspondence of carrying out read operation be needed to be set to noble potential, then by sense bit line 322, read operation is carried out to selected storage unit 310.
Connection conveniently between multiple storage unit 310 and reading transistor 321, this SRAM memory cell array also comprises interconnection line (inter line, IL) 370, the reading end of multiple storage unit 310 is all connected to interconnection line 370, to be connected to reading transistor 321 by interconnection line 370.Therefore, multiple storage unit 310 can be connected to reading transistor 321 by an interconnection line 370, can facilitate overall routing.
Preferably, the grid of reading transistor 321 is connected to the reading end of storage unit 310; The drain electrode of reading transistor is connected to sense bit line 322; The source ground of reading transistor.In this kind of connected mode, when carrying out read operation, what be connected with the reading end of storage unit 310 is the grid of transistor, therefore the voltage fluctuation on sense bit line 322 and external noise can not have an impact to storage unit 310, thus add read noise tolerance limit, improve the stability of storage unit.Be connected in the preferred embodiment of reading transistor 321 at the reading end of storage unit 310 by interconnection line 370, the grid of reading transistor 321 is connected to the reading end of storage unit 310 by being connected to interconnection line 370.
Preferably, according to one embodiment of present invention, reading transistor 321 is nmos pass transistor.The main charge carrier of nmos pass transistor is electronics, and mobility is high, and electric current is relatively large, conveniently carries out read operation.Certainly, the present invention limits the type of reading transistor 321 unintentionally.In the present invention's other embodiments unshowned, reading transistor 321 can also be the transistor of other types, such as PMOS transistor.
The size of storage unit 310 determines the size of sram chip to a great extent, therefore, needs to make the size of storage unit 310 little as much as possible.Storage unit 310 can be made up of reverse unit, for by reverse for the current potential of memory node.As shown in Figure 3, storage unit 310 comprises the first phase inverter 311, second phase inverter 312, first and writes transmission transistor 313, second and write transmission transistor 314 and read transmission transistor 315.Storage unit 310 is introduced in detail below in conjunction with Fig. 3-Fig. 4.
As shown in Figure 3, first phase inverter 311 and the second phase inverter 312 are connected between first node Q5 and Section Point Q6, wherein the input end of the first phase inverter 311 and the output terminal of the second phase inverter 312 are connected to first node Q5, and the output terminal of the first phase inverter 311 and the input end of the second phase inverter 312 are connected to Section Point Q6.First phase inverter 311 of this storage unit 310 and the second phase inverter 312 form latch cicuit, in order to latch the data of memory node Q5 and Q6.
First phase inverter 311 and the second phase inverter 312 can be cmos cell.Such as, in according to one embodiment of present invention, as shown in Figure 4, first phase inverter 311 comprises the first pull-up PMOS transistor (PU) 311A and the first pulldown NMOS transistor (PD) 311B, second phase inverter 312 comprises the second pull-up PMOS transistor (PU) 312A and the second pulldown NMOS transistor (PD) 312B, wherein the first pull-up PMOS transistor 311A is connected with supply voltage with the source electrode of the second pull-up PMOS transistor 312A, and the source ground of the first pulldown NMOS transistor 311B and the second pulldown NMOS transistor 312B; The drain electrode of the first pull-up PMOS transistor 311A and the first pulldown NMOS transistor 311B is connected to first node Q5, and the drain electrode of the second pull-up PMOS transistor 312A and the second pulldown NMOS transistor 312B is connected to Section Point Q6; The grid of the first pull-up PMOS transistor 311A and the first pulldown NMOS transistor 311B is connected to Section Point Q6, and the grid of the second pull-up PMOS transistor 312A and the second pull-down NMOS crystal 312 pipe B is connected to first node Q5.This storage unit 310 comprises 7 transistors, and compared with the SRAM of 8 transistor-types, its unit size reduces, and makes sram chip size reduce further.
Further, first writes the source electrode that transmission transistor 313 and second writes transmission transistor 314 is connected with first node Q5 and Section Point Q6 respectively, and drain electrode is connected with the first bit line 350 and the second bit line 360 respectively, and grid connects with corresponding write word line 330 respectively.The drain electrode of reading transmission transistor 315 is connected with reading transistor 321.Should be appreciated that connection mentioned here can, for directly connecting, also can be indirectly connect.According to a preferred embodiment of the present invention, the drain electrode of reading transmission transistor 315 is connected to interconnection line 370, to be connected to reading transistor 321 by interconnection line 370.The grid reading transmission transistor 315 is connected with readout word line 340, and source electrode is connected with in first node Q5 and Section Point Q6, and according to one embodiment of present invention, the source electrode reading transmission transistor 315 is connected with Section Point Q6.
Preferably, first write transmission transistor 313, second and write transmission transistor 314 and read transmission crystal 315 and manage as nmos pass transistor.Same, as described above, the main charge carrier of nmos pass transistor is electronics, and mobility is high, and electric current is relatively large, conveniently carries out Signal transmissions.Certainly, the present invention is not intended to write to first the type that transmission transistor 313 and second writes transmission transistor 314 and read transmission transistor 315 and limits.In the present invention's other embodiments unshowned, first writes transmission transistor 313 and second writes transmission transistor 314 and reads the transistor that transmission transistor 315 can also be other types, such as PMOS transistor.
According to another aspect of the present invention, a kind of SRAM memory is also provided.This SRAM memory comprises any one SRAM memory cell array as above.Can comprise multiple this SRAM memory cell array in this SRAM memory, multiple this SRAM memory cell array arranges along line direction.Little according to the memory cell size of SRAM of the present invention, thus sram chip size is little.Improve storage unit stability simultaneously.
According to another aspect of the invention, a kind of control method based on above-mentioned SRAM memory is also provided.The method comprises:
When carrying out write operation to the selected person in multiple storage unit 310, the write word line 330 corresponding with selected storage unit 310 is set to noble potential, and peripheral circuit is delivered to bit line to the information on (comprising the first bit line 350 and the second bit line 360) as input.When read operation is carried out to the selected person in multiple storage unit 310, the readout word line 340 corresponding with selected storage unit 310 is set to noble potential, to be read the information in selected storage unit by sense bit line 322.Such as, in this embodiment, when carrying out read operation, first sense bit line 322 can be set to noble potential.Because the information of memory node can have an impact to the current potential of sense bit line 322, therefore can be compared the read output signal on this sense bit line 322 by external reference circuit, judge the storage information on memory node.
Based on above-mentioned SRAM memory, preferably, this control method also comprises and carries out read-write operation to multiple storage unit 310 simultaneously.Be about to the write word line corresponding with the selected person in first in 310 in multiple storage unit and be set to noble potential, by the first bit line 350 and the second bit line 360, write operation is carried out to this first selected person.The readout word line corresponding with the selected person of second in multiple storage unit 310 being set to noble potential simultaneously, by reading unit 320, read operation being carried out to this second selected person.Wherein the first selected person and the second selected person are different storage unit.Such as, sense bit line 322 is set to noble potential, compares the read output signal on this sense bit line 322 by reference to circuit, thus judge the storage information of this memory node.Can write operation be carried out to the first selected person by this control method simultaneously and write operation be carried out to the second selected person, improve access speed.
Few according to the number of transistors that the storage unit 310 of SRAM memory cell array 300 of the present invention comprises, and an array storage unit 310 only acts on multiple storage unit 310 with a reading transistor 321, reduce the quantity of transistor in SRAM memory cell array, thus reduce the size of SRAM memory cell array, and then reduce the size of sram chip.Meanwhile, the write operation path in storage unit 310 separates with read operation path, can improve β ratio and γ ratio simultaneously, and improve static noise margin, thus improve stability.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a SRAM memory cell array, is characterized in that, described SRAM memory cell array comprises:
Multiple wordline pair arranged in the row direction, described wordline is to comprising write word line and readout word line;
Along the bit line pair of column direction arrangement, described bit line is to comprising the first bit line and the second bit line;
Described wordline to and described bit line between multiple storage unit, each described storage unit be connected to respectively corresponding described wordline to described bit line pair, described storage unit comprises and reads end; And
Read unit, described in read unit and comprise a reading transistor and a sense bit line, described sense bit line is connected to the described reading end of multiple described storage unit by described reading transistor.
2. SRAM memory cell array as claimed in claim 1, it is characterized in that, described SRAM memory cell array also comprises interconnection line, and the reading end of described storage unit is connected to described interconnection line, to be connected to described reading transistor by described interconnection line.
3. SRAM memory cell array as claimed in claim 1, is characterized in that, the grid of described reading transistor is connected to the described reading end of described storage unit; The drain electrode of described reading transistor is connected to described sense bit line; The source ground of described reading transistor.
4. SRAM memory cell array as claimed in claim 1, it is characterized in that, described reading transistor is nmos pass transistor.
5. SRAM memory cell array as claimed in claim 1, it is characterized in that, described storage unit comprises:
First phase inverter and the second phase inverter, described first phase inverter and described second phase inverter are connected between first node and Section Point, the input end of wherein said first phase inverter and the output terminal of described second phase inverter are connected to described first node, and the output terminal of described first phase inverter and the input end of described second phase inverter are connected to described Section Point;
First writes transmission transistor and second writes transmission transistor, described first writes transmission transistor is connected with described first node and described Section Point respectively with the described second source electrode writing transmission transistor, drain electrode is connected with described first bit line and described second bit line respectively, and grid connects with corresponding write word line respectively; And
Read transmission transistor, described in read transmission transistor source electrode be connected with in described first node and described Section Point, drain electrode is connected with described reading transistor, and grid is connected with described readout word line.
6. SRAM memory cell array as claimed in claim 5, it is characterized in that, described first phase inverter comprises the first pull-up PMOS transistor and the first pulldown NMOS transistor, and described second phase inverter comprises the second pull-up PMOS transistor and the second pulldown NMOS transistor
Wherein said first pull-up PMOS transistor is connected with supply voltage with the source electrode of described second pull-up PMOS transistor, and the source ground of described first pulldown NMOS transistor and described second pulldown NMOS transistor; The drain electrode of described first pull-up PMOS transistor and described first pulldown NMOS transistor is connected to described first node, and the drain electrode of described second pull-up PMOS transistor and described second pulldown NMOS transistor is connected to described Section Point; The grid of described first pull-up PMOS transistor and described first pulldown NMOS transistor is connected to described Section Point, and the grid of described second pull-up PMOS transistor and described second pulldown NMOS transistor is connected to described first node.
7. SRAM memory cell array as claimed in claim 5, is characterized in that, described first writes transmission transistor, described second writes transmission transistor and described transmission transistor of reading is nmos pass transistor.
8. a SRAM memory, is characterized in that, described SRAM memory comprises the SRAM memory cell array according to any one of claim 1-7.
9. based on a control method for SRAM memory according to claim 8, it is characterized in that, described control method comprises:
When carrying out write operation to the selected person in multiple described storage unit, the write word line corresponding with described selected person is set to noble potential, peripheral circuit is delivered to described bit line to upper information as input; And
When read operation is carried out to the selected person in multiple described storage unit, the readout word line corresponding with described selected person is set to noble potential, and described sense bit line is set to noble potential, to be read the information in described selected person by described sense bit line.
10. control method as claimed in claim 9, it is characterized in that, described control method also comprises:
The described write word line corresponding with the selected person of first in described multiple described storage unit is set to noble potential, and the described readout word line corresponding with the selected person of second in described multiple storage unit is set to noble potential, to carry out write operation to the described first selected person and to carry out read operation to the described second selected person simultaneously simultaneously.
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