CN107508594A - Low-power consumption SRAM type FPGA - Google Patents
Low-power consumption SRAM type FPGA Download PDFInfo
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- CN107508594A CN107508594A CN201710574578.1A CN201710574578A CN107508594A CN 107508594 A CN107508594 A CN 107508594A CN 201710574578 A CN201710574578 A CN 201710574578A CN 107508594 A CN107508594 A CN 107508594A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
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- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
Low-power consumption SRAM type FPGA, is related to IC design technical field.The present invention includes memory cell array, row control line and row control line, memory cell array includes at least one low-power consumption memory cell group, each low-power consumption memory cell group is made up of the array storage unit of A, B two, the first alignment and the second alignment that wherein A array storage units have with each memory cell is connected in A row, the 3rd alignment and the 4th alignment that B array storage units have with each memory cell is connected in B row, the first alignment, the second alignment, the 3rd alignment, the 4th alignment are 4 articles of separate alignments；First switch is provided between first alignment and the 3rd alignment；Second switch is provided between first alignment and the 4th alignment；The 3rd switch is provided between second alignment and the 3rd alignment；The 4th switch is provided between second alignment and the 4th alignment.The present invention can effectively reduce the power consumption levels of whole chip.
Description
Technical field
The present invention relates to IC design technical field.
Background technology
In recent years, portable product equipment Market is constantly developed with stepped jump, and its disposal ability greatly promotes,
The application supported is more and more.Emerging portable product equipment Market also has every kind of equipment in an a trend i.e. series
Shipment amount reduce, but the customization function of different series equipment room increases.The used in amounts for FPGA is thus raised
Ask, and FPGA design may add chip cooling design difficulty because power problemses do not solve well, extend
R＆D cycle and radiating and the obvious increase of packaging cost, the reliability of chip is also decreased obviously, the drift of electrical parameter, even
Cause the failure of device, the collapse of system etc., therefore the FPGA reductions power consumption for designing low-power consumption can bring many benefits.Low-power consumption
How strong design have the integration capability for determining a system.
It is currently used all relatively simple when being applied to FPGA Low-power Technologies, current FPGA cores are not can solve
Piece runs into higher low power dissipation design problem on portable devices.
The content of the invention
The technical problem to be solved by the invention is to provide a kind of power consumption that can effectively reduce whole chip
FPGA。
It is low-power consumption SRAM type FPGA that the present invention, which solves the technical scheme that the technical problem uses, including memory cell
Battle array column and row control line and row control line, it is characterised in that memory cell array includes at least one low-power consumption memory cell
Group, each low-power consumption memory cell group are made up of the array storage unit of A, B two, and wherein A array storage units have with respectively being stored in A row
The the first alignment A1 and the second alignment A2, B array storage unit of unit connection have the 3rd row being connected with each memory cell in B row
Line B1 and the 4th alignment B2, the first alignment A1, the second alignment A2, the 3rd alignment B1, the 4th alignment B2 are 4 articles of separate row
Line；
First switch S0 is provided between first alignment A1 and the 3rd alignment B1；
Second switch S1 is provided between first alignment A1 and the 4th alignment B2；
The 3rd switch S2 is provided between second alignment A2 and the 3rd alignment B1；
The 4th switch S3 is provided between second alignment A2 and the 4th alignment B2.
In the memory cell, at least one memory cell contains six pipe memory modules and reads branch road module, institute
State first metal-oxide-semiconductor W1 and second metal-oxide-semiconductor W2, first metal-oxide-semiconductor W1 current input terminal of the reading branch road module including series connection and connect position
Line or alignment, the first metal-oxide-semiconductor W1 current output terminal connect the second metal-oxide-semiconductor W2 current input terminal, and the second metal-oxide-semiconductor W2 electric current is defeated
Go out end ground connection, the second metal-oxide-semiconductor W2 grid end is connected to any one grid common reference point in six pipe memory modules.
Six described pipe memory modules are six general in the prior art pipe storage organizations, wherein only two reference points expire
Foot connects the grid of two metal-oxide-semiconductors in six pipe storage organizations simultaneously, and the two reference points are referred to as into grid collective reference herein
Point.
The present invention can effectively reduce the power consumption levels of whole chip.Because SRAM memory cell is inside fpga chip
It is distributed more widely, use is very frequent, thus using novel sram memory cell fpga chip go for power consumption will
Ask on higher portable product and the well sold and in short supply space equipment of resource, to obtain the longer working time.With bit line charge
Recycling scheme reduces the voltage swing on signal wire when being written and read operation for memory cell, so as to reduce power consumption.This hair
Bright eight transistor memory units that six traditional transistor memory units are improved to Novel low power consumption, add independent reading branch road.By
In the presence for being independently read out branch road, the stability when memory cell is read is strengthened, that is, adds SNM (static noises
Tolerance limit) value.Also the unit is more suitable in extremely low operating at voltages simultaneously, for example is more suitable for setting for subthreshold value SRAM circuit
Meter.
Brief description of the drawings
Fig. 1 is that bit line charge recycles schematic diagram of mechanism outside the memory cell of the present invention.
Fig. 2 is the eight transistor memory unit basic circuit structure schematic diagrames of the present invention.
Fig. 3 is the first eight transistor memory unit detailed circuit structural representation of the present invention.
Fig. 4 is second of eight transistor memory unit detailed circuit structural representations of the present invention.
Embodiment
Referring to Fig. 1~3.
Present embodiment employs new bit line charge on write-in bit line and recycles scheme, so as to eliminate traditional scheme
In required reference voltage source.The voltage swing of write-in bit line is reduced, so as to reduce power consumption.Readout bit line and write-in bit line point
Open, the structure of stratification is used on readout bit line, effectively reduce the parasitic capacitance of readout bit line.Eliminate sensitive put simultaneously
Power consumption, area, the complexity for reducing circuit of big device.
The present invention carries bit line charge and recycles mechanism as shown in Figure 1.Including memory cell array, row control line and row control
Line processed, memory cell array include at least one low-power consumption memory cell group, and each low-power consumption memory cell group is arranged by A, B two
Memory cell is formed, the first alignment A1 and the second alignment that wherein A array storage units have with each memory cell is connected in A row
A2, B array storage unit have arranged with B in each memory cell the 3rd alignment B1 and the 4th alignment B2 for being connected, the first alignment A1, the
Two alignment A2, the 3rd alignment B1, the 4th alignment B2 are 4 articles of separate alignments；
First switch S0 is provided between first alignment A1 and the 3rd alignment B1；
Second switch S1 is provided between first alignment A1 and the 4th alignment B2；
The 3rd switch S2 is provided between second alignment A2 and the 3rd alignment B1；
The 4th switch S3 is provided between second alignment A2 and the 4th alignment B2.
Specifically, memory cell array divided by column is one group, such as Fig. 1 two-by-two by the present invention, two memory cell
Two bit lines of row are respectively BL0 and BL0_N and BL1 and BL1_N, using 4 nmos switch pipe S0-S4 by BL1 and BL1_N points
BL0 and BL0_N are not connected to it.Bit line BL1 and BL1_N are connected to the NMOS tube for being pre-charged to GND, when it is opened
Can be GND by BL1 and BL1_N voltage pre-charges.And the PMOS for being pre-charged to VDD is then connected with bit line BL0 and BL0_N respectively,
Can be VDD by BL0 and BL0_N voltage pre-charges when it is opened.
When some NMOS tube is opened in switching tube S0-S4, by being pre-charged PMOS on BL0 and BL0_N
With the length-width ratio control and adjustment that NMOS tube and S0-S4 switching tubes are pre-charged on BL1 and BL1_N, it is possible to by unlatching
Switching tube both ends control of Electric potentials is approximate 0.5VDD.This is just that discharge and recharge of the deposit of follow-up data on bit line reduces pendulum
Width, so as to reduce power consumption.Exemplified by writing data " 01 ", illustrate the process of circuit write operation.The preliminary filling cycle, bit line BL1 and
BL1_N is pre-charged to GND, BL0 and BL0_N and is pre-charged to VDD.Write cycle, 2bit data can be produced by decoder
Raw 4 kinds of states, it is corresponding to turn on S3 after write-in data " 01 " are by decoder, so as to make bit line BL1_N and BL0_N phase
Even.BL1_N and BL0_N forms approximate 0.5VDD current potential, the GND before BL1 holdings, the VDD before BL0 holdings after connection.
Approximate 0.5VDD voltage difference is so all formd on two groups of bit lines.Write wordline WWL afterwards to open, because sram cell is adopted
With the structure of 2 phase inverter rings, 0.5VDD voltage difference is written in unit and can be reconstructed, it will with GND and VDD stable state
Storage is in the cells.
In the memory cell of the present invention, at least one memory cell contains six pipe memory modules and reads branch road mould
Block, the branch road module that reads include the first metal-oxide-semiconductor W1 and the second metal-oxide-semiconductor W2 of series connection, the first metal-oxide-semiconductor W1 current input terminal
Line or alignment are connect, the first metal-oxide-semiconductor W1 current output terminal connects the second metal-oxide-semiconductor W2 current input terminal, the second metal-oxide-semiconductor W2 electricity
Output head grounding is flowed, the second metal-oxide-semiconductor W2 grid end is connected to any one grid common reference point in six pipe memory modules.Six
Pipe memory module is 6 general in the prior art pipe storage organizations, wherein only two reference points meet to connect the storage of 6 pipes simultaneously
The two reference points are referred to as grid common reference point by the grid of two metal-oxide-semiconductors in structure herein, such as the X1 and X2 in Fig. 2.
The basic circuit structure of novel sram memory cell that the present invention is carried as shown in Fig. 2 its with traditional 6T-SRAM most
Big difference is the increase in independent reading branch road, i.e. nmos pass transistor W1, W2.The main purpose so designed is to increase
Stability when SRAM is read, that is, the data that external signal stores without interference with internal node when reading.It can be appreciated that increase
Add SNM (static noise margin) value, i.e. SNM values when 8T-SRAM is read, equivalent to the SNM values under 6T-SRAM hold modes
(Hold SNM).Because reading and writing branch road separates, the raising of the stability of data is read, so 8T-SRAM is more suitable in extremely low electricity
Work is depressed, for example is more suitable for the small SRAM circuit design of subthreshold value, leakage current.
As shown in Figure 3,4, wherein Fig. 3 and Fig. 4 difference is：In Fig. 3 with write-in wordline WWL be connected transistor N3,
N6 is nmos pass transistor；Transistor P3, the P6 being connected in Fig. 4 with writing wordline WWL_N are PMOS transistor.The mesh so designed
Be use different types of unit for different bit-line voltage scopes, avoid threshold value from losing.For GND to 0.5VDD electricity
The bit line of scope is pressed, still using unit as shown in Figure 3, ensures that " strong 0 " signal enters in cell units at least one.Pin
To the bit line in 0.5VDD to vdd voltage scope, using unit as shown in Figure 4.PMOS transistor P3 and P6 are used, so
On the bit line of the 0.5VDD and VDD amplitudes of oscillation, it will having one, " strong 1 " signal enters in cell units.
Wordline is connected with P6 due to using PMOS transistor P3 instead, so wordline WWL_N signals logically need to be WWL
Reverse signal, this needs to add a reverser in the wordline of every row to generate reverse signal.Often row adds a phase inverter
To the expense of area and power consumption and little, can be ignored.This is equal to simultaneously is divided into two sections by wordline, is classified similar to bit line
Thinking, long line is divided into two, reduces the parasitic capacitance during upset of each wordline to a certain extent, also just reduces
Power consumption.
Claims (2)
1. low-power consumption SRAM type FPGA, including memory cell array, word control line and position control line, it is characterised in that storage is single
Element array includes at least one low-power consumption memory cell group, and each low-power consumption memory cell group is by the array storage unit structure of A, B two
Into the first alignment (A1) and the second alignment (A2) that wherein A array storage units have with each memory cell is connected in A row, B row are deposited
The 3rd alignment (B1) and the 4th alignment (B2) that storage unit has with each memory cell is connected in B row, the first alignment (A1), second
Alignment (A2), the 3rd alignment (B1), the 4th alignment (B2) are 4 articles of separate alignments；
First switch (S0) is provided between first alignment (A1) and the 3rd alignment (B1)；
Second switch (S1) is provided between first alignment (A1) and the 4th alignment (B2)；
The 3rd switch (S2) is provided between second alignment (A2) and the 3rd alignment (B1)；
The 4th switch (S3) is provided between second alignment (A2) and the 4th alignment (B2).
2. low-power consumption SRAM type FPGA as claimed in claim 1, it is characterised in that in the memory cell, at least one
Memory cell contains six pipe memory modules and reads branch road module, and the branch road module that reads includes the first metal-oxide-semiconductor of series connection
(W1) and the second metal-oxide-semiconductor (W2), the current input terminal of the first metal-oxide-semiconductor (W1) connect bit line or alignment, the electric current of the first metal-oxide-semiconductor (W1)
The current input terminal of output the second metal-oxide-semiconductor of termination (W2), the current output terminal ground connection of the second metal-oxide-semiconductor (W2), the second metal-oxide-semiconductor (W2)
Grid end be connected to any one grid common reference point in six pipe memory modules.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710574578.1A CN107508594A (en) | 2017-07-14 | 2017-07-14 | Low-power consumption SRAM type FPGA |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710574578.1A CN107508594A (en) | 2017-07-14 | 2017-07-14 | Low-power consumption SRAM type FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111723045A (en) * | 2020-06-19 | 2020-09-29 | 成都华微电子科技有限公司 | Multifunctional memory circuit and integrated circuit chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034533A (en) * | 2011-01-11 | 2011-04-27 | 中国科学院半导体研究所 | Static random storage unit with resetting function |
| CN102446545A (en) * | 2011-12-31 | 2012-05-09 | 上海交通大学 | Design method of static random access memory suitable for low-power chip |
| US20140050025A1 (en) * | 2012-08-15 | 2014-02-20 | Aplus Flash Technology, Inc | Low-voltage fast-write pmos nvsram cell |
| US20150340090A1 (en) * | 2013-12-06 | 2015-11-26 | Empire Technology Development Llc | Non-volatile sram with multiple storage states |
| CN105702281A (en) * | 2015-12-31 | 2016-06-22 | 西安交通大学 | SRAM half-select disturb elimination structure based on hierarchical bit line structure |
-
2017
- 2017-07-14 CN CN201710574578.1A patent/CN107508594A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034533A (en) * | 2011-01-11 | 2011-04-27 | 中国科学院半导体研究所 | Static random storage unit with resetting function |
| CN102446545A (en) * | 2011-12-31 | 2012-05-09 | 上海交通大学 | Design method of static random access memory suitable for low-power chip |
| US20140050025A1 (en) * | 2012-08-15 | 2014-02-20 | Aplus Flash Technology, Inc | Low-voltage fast-write pmos nvsram cell |
| US20150340090A1 (en) * | 2013-12-06 | 2015-11-26 | Empire Technology Development Llc | Non-volatile sram with multiple storage states |
| CN105702281A (en) * | 2015-12-31 | 2016-06-22 | 西安交通大学 | SRAM half-select disturb elimination structure based on hierarchical bit line structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111723045A (en) * | 2020-06-19 | 2020-09-29 | 成都华微电子科技有限公司 | Multifunctional memory circuit and integrated circuit chip |
| CN111723045B (en) * | 2020-06-19 | 2023-05-16 | 成都华微电子科技股份有限公司 | Multifunctional memory circuit and integrated circuit chip |
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