CN104637528B - SRAM memory cell array, SRAM memory and its control method - Google Patents
SRAM memory cell array, SRAM memory and its control method Download PDFInfo
- Publication number
- CN104637528B CN104637528B CN201310552338.3A CN201310552338A CN104637528B CN 104637528 B CN104637528 B CN 104637528B CN 201310552338 A CN201310552338 A CN 201310552338A CN 104637528 B CN104637528 B CN 104637528B
- Authority
- CN
- China
- Prior art keywords
- memory cell
- transistor
- bit line
- reading
- sram memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Abstract
The present invention provides a kind of SRAM memory cell array, SRAM memory and its control method.The SRAM memory cell array includes：Multiple wordline pair arranged along line direction, the wordline is to including write word line and readout word line；The bit line pair arranged along column direction, the bit line is to including the first bit line and the second bit line；Multiple memory cell between the wordline pair and the bit line pair, each memory cell are respectively connecting to the corresponding wordline pair and the bit line pair, and the memory cell includes reading end；And unit is read, the reading unit includes a reading transistor and a sense bit line, and the sense bit line is connected to the reading end of multiple memory cell by the reading transistor.Number of transistors is reduced according to the SRAM memory cell array of the present invention, improves stability.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of SRAM memory cell array, there is the SRAM to deposit
The SRAM memory of storage unit array and the control method of the SRAM memory.
Background technology
With the continuous development of digital integrated electronic circuit, the memory integrated on piece has become group important in digital display circuit
Into part.SRAM（Static Random Access Memory, static RAM）With its low-power consumption, high speed
Advantage turns into important component indispensable in on-chip memory.As long as SRAM, which is its power supply, can preserve data, without
Constantly it is refreshed.
SRAM overall structures can be divided into memory cell array and peripheral circuit two parts.In sram, memory cell
It is most basic, most important part.The quantity of the memory cell included in array and the stability of memory cell are to influence
Two key factors of SRAM performances.The quantity of memory cell is more, and storage capacity is higher, and the size of sram chip is bigger.
But the increase of the size of sram chip is disagreed with consumer for portable requirement.SRAM main flow unit at present
For 6T, as shown in Figure 1.The 6T sram cells 100 include two identical and cross-linked phase inverters 110,120.Bit line（BL）
Pass through two transmission transistors to 130,140（PG）150th, 160 memory node Q1, Q2 are connected to.In 6T SRAM, data are deposited
Storage node Q1, Q2 are directly connected to bit line to upper by transmission transistor 150 and 160.During reading, due to transmitting crystal
Partial pressure effect between pipe and pull-down transistor can make the data of memory node be interfered, in addition, the data of memory node
The influence of external noise is highly susceptible to so as to cause logic error, influences the stability of memory cell.
Existing 8T SRAM memory cells 200（As shown in Figure 2）Including two identical and cross-linked phase inverters 210,
220.Bit line（BL）Pass through two transmission transistors to 230,240（PG）250th, 260 memory node Q3, sense bit line are connected to
（RBL）270 by reading transmission transistor（RPG）280 and reading transistor（RPD）290 are connected to memory node Q4.8T structures
Although SRAM memory cell 200 improves stability, the quantity increase of transistor, the size of memory cell array also accordingly increases
Add, be unfavorable for the raising of integrated circuit integrated level and the miniaturization of chip size.
Therefore, it is necessary to propose that a kind of SRAM memory cell array, the SRAM with the SRAM memory cell array store
The control method of device and the SRAM memory, to solve problems of the prior art.
The content of the invention
In order to solve problems of the prior art, the present invention provides a kind of SRAM memory cell array.The SRAM is deposited
Storage unit array includes：Multiple wordline pair arranged along line direction, the wordline is to including write word line and readout word line；Along column direction
The bit line pair of arrangement, the bit line is to including the first bit line and the second bit line；Between the wordline pair and the bit line pair
Multiple memory cell, each memory cell be respectively connecting to corresponding to the wordline pair and the bit line pair, it is described to deposit
Storage unit includes reading end；And unit is read, the reading unit includes a reading transistor and a sense bit line, the sense bit line
The reading end of multiple memory cell is connected to by the reading transistor.
Preferably, the SRAM memory cell array also includes interconnection line, and the reading end of the memory cell is connected to institute
Interconnection line is stated, to be connected to the reading transistor by the interconnection line.
Preferably, the grid of the reading transistor is connected to the reading end of the memory cell；The reading transistor
Drain electrode be connected to the sense bit line；The source ground of the reading transistor.
Preferably, the reading transistor is nmos pass transistor.
Preferably, the memory cell includes：First phase inverter and the second phase inverter, first phase inverter and described
Two phase inverters are connected between first node and section point, wherein the input of first phase inverter and described second anti-phase
The output end of device is connected to the first node, and the output end of first phase inverter and the input of second phase inverter connect
It is connected to the section point；First writes transmission transistor and second writes transmission transistor, and described first writes transmission transistor and institute
State the second source electrode for writing transmission transistor to be connected with the first node and the section point respectively, drain electrode is respectively with described the
One bit line connects with second bit line, and grid connects with corresponding write word line respectively；And transmission transistor is read, it is described to read to pass
The source electrode of defeated transistor is connected with one in the first node and the section point, and drain electrode connects with the reading transistor
Connect, grid is connected with the readout word line.
Preferably, first phase inverter includes the first pullup PMOS transistor and the first pulldown NMOS transistor, described
Second phase inverter includes the second pullup PMOS transistor and the second pulldown NMOS transistor, wherein the first pull-up PMOS crystal
Pipe and the source electrode of second pullup PMOS transistor are connected with supply voltage, and first pulldown NMOS transistor and described
The source ground of second pulldown NMOS transistor；First pullup PMOS transistor and first pulldown NMOS transistor
Drain electrode is connected to the first node, and the drain electrode of second pullup PMOS transistor and second pulldown NMOS transistor connects
It is connected to the section point；The grid of first pullup PMOS transistor and first pulldown NMOS transistor is connected to institute
Section point is stated, and the grid of second pullup PMOS transistor and second pulldown NMOS transistor is connected to described
One node.
Preferably, described first write transmission transistor, described second write transmission transistor and it is described reading transmission transistor be
Nmos pass transistor.
According to another aspect of the present invention, a kind of SRAM memory is also provided.The SRAM memory includes above-mentioned
A kind of SRAM memory cell array.
According to a further aspect of the invention, a kind of control method based on above-mentioned SRAM memory is also provided.The control
Method processed includes：When carrying out write operation to the selected person in multiple memory cell, corresponding with the selected person it will write
Line is arranged to high potential, and peripheral circuit is delivered to the bit line to upper information as input；It is and single to multiple storages
When selected person in member carries out read operation, readout word line corresponding with the selected person is arranged to high potential, and by the read bit
Line is arranged to high potential, to read the information in the selected person by the sense bit line.
Preferably, the control method also includes：Will be corresponding with the first selected person in the multiple memory cell
The write word line be arranged to high potential, and simultaneously by the reading corresponding with the second selected person in the multiple memory cell
Wordline is arranged to high potential, to carry out write operation to the described first selected person simultaneously and to carry out reading behaviour to the described second selected person
Make.
It is few according to the number of transistors that the memory cell of the SRAM memory cell array of the present invention includes, and a row storage is single
Member only acts on multiple memory cell with a reading transistor, reduces the quantity of transistor in SRAM memory cell array, from
And the size of SRAM memory cell array is reduced, and then reduce the size of sram chip.Meanwhile the write operation in memory cell
Path separates with read operation path, can improve β ratios and γ ratios simultaneously, and improves static noise margin, so as to improve
Stability.
A series of concept of reduced forms is introduced in the content of the invention, this will be in specific embodiment part further
Describe in detail.Present invention part be not meant to attempt the key feature for limiting technical scheme claimed and
Essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
Below in conjunction with accompanying drawing, advantages and features of the invention are described in detail.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.In the accompanying drawings,
Fig. 1 is the schematic diagram of existing 6T SRAM memory cells；
Fig. 2 is the schematic diagram of existing 8T SRAM memory cells；
Fig. 3 is the schematic diagram according to the SRAM memory cell array of one embodiment of the present of invention；And
Fig. 4 is the schematic diagram of the SRAM memory cell in the SRAM memory cell array shown in Fig. 3.
Embodiment
Next, the present invention will be more fully described by with reference to accompanying drawing, shown in the drawings of embodiments of the invention.But
It is that the present invention can be implemented in different forms, and should not be construed as being limited to embodiments presented herein.On the contrary, provide
These embodiments will make disclosure thoroughly and complete, and will fully convey the scope of the invention to those skilled in the art.
In accompanying drawing, for clarity, the size and relative size in Ceng He areas may be exaggerated.Same reference numerals represent phase from beginning to end
Same element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other
When element or layer, its can directly in other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.In the accompanying drawings, in order to clear
For the sake of, the size and relative size in Ceng He areas may be exaggerated.And make identical element is presented with like reference characters.
According to an aspect of the present invention, there is provided a kind of SRAM memory cell array.As shown in figure 3, SRAM memory cell
Array 300 includes：Multiple wordline along line direction arrangement to, along the bit line of column direction arrangement to, multiple memory cell 310 and
Read unit 320.Here only the array comprising an array storage unit 310 is described.It can be included in each SRAM memory
Memory cell array 300 as multiple row.Multiple such memory cell arrays 300 can arrange or with other along line direction
Mode arranges.
The wordline of the memory cell array 300 is to including write word line（WWL）330 and readout word line（RWL）340, bit line is to bag
Include the first bit line（BL）350 and second bit line（BLB）360.The quantity of memory cell 310 corresponds to the quantity of wordline pair, namely
The quantity of write word line 330 or readout word line 340.Each memory cell 310 is connected between each wordline pair and bit line pair.Such as
Shown in Fig. 3, memory cell 310 is connected between write word line 330 and the bit line 350 of readout word line 340 and first and the second bit line 360.
Each memory cell 310 includes write-in end and reads end, and write-in end is connected to the first bit line 350 and the second bit line 360, reads
End, which is connected to, reads unit 320.The current potential of write word line 330 and readout word line 340 could be arranged to high potential or low potential, for selecting
Corresponding memory cell 310, control write operation and the read operation of corresponding memory cell 310.In one according to the present invention
In embodiment, one in write word line 330 could be arranged to high potential, and other write word lines 330 could be arranged to low potential, now
Can pair progress of a memory cell 310 write operation corresponding with the write word line 330 of the high potential.First bit line 350 and second
Line 360 can receive peripheral circuit（It is not shown）The voltage of transmission is as input, so as to write information into memory cell 310.
Reading unit 320 includes a reading transistor 321 and a sense bit line（RBL）322, the sense bit line 322 is brilliant by reading
Body pipe 321 is connected to the reading end of multiple memory cell 310.The plurality of memory cell 310 is located at same row.Therefore, only pass through
One can of reading transistor 321 realizes the read operation of multiple memory cell 310, it is possible to reduce the crystalline substance of SRAM memory cell array
Body pipe quantity, so as to reduce the size of SRAM memory cell array, and then reduce the size of sram chip.Carried in the present invention
In this embodiment supplied, when needing to carry out read operation, pass through the selected memory cell for needing to carry out read operation of readout word line 340
310, such as readout word line 340 corresponding to the memory cell 310 of progress read operation will be needed to be arranged to high potential, then pass through read bit
Line 322 carries out read operation to selected memory cell 310.
The connection between multiple memory cell 310 and reading transistor 321, the SRAM memory cell array also wrap for convenience
Include interconnection line（Inter line, IL）370, the reading end of multiple memory cell 310 is connected to interconnection line 370, with by mutual
Line 370 is connected to reading transistor 321.Therefore, it is brilliant can be connected to reading by an interconnection line 370 for multiple memory cell 310
Body pipe 321, overall routing can be facilitated.
Preferably, the grid of reading transistor 321 is connected to the reading end of memory cell 310；The drain electrode connection of reading transistor
To sense bit line 322；The source ground of reading transistor.In such a connected mode, when carrying out read operation, with memory cell 310
The connection of reading end be transistor grid, therefore voltage pulsation on sense bit line 322 and external noise will not be single to storage
Member 310 has an impact, thus adds read noise tolerance limit, improves the stability of memory cell.In the reading of memory cell 310
End is connected in the preferred embodiment of reading transistor 321 by interconnection line 370, and the grid of reading transistor 321 is by being connected to mutually
Line 370 and be connected to the reading end of memory cell 310.
Preferably, according to one embodiment of present invention, reading transistor 321 is nmos pass transistor.Nmos pass transistor is main
Carrier be electronics, mobility is high, and electric current is relatively large, convenient to carry out read operation.Certainly, the present invention is not intended to reading transistor
321 type is defined.In the unshowned other embodiment of the present invention, reading transistor 321 can also be other kinds of
Transistor, such as PMOS transistor.
The size of memory cell 310 largely determines the size of sram chip, therefore, it is necessary to makes memory cell
310 size is small as much as possible.Memory cell 310 can be made up of reverse unit, for the current potential of memory node is reverse.Such as
Shown in Fig. 3, memory cell 310 includes the first phase inverter 311, the second phase inverter 312, first writes transmission transistor 313, second writes
Transmission transistor 314 and reading transmission transistor 315.Memory cell 310 is discussed in detail below in conjunction with Fig. 3-Fig. 4.
As shown in figure 3, the first phase inverter 311 and the second phase inverter 312 be connected to first node Q5 and section point Q6 it
Between, wherein the output end of the input of the first phase inverter 311 and the second phase inverter 312 is connected to first node Q5, first is anti-phase
The output end of device 311 and the input of the second phase inverter 312 are connected to section point Q6.The first of the memory cell 310 is anti-phase
The phase inverter 312 of device 311 and second forms latch cicuit, to latch memory node Q5 and Q6 data.
First phase inverter 311 and the second phase inverter 312 can be cmos cell.For example, in a reality according to the present invention
Apply in example, as shown in figure 4, the first phase inverter 311 includes the first pullup PMOS transistor（PU）311A and the first pull-down NMOS are brilliant
Body pipe（PD）311B, the second phase inverter 312 include the second pullup PMOS transistor（PU）312A and the second pulldown NMOS transistor
（PD）312B, wherein the first pullup PMOS transistor 311A and the second pullup PMOS transistor 312A source electrode connect with supply voltage
Connect, and the first pulldown NMOS transistor 311B and the second pulldown NMOS transistor 312B source ground；First pull-up PMOS is brilliant
Body pipe 311A and the first pulldown NMOS transistor 311B drain electrode are connected to first node Q5, the second pullup PMOS transistor 312A
Drain electrode with the second pulldown NMOS transistor 312B is connected to section point Q6；Under first pullup PMOS transistor 311A and first
Nmos pass transistor 311B grid is drawn to be connected to section point Q6, and the second pullup PMOS transistor 312A and the second pull-down NMOS
The pipe B of crystal 312 grid is connected to first node Q5.The memory cell 310 includes 7 transistors, with 8 transistor-types
SRAM is compared, and its unit size reduces, and further reduces sram chip size.
Further, first write transmission transistor 313 and second write the source electrode of transmission transistor 314 respectively with first node Q5
Connected with section point Q6, drain electrode is connected with the first bit line 350 and the second bit line 360 respectively, and grid writes with corresponding respectively
Line 330 connects.The drain electrode for reading transmission transistor 315 is connected with reading transistor 321.It should be appreciated that connection mentioned here can be with
To be directly connected to, or be indirectly connected with.According to a preferred embodiment of the present invention, transmission transistor 315 is read
Drain electrode is connected to interconnection line 370, to be connected to reading transistor 321 by interconnection line 370.Read transmission transistor 315 grid with
Readout word line 340 is connected, and source electrode is connected with one in first node Q5 and section point Q6, in an implementation according to the present invention
In example, the source electrode for reading transmission transistor 315 is connected with section point Q6.
Preferably, first write transmission transistor 313, second write transmission transistor 314 and read transmission crystal 315 pipe be NMOS
Transistor.Likewise, as described above, the main carrier of nmos pass transistor is electronics, and mobility is high, and electric current is relatively
Greatly, it is convenient to carry out signal transmission.Certainly, transmission transistor 313 and second is write to first writes transmission transistor 314 to the present invention unintentionally
And the type of reading transmission transistor 315 is defined.In the unshowned other embodiment of the present invention, first writes transmission crystal
Pipe 313 and second write transmission transistor 314 and read transmission transistor 315 can also be other kinds of transistor, such as
PMOS transistor.
According to another aspect of the present invention, a kind of SRAM memory is also provided.The SRAM memory includes as described above
Any SRAM memory cell array.Multiple this SRAM memory cell arrays can be included in the SRAM memory, it is more
Individual this SRAM memory cell array arranges along line direction.It is small according to the SRAM of present invention memory cell size, thus
Sram chip size is small.Improve memory cell stability simultaneously.
According to another aspect of the invention, a kind of control method based on above-mentioned SRAM memory is also provided.This method
Including：
When carrying out write operation to the selected person in multiple memory cell 310, write corresponding with selected memory cell 310
Wordline 330 is arranged to high potential, and peripheral circuit is delivered to bit line pair（Including the first bit line 350 and the second bit line 360）On letter
Breath is as input., will be corresponding with selected memory cell 310 when carrying out read operation to the selected person in multiple memory cell 310
Readout word line 340 be arranged to high potential, read information in selected memory cell to pass through sense bit line 322.For example, in the reality
Apply in example, when carrying out read operation, sense bit line 322 first can be arranged to high potential.Because the information of memory node can be to reading
The current potential of bit line 322 has an impact, therefore can compare the read output signal on the sense bit line 322 by external reference circuit, sentences
Storage information on disconnected memory node.
Based on above-mentioned SRAM memory, it is preferable that the control method also includes carrying out multiple memory cell 310 simultaneously
Read-write operation.Will with 310 in multiple memory cell in the corresponding write word line of the first selected person be arranged to high potential, by the
One bit line 350 and the second bit line 360 carry out write operation to the first selected person.Simultaneously by with the in multiple memory cell 310
Readout word line corresponding to two selected persons is arranged to high potential, and read operation is carried out to the second selected person by reading unit 320.Wherein
One selected person and the second selected person are different memory cell.For example, sense bit line 322 is arranged to high potential, by reference to electricity
The read output signal on the sense bit line 322 is compared on road, so as to judge the storage information of the memory node.Can be with by the control method
Write operation is carried out to the first selected person simultaneously and write operation is carried out to the second selected person, improves access speed.
It is few according to the number of transistors that the memory cell 310 of the SRAM memory cell array 300 of the present invention includes, and a row
Memory cell 310 only acts on multiple memory cell 310 with a reading transistor 321, reduces in SRAM memory cell array
The quantity of transistor, so as to reduce the size of SRAM memory cell array, and then reduce the size of sram chip.Meanwhile deposit
Write operation path and read operation path in storage unit 310 separate, and can improve β ratios and γ ratios simultaneously, and improve static state
Noise margin, so as to improve stability.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of SRAM memory cell array, it is characterised in that the SRAM memory cell array includes：
Multiple wordline pair arranged along line direction, the wordline is to including write word line and readout word line；
The bit line pair arranged along column direction, the bit line is to including the first bit line and the second bit line；
Multiple memory cell between the wordline pair and the bit line pair, each memory cell are respectively connecting to pair
The wordline pair answered and the bit line pair, the memory cell include reading end；And
Unit is read, the reading unit includes a reading transistor and a sense bit line, the sense bit line pass through the reading transistor
The reading end of multiple memory cell is connected to, only to realize multiple storages by a reading transistor
The read operation of unit.
2. SRAM memory cell array as claimed in claim 1, it is characterised in that the SRAM memory cell array also includes
Interconnection line, the reading end of the memory cell are connected to the interconnection line, to be connected to the reading crystal by the interconnection line
Pipe.
3. SRAM memory cell array as claimed in claim 1, it is characterised in that the grid of the reading transistor is connected to institute
State the reading end of memory cell；The drain electrode of the reading transistor is connected to the sense bit line；The source electrode of the reading transistor
Ground connection.
4. SRAM memory cell array as claimed in claim 1, it is characterised in that the reading transistor is nmos pass transistor.
5. SRAM memory cell array as claimed in claim 1, it is characterised in that the memory cell includes：
First phase inverter and the second phase inverter, first phase inverter and second phase inverter are connected to first node and second
Between node, wherein the output end of the input of first phase inverter and second phase inverter is connected to the first segment
Point, the output end of first phase inverter and the input of second phase inverter are connected to the section point；
First writes transmission transistor and second writes transmission transistor, and described first writes transmission transistor and described second to write transmission brilliant
The source electrode of body pipe is connected with the first node and the section point respectively, drain electrode respectively with first bit line and described the
Two bit lines connect, and grid connects with corresponding write word line respectively；And
Read transmission transistor, the source electrode for reading transmission transistor and a company in the first node and the section point
Connect, drain electrode is connected with the reading transistor, and grid is connected with the readout word line.
6. SRAM memory cell array as claimed in claim 5, it is characterised in that first phase inverter includes the first pull-up
PMOS transistor and the first pulldown NMOS transistor, second phase inverter include the second pullup PMOS transistor and the second drop-down
Nmos pass transistor,
The source electrode of wherein described first pullup PMOS transistor and second pullup PMOS transistor is connected with supply voltage, and
The source ground of first pulldown NMOS transistor and second pulldown NMOS transistor；The first pull-up PMOS crystal
The drain electrode of pipe and first pulldown NMOS transistor is connected to the first node, second pullup PMOS transistor and institute
The drain electrode for stating the second pulldown NMOS transistor is connected to the section point；First pullup PMOS transistor and described first
The grid of pulldown NMOS transistor is connected to the section point, and second pullup PMOS transistor and second drop-down
The grid of nmos pass transistor is connected to the first node.
7. SRAM memory cell array as claimed in claim 5, it is characterised in that described first writes transmission transistor, described
Second write transmission transistor and it is described reading transmission transistor be nmos pass transistor.
8. a kind of SRAM memory, it is characterised in that the SRAM memory is included as any one of claim 1-7
SRAM memory cell array.
A kind of 9. control method of the SRAM memory based on described in claim 8, it is characterised in that the control method bag
Include：
When carrying out write operation to the selected person in multiple memory cell, write word line corresponding with the selected person is arranged to
High potential, peripheral circuit are delivered to the bit line to upper information as input；And
When carrying out read operation to the selected person in multiple memory cell, readout word line corresponding with the selected person is arranged to
High potential, and the sense bit line is arranged to high potential, to read the information in the selected person by the sense bit line.
10. control method as claimed in claim 9, it is characterised in that the control method also includes：
The write word line corresponding with the first selected person in the multiple memory cell is arranged to high potential, and simultaneously
The readout word line corresponding with the second selected person in the multiple memory cell is arranged to high potential, so as to simultaneously to described
First selected person carries out write operation and carries out read operation to the described second selected person.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310552338.3A CN104637528B (en) | 2013-11-07 | 2013-11-07 | SRAM memory cell array, SRAM memory and its control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310552338.3A CN104637528B (en) | 2013-11-07 | 2013-11-07 | SRAM memory cell array, SRAM memory and its control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104637528A CN104637528A (en) | 2015-05-20 |
| CN104637528B true CN104637528B (en) | 2017-12-05 |
Family
ID=53216182
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310552338.3A Active CN104637528B (en) | 2013-11-07 | 2013-11-07 | SRAM memory cell array, SRAM memory and its control method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104637528B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106558334B (en) * | 2015-09-24 | 2020-08-25 | 中芯国际集成电路制造(上海)有限公司 | SRAM memory cell, SRAM memory and control method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154442A (en) * | 2006-09-27 | 2008-04-02 | 台湾积体电路制造股份有限公司 | Two-port sram with a high speed sensing scheme |
| CN101243518A (en) * | 2005-08-11 | 2008-08-13 | 德克萨斯仪器股份有限公司 | SRAM cell with separate read-write circuitry |
| CN103295624A (en) * | 2012-02-22 | 2013-09-11 | 德克萨斯仪器股份有限公司 | High performance two-port sram architecture using 8T high performance single-port bit cell |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7525868B2 (en) * | 2006-11-29 | 2009-04-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple-port SRAM device |
-
2013
- 2013-11-07 CN CN201310552338.3A patent/CN104637528B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101243518A (en) * | 2005-08-11 | 2008-08-13 | 德克萨斯仪器股份有限公司 | SRAM cell with separate read-write circuitry |
| CN101154442A (en) * | 2006-09-27 | 2008-04-02 | 台湾积体电路制造股份有限公司 | Two-port sram with a high speed sensing scheme |
| CN103295624A (en) * | 2012-02-22 | 2013-09-11 | 德克萨斯仪器股份有限公司 | High performance two-port sram architecture using 8T high performance single-port bit cell |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104637528A (en) | 2015-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107403635B (en) | Memory macro and method of operating the same | |
| KR100594927B1 (en) | Semiconductor memory device | |
| US7639525B2 (en) | Semiconductor memory device | |
| US7813161B2 (en) | Dual port SRAM with dedicated read and write ports for high speed read operation and low leakage | |
| TWI485705B (en) | Memory cells having a row-based read and/or write support circuitry | |
| US7969811B2 (en) | Semiconductor memory device highly integrated in direction of columns | |
| US20120063211A1 (en) | Method for improving writability of sram memory | |
| CN104952482A (en) | Semiconductor storage device | |
| CN104599700B (en) | High density storage structure | |
| CN202275603U (en) | Device and chip for memory writing operation | |
| CN104637532B (en) | SRAM memory cell arrays, SRAM memories and its control method | |
| CN105070315B (en) | SRAM memory cell, SRAM circuit and its reading/writing method | |
| CN101009135A (en) | Semiconductor memory device having reduced voltage coupling between bit lines | |
| JP2006093696A (en) | Integrated circuit memory device | |
| US8611169B2 (en) | Fine granularity power gating | |
| US8988920B2 (en) | Semiconductor memory device | |
| CN101727973B (en) | Semiconductor memory apparatus | |
| CN106558334A (en) | A kind of SRAM memory cell, SRAM memory and its control method | |
| JP2002015579A (en) | Architecture for high-speed memory circuit having relatively large number of internal data lines | |
| CN105097017A (en) | SRAM (static random access memory) storage unit, SRAM memory and control method therefor | |
| US9928182B2 (en) | Direct interface between SRAM and non-volatile memory providing space efficiency by matching pitch in both memories | |
| CN104637528B (en) | SRAM memory cell array, SRAM memory and its control method | |
| CN104658597A (en) | Three-dimensional (3-D) write assist scheme for memory cells | |
| Chang et al. | A 0.45-V 300-MHz 10T flowthrough SRAM with expanded write/read stability and speed-area-wise array for sub-0.5-V chips | |
| CN104637527B (en) | SRAM memory cell array, SRAM memory and its control method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |