TWI223811B - Semiconductor memory and method for controlling the same - Google Patents

Semiconductor memory and method for controlling the same Download PDF

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Publication number
TWI223811B
TWI223811B TW092123937A TW92123937A TWI223811B TW I223811 B TWI223811 B TW I223811B TW 092123937 A TW092123937 A TW 092123937A TW 92123937 A TW92123937 A TW 92123937A TW I223811 B TWI223811 B TW I223811B
Authority
TW
Taiwan
Prior art keywords
mode
burst
semiconductor memory
address
signal
Prior art date
Application number
TW092123937A
Other languages
English (en)
Chinese (zh)
Other versions
TW200409120A (en
Inventor
Shinya Fujioka
Shinichi Yamada
Kotoku Sato
Jun Ohno
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of TW200409120A publication Critical patent/TW200409120A/zh
Application granted granted Critical
Publication of TWI223811B publication Critical patent/TWI223811B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
TW092123937A 2002-09-13 2003-08-29 Semiconductor memory and method for controlling the same TWI223811B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002268975A JP4111789B2 (ja) 2002-09-13 2002-09-13 半導体記憶装置の制御方法及び半導体記憶装置

Publications (2)

Publication Number Publication Date
TW200409120A TW200409120A (en) 2004-06-01
TWI223811B true TWI223811B (en) 2004-11-11

Family

ID=31944505

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092123937A TWI223811B (en) 2002-09-13 2003-08-29 Semiconductor memory and method for controlling the same

Country Status (6)

Country Link
US (2) US6842391B2 (enExample)
EP (1) EP1400978B1 (enExample)
JP (1) JP4111789B2 (enExample)
KR (1) KR100922412B1 (enExample)
CN (1) CN100369156C (enExample)
TW (1) TWI223811B (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4111789B2 (ja) * 2002-09-13 2008-07-02 富士通株式会社 半導体記憶装置の制御方法及び半導体記憶装置
EP1418589A1 (en) * 2002-11-06 2004-05-12 STMicroelectronics S.r.l. Method and device for timing random reading of a memory device
JP4386706B2 (ja) * 2003-11-06 2009-12-16 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
TWI260019B (en) * 2004-05-21 2006-08-11 Fujitsu Ltd Semiconductor memory device and memory system
JP4620504B2 (ja) * 2005-03-10 2011-01-26 富士通セミコンダクター株式会社 半導体メモリおよびシステム装置
KR100771876B1 (ko) * 2006-07-14 2007-11-01 삼성전자주식회사 버스트 데이터의 리오더링 여부에 따라 클럭 레이턴시를조절하는 반도체 메모리 장치 및 방법
JP5018074B2 (ja) * 2006-12-22 2012-09-05 富士通セミコンダクター株式会社 メモリ装置，メモリコントローラ及びメモリシステム
JP5029205B2 (ja) * 2007-08-10 2012-09-19 富士通セミコンダクター株式会社 半導体メモリ、半導体メモリのテスト方法およびシステム
US8307180B2 (en) 2008-02-28 2012-11-06 Nokia Corporation Extended utilization area for a memory device
KR100987296B1 (ko) * 2008-06-24 2010-10-12 종 진 우 범용 캐스터
US8874824B2 (en) 2009-06-04 2014-10-28 Memory Technologies, LLC Apparatus and method to share host system RAM with mass storage memory RAM
US9417998B2 (en) 2012-01-26 2016-08-16 Memory Technologies Llc Apparatus and method to provide cache move with non-volatile mass memory system
US9311226B2 (en) 2012-04-20 2016-04-12 Memory Technologies Llc Managing operational state data of a memory module using host memory in association with state change
JP2015008029A (ja) * 2013-06-26 2015-01-15 マイクロン テクノロジー， インク． 半導体装置
WO2015089488A1 (en) 2013-12-12 2015-06-18 Memory Technologies Llc Channel optimized storage modules
KR102164019B1 (ko) * 2014-01-27 2020-10-12 에스케이하이닉스 주식회사 버스트 랭스 제어 장치 및 이를 포함하는 반도체 장치
US10380060B2 (en) * 2016-06-17 2019-08-13 Etron Technology, Inc. Low-pincount high-bandwidth memory and memory bus
US20230221892A1 (en) * 2022-01-12 2023-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Memory interface

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6275948B1 (en) * 1997-11-14 2001-08-14 Agere Systems Guardian Corp. Processor powerdown operation using intermittent bursts of instruction clock
JP2000011652A (ja) * 1998-06-29 2000-01-14 Nec Corp 半導体記憶装置
US6314049B1 (en) * 2000-03-30 2001-11-06 Micron Technology, Inc. Elimination of precharge operation in synchronous flash memory
JP4111789B2 (ja) * 2002-09-13 2008-07-02 富士通株式会社 半導体記憶装置の制御方法及び半導体記憶装置

Also Published As

Publication number Publication date
JP2004110890A (ja) 2004-04-08
US6842391B2 (en) 2005-01-11
US7057959B2 (en) 2006-06-06
CN100369156C (zh) 2008-02-13
US20050094480A1 (en) 2005-05-05
KR20040024515A (ko) 2004-03-20
TW200409120A (en) 2004-06-01
JP4111789B2 (ja) 2008-07-02
EP1400978A2 (en) 2004-03-24
KR100922412B1 (ko) 2009-10-16
EP1400978A3 (en) 2004-11-17
CN1489155A (zh) 2004-04-14
US20040184325A1 (en) 2004-09-23
EP1400978B1 (en) 2017-10-11

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MM4A Annulment or lapse of patent due to non-payment of fees