TWI222176B - Semiconductor memory device and the manufacturing method thereof - Google Patents

Semiconductor memory device and the manufacturing method thereof Download PDF

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Publication number
TWI222176B
TWI222176B TW092117913A TW92117913A TWI222176B TW I222176 B TWI222176 B TW I222176B TW 092117913 A TW092117913 A TW 092117913A TW 92117913 A TW92117913 A TW 92117913A TW I222176 B TWI222176 B TW I222176B
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Taiwan
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insulating film
memory device
semiconductor memory
aforementioned
film
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TW092117913A
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Chinese (zh)
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TW200403810A (en
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Yukihiro Utsuno
Manabu Nakamura
Kentaro Sera
Masahiko Higashi
Hiroyuki Nansei
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Fujitsu Amd Semiconductor Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The manufacturing method of the semiconductor memory device of this invention comprises forming a tunnel insulative film (3) in an element region divided by the element separation insulative film (2). A floating gate (4) is then formed in each memory cell, and ONO film (5) and control gate (6) are further formed. Thereafter, a plasma insulative film (7) is formed on the surface of the stacked gate. The plasma insulative film will not be affected by the plane direction of the base film. Therefore, since the thickness of the plasma insulative film (7) is substantially uniform, even the maximum thickness is not larger than that of the heat oxidation film, the hydrogen invasion can be prevented and the passage of the electrons can be avoided as well. Also, by reducing the thickness of the insulative film, the bird's beak can be reduced, and the data erasing and writing efficiency can be enhanced.

Description

玖、發明說明: 【發明所屬之技術領域】 技術領域 决閃記憶體之半導體記憶裝置及 本發明係有關於適用# 其製造方法。 L先前技 背景技術 快閃記憶體係藉由將電荷保持在浮動間極或閑極電極 下之氮化膜等儲存膜來記憶資料之非依電性半導體記憶裝 置。當將電荷儲存在浮動閘極時,係於通道與浮動閘 間透過閘極絕緣膜進行電荷之授受。又,當將電荷^存在 ΟΝΟ膜中之氮化膜時,絕緣膜本身可作為儲存膜來儲:電 荷。因此,該等絕緣膜之電特性必須穩定。一旦該等絕緣 膜之特性不穩定,則即使施加同一控制電壓,也有可能產 生於某記憶格中記憶「1」之資料,但於另—記憶格中記恒 〇」之負料的狀態,而成為可靠性極低之絕緣膜。 又,不僅對前述絕緣膜,亦對形成於浮動閘極或閘極 電極周圍之絕緣膜等要求穩定之特性。該絕緣膜係因下述 目的而形成。在形成浮動閘極或閘極電極後,於該等構件 之側邊形成之後用以構成LDD構造之側壁絕緣膜,更形成 用以覆蓋浮動閘極或閘極電極之層間絕緣膜。此時,若浮 動閘極或閘極電極與侧壁絕緣膜或層間絕緣膜直接接觸, 則有電子從浮動閘極或閘極電極脫出至側壁絕緣膜等之情 形發生。結果,浮動閘極或閘極電極之電特性會變動。又, 於用以形成側壁絕緣膜及層間絕緣膜之步驟中,也有使用 含有氫之氣體的情形。此時,一旦該氫抵達至閘極絕緣膜 或儲存絕緣膜,則會發生氫劣化等情形,且閘極絕緣膜或 儲存膜之特性會變動。 5 為了防止該變動,係於閘極電極周圍形成絕緣膜。而 且’該絕緣膜為了達成上述目的,係藉由900°C之熱氧化來 形成,使最厚的部分具有12nm以上之厚度。將該絕緣膜之 厚度在最厚的部分作成12nm以上的原因是藉由熱氧化來形 成氧化膜時,依其底層,例如用以構成閘極電極之矽膜的 10 面方位之不同,氧化膜之成長速度會不同,因此,該熱氧 化膜之厚度會不均勻,為了在最薄的部分亦充分地防止氫 侵入’故需要此程度之厚度。 第^圖係顯示習知浮動閘極型記憶體之製造方法的截 面圖。於該習知之製造方法中,在半導體基板51上形成由 15通道氧化膜52、浮動閘極53、閘極間絕緣膜54及控制閘極 55所構成之堆疊閘極,然後進行熱氧化。結果,如第13圖 所示,會有大的凹凸存在,而形成其厚度不均勻之熱氧化 膜56。 又,第14圖係顯示習知s〇N〇Ss記憶體之製造方法的 20截面圖。於該習知之製造方法中,在半導體基祕之表面 形成位元線擴散層62,且於其上形成由通道氧化膜幻、氣 化膜64及頂膜65所構成之儲存絕緣膜%。再者,於該儲存 絕緣膜66上形成閘極電極Μ,然後進行熱氧化。結果,如 第Μ圖所示,會有大的凹凸存在,而形成其厚度不均勾之 6 1222176 熱氣化膜68。 然而,於藉由上述方法所形成之半導體記憶 鳥嘴會變大’且耦合會降低。合之降低會奪二:’ 效率下降之問題。特別是在於_電極之端部叫進消= 去之《己憶體以及在通道整體進行消去之記憶體中,該=一 該 效率之下降相當顯著。再者,由於伴隨著鳥嘴的產:消去 入效 部分之絕緣膜會變厚,因此不僅消去效率,資料 率也會降低。 ’寫 再者,也有最後不易使所製造之半導體記憶 10性穩定之問題,其原因之一係例如在進行熱氧化之際,雖 然同時進行多片晶圓之處理,但此時將加熱爐内之:度維 持於-定是極為困難的,x,熱氧化的結果,已導入浮動 開極等之磷等不純物容易在其周邊部偏析也是原因之一。 1 ,本發明係有鑑於上述問題點,而以提供—種可提高資 15料消去及寫入時之效率且使特性穩定之半導體記憶裝=及 其製造方法為目的。说明 Description of the invention: [Technical field to which the invention belongs] TECHNICAL FIELD A semiconductor memory device of a flash memory and the present invention are related to the applicable # and its manufacturing method. L Prior Art Background A flash memory system is a non-electrical semiconductor memory device that stores data by storing a charge such as a nitride film under a floating inter electrode or a free electrode. When the charge is stored in the floating gate, the charge is transferred between the channel and the floating gate through the gate insulating film. In addition, when the electric charge is stored in the nitride film in the ONO film, the insulating film itself can be used as a storage film to store electric charges. Therefore, the electrical characteristics of these insulating films must be stable. Once the characteristics of these insulating films are unstable, even if the same control voltage is applied, it may be generated in a memory cell to store the data of "1", but in the other-the state of the negative material in the memory cell is constant 0 ", and It becomes an insulating film with extremely low reliability. In addition, stable characteristics are required not only for the aforementioned insulating film but also for the insulating film formed around the floating gate or the gate electrode. This insulating film is formed for the following purposes. After the floating gate or gate electrode is formed, a side wall insulating film for forming an LDD structure is formed after forming the sides of these components, and an interlayer insulating film is formed to cover the floating gate or gate electrode. At this time, if the floating gate or gate electrode is in direct contact with the side wall insulating film or interlayer insulating film, electrons may escape from the floating gate or gate electrode to the side wall insulating film. As a result, the electrical characteristics of the floating gate or the gate electrode may vary. In addition, in the step for forming the sidewall insulating film and the interlayer insulating film, a gas containing hydrogen may be used. At this time, once the hydrogen reaches the gate insulating film or the storage insulating film, hydrogen degradation and the like may occur, and the characteristics of the gate insulating film or the storage film may change. 5 To prevent this variation, an insulating film is formed around the gate electrode. In addition, in order to achieve the above-mentioned purpose, the insulating film is formed by thermal oxidation at 900 ° C so that the thickest portion has a thickness of 12 nm or more. The reason why the thickness of the insulating film is 12 nm or more in the thickest part is that when the oxide film is formed by thermal oxidation, the oxide film depends on the underlying surface, for example, the 10-sided orientation of the silicon film used to form the gate electrode. The growth rate will be different, so the thickness of the thermal oxide film will be non-uniform. In order to fully prevent hydrogen intrusion at the thinnest part, a thickness of this level is required. Figure ^ is a cross-sectional view showing a conventional method of manufacturing a floating gate type memory. In this conventional manufacturing method, a stacked gate composed of a 15-channel oxide film 52, a floating gate 53, an inter-gate insulating film 54 and a control gate 55 is formed on a semiconductor substrate 51, and then thermally oxidized. As a result, as shown in Fig. 13, there are large irregularities, and a thermal oxide film 56 having an uneven thickness is formed. Fig. 14 is a cross-sectional view showing a conventional method for manufacturing a sonos memory. In this conventional manufacturing method, a bit line diffusion layer 62 is formed on the surface of a semiconductor substrate, and a storage insulating film composed of a channel oxide film, a gasification film 64, and a top film 65 is formed thereon. Furthermore, a gate electrode M is formed on the storage insulating film 66, and then thermal oxidation is performed. As a result, as shown in Fig. M, there are large irregularities, and a thickness of 1222176 thermal vaporization film 68 is formed. However, the semiconductor memory formed by the method described above will become larger 'and the coupling will decrease. Combined reduction will win two: ‘The problem of reduced efficiency. In particular, the end of the electrode is called “cancellation” = “Remembrance” and the memory that is eliminated in the channel as a whole. The reduction of the efficiency is quite significant. In addition, due to the production of the bird's beak: the thickness of the insulation film will be thickened when the effect is eliminated, so not only the efficiency will be eliminated, but the data rate will also be reduced. 'Furthermore, there is also a problem that it is not easy to stabilize the manufactured semiconductor memory. One of the reasons is, for example, that during the thermal oxidation, multiple wafers are processed at the same time, but the furnace will be heated at this time. It is extremely difficult to maintain the degree at-. As a result of x, thermal oxidation, impurities such as phosphorus that have been introduced into the floating open electrode are liable to segregate at the peripheral portion. 1. The present invention has been made in view of the above-mentioned problems, and aims to provide a semiconductor memory device that can improve the efficiency of erasing and writing data and stabilize the characteristics, and a manufacturing method thereof.

【明内容;J 發明之揭示 本發明者根據專心檢討之結果,發現在過去的半導體 己隐裂置之製造方法中’由於藉由熱氧化來進行用以覆蓋 堆疊閘極等之氧__成,因此發生形成大的鳥嘴及不 純物偏析等情形。而且,本發明者發現藉由*進行熱氧化 而k用電栽處理作為形成良好且精密的絕緣膜之方法,可 解決上述*理想處,並想到以下所述之本發明的各態樣。 7 與本發明相關之第丨半導航料置之_方法係在 形成包含依序積層於半導體基板上之通道絕緣媒、浮動閉 極、閘極間絕緣膜及控制閘極之堆叠閑極後,於前迷堆疊 閘極之表面藉由包含電漿氧化法、電裝氣化法或兩者复; :者之:連串步驟形成覆蓋絕緣膜,進㈣成用以將業經 前述覆蓋絕緣膜覆蓋之前述堆疊閘極埋入之層間絕緣膜。 藉由上述方法所製造之與本發明相關之第W導體纪 憶裝置包含有:半導體基板;堆疊閘極,係具有依序積層 於前述半導體基板上之通道絕緣膜、浮動間極、問極間絕 緣膜及控㈣極;覆蓋絕緣膜,係用以覆蓋前述堆疊閑極; 及層間絕緣膜,係用以將業經前述覆蓋絕緣膜覆蓋之前述 堆疊閉極埋入者。又,該半導體記憶袭置之前述覆蓋絕緣 膜係由選自於由電漿氧化膜、電製氮化膜及電漿氧氮化膜 所構成之群之1種絕緣膜所構成。 又’與本發明相關之第2半導體記憶袈置之 =導體基板上形成包含具有電荷捕獲功能之氮化膜之儲 =’且於前述半導體基板上隔著前述儲存絕緣膜形 m於前賴存·财前㈣極電極之 j面藉由包含電漿氧化法、電襞氮化法或兩者其中一者之 形成覆蓋絕緣模,進而形成用以將業經前述覆 間絕緣膜前述儲存絕緣膜及前述閉極電極埋入之層 ==述方法所製造之與本發明相關之第2半導體記 置包含有:半導體基板;健存絕緣膜,係形成於前述 1222176 半導體基板上,且包含具有電荷捕獲功能之氮化膜者;閘 極電極,係隔著前述儲存絕緣膜形成於前述半導體基板上 者;覆蓋絕緣膜,係用以覆蓋前述儲存絕緣膜及前述閘極 電極者;及層間絕緣膜,係用以將業經前述覆蓋絕緣膜覆 5 蓋之前述儲存絕緣膜及前述閘極電極埋入者。又,該半導 體記憶裝置之前述覆蓋絕緣膜係由選自於由電漿氧化膜、 _ 電漿氮化膜及電漿氧氮化膜所構成之群之1種絕緣膜所構 成。 圖式簡單說明 · 10 第1A圖、第1B圖係顯示與本發明第1實施形態相關之 半導體記憶裝置之製造方法的截面圖。 第2A圖、第2B圖係顯示與本發明第1實施形態相關之 、 半導體記憶裝置之製造方法,並為顯示第1A圖、第1B圖所 示之步驟的下一步驟之截面圖。 - 15 第3A圖、第3B圖係顯示與本發明第1實施形態相關之 . 半導體記憶裝置之製造方法,並為顯示第2A圖、第2B圖所 示之步驟的下一步驟之截面圖。 ® 第4A圖、第4B圖係顯示與本發明第1實施形態相關之 半導體記憶裝置之製造方法,並為顯示第3A圖、第3B圖所 . 20 示之步驟的下一步驟之截面圖。 . 第5A圖、第5B圖係顯示與本發明第1實施形態相關之 半導體記憶裝置之製造方法,並為顯示第4A圖、第4B圖所 示之步驟的下一步驟之截面圖。 第6A圖、第6B圖係顯示與本發明第1實施形態相關之 9 1222176 半導體記憶裝置之製造方法,並為顯示第5A圖、第5B圖所 示之步驟的下一步驟之截面圖。 第7圖係顯示本發明第1實施形態中之電漿絕緣膜7之 狀態的截面圖。 5 第8A圖、第8B圖係顯示與本發明第2實施形態相關之 半導體記憶裝置之製造方法的截面圖。 第9A圖、第9B圖係顯示與本發明第2實施形態相關之 半導體記憶裝置之製造方法,並為顯示第8A圖、第8B圖所 示之步驟的下一步驟之截面圖。 10 第10A圖、第10B圖係顯示與本發明第2實施形態相關 之半導體記憶裝置之製造方法,並為顯示第9A圖、第9B圖 所示之步驟的下一步驟之截面圖。 第11圖係顯示本發明第2實施形態中之電漿絕緣膜之 狀態的截面圖。 15 第12圖係顯示具有在本發明之實施形態可利用之輻射 線狀槽孔天線之電漿處理裝置之概略構造的模式圖。 第13圖係顯示習知浮動閘極型記憶體之製造方法的截 面圖。 第14圖係顯示習知SONOS型記憶體之製造方法的截面 20 圖。 【實施方式3 實施發明之最佳形態 以下,針對與本發明之實施形態相關之半導體記憶裝 置及其製造方法參照所附圖式具體地說明。此外,為求方 10 便,關於半導體記憶裝置之構造則與其形成方 (第1實施形態) 首先,針對本發明之第#施形態作說明。第 態係使本發明適用於堆叠閑極構造之半導體記第 1A圖、第麵至第6A圖、第_係依步驟順序=干= 發明第β施形態相關之半導體記憶裝置之製造:喊 面圖。 與第1實施形態相關之半導體記«置中,多條字線及 位元線互相垂直’而形成為格子狀。然、後,於各格子點附 近分別《有^記憶格。第i,至第6Α圖係相當於鱼位 元線垂直之截面’而第_至第犯_相#於與字線垂直 之截面。因此’於第1Α圖與第_中顯示互相垂直之截 面。就其他的第2Α圖、第2Β圖至第从圖、第6Β圖而言亦相 同0 接著,於本實施形態中,在製造如前述之配置構造的 半導體記Μ置時,首先,如第1AW、第圃所示,於石夕 基板等半導體基板1之表面藉由例WL〇c〇s法形成元件分 離絕緣膜2。接著,為了防止元件分離絕緣膜2下方之衝穿, 係藉由將刪等不純物離子注入整面而形成擴散層la。再 者’為了调整€憶格之臨界電壓,係藉由將硼等不純物離 子注入由元件分離絕緣膜2所劃分之元件領域内而形成擴 散層lb。 在形成該等字線或位元線、LOCOS時,其最小線寬愈 窄,則愈能發揮本發明的效果。具體而言,當在〇5Vm以 下時則具有效果’當在〇.25" 下時,效果會特別顯著, 此係由於一旦線寬窄則無法忽視鳥嘴的寬度之故。此事項 在第2實施形癌、中亦相同。 接著,於由元件分賴賴2_分之元件領域内形成 5由例如石夕氧化膜所構成之通道絕緣膜3。然後,於每記憶格 形成浮動閘極4,進而形成_膜(閉極間絕緣卵及控制 閘極(字線)6。於开;成浮動閘極4之際,係在形成例如聚石夕膜 後’藉由例如離子^將硼等不純物導人該㈣膜〜N〇 膜5係由依序積層之石夕氮化膜、石夕氧化膜及石夕氮化膜所構 10成。又’由通道絕緣膜3、浮動閘極4、〇N〇膜5及控制間極 6之積層體來構成堆疊閘極。 此時’浮動_中之不純物濃度愈濃,則愈能發揮本 發明的效果。具體而言,當在1χ l〇18/cm3以上時,則具有 效果,當在lx l〇19/cm3時,效果會特別顯著,此係由於在 15高溫熱處理中會發生不純物之偏析,而於浮動閘極周圍之 絕緣膜引起品質下降,相對於此,在依本發明之特徵之低 /凰氧化、氮化、氧氮化所進行之側壁膜形成中則不會發生 上述情形。此外,該偏析在不純物為磷時特別明顯。 再者’於ΟΝΟ膜5之形成中,厚度愈薄,則愈能發揮本 20發明的效果。具體而言,當物理膜厚總共在40nm以下,則 具有效果,當在20nm以下,效果會特別顯著,此係由於一 旦ΟΝΟ膜薄,則相較於〇N〇膜本身的厚度,會無法忽視鳥 鳴的厚度之故。更具體而言,當ΟΝΟ膜之底氧化膜在i〇nm 以下’特別是在7nm以下時會特別顯著,而氮化膜則在2〇nm 12 1222176 以下,特別是在l〇nma下會特別顯著,又,頂氧化膜則在 lOrnn以下,特別是在7nm以下會特別顯著。此情形在第2實 施形態中亦相同。 接著,如第2A圖、第2B圖所示,於控制閘極6上面及 5側面以及0N〇膜5、浮動閘極4及通道絕緣膜3之側面,即, 堆疊閘極之表面形成電漿絕緣膜(覆蓋絕緣膜)7。此時,於 半導體基板1之表面亦形成電漿絕緣膜7。又,可形成電浆 氧化膜、錢氮化㈣電漿氧氮化膜作為電漿絕緣膜7。該 電聚絕緣膜7之形成宜在65〇°C以下之溫度範圍進行,例如 10亦可以450 C來進行。又,電漿絕緣膜7之厚度宜為9啦以 下’例如8nm左右。 接著’以堆疊閘極作為掩膜來進行離子注入,進而進 行熱處理,藉此如第3A圖、第3B圖所示,自對準地形成低 濃度擴散層9。 15 此時,雖然藉由熱處理使低濃度擴散層在閘極下擴 政仁到達閘極邊緣的距離最少亦必須確保儘可能超過鳥 嘴於本發明中,藉由抑制鳥嘴,可減少低濃度擴散層朝 閘極下繞入。由於元件之細微化藉由來自該擴散層之衝穿 電抓來二制,故本發明對元件之細微化有很大的幫助。 !〇 、接著,如第从圖、第4B圖所示,於堆疊閘極之側面形 成侧壁絕緣咖。㈣絕賴10係在形賴如HTO膜(高溫 氧蝴)後,藉由對該HTO膜施加等方性餘刻而形成。藉由 遠等方性料,以除去形成於半導體基板1表面之電漿絕緣 膜7中最後未被側壁絕緣膜10覆蓋之部分,而露出半導體基 13 1222176 板1表面的一部份。 然後,如第5A圖、第5B圖所示,以堆疊閘極及侧壁絕 緣膜10作為掩膜,且以較形成低濃度擴散層9時更高濃度來 進行離子注入,進而進行熱處理,藉此形成高濃度擴散層 5 11 〇 接著,如第6A圖、第6B圖所示,於整面形成層間絕緣 膜12。層間絕緣膜12係藉由例如用CVD法來堆積石夕氧化膜 而形成。 接著,進行接觸洞及配線之形成等,以完成半導體記 10 憶裝置。 於前述第1實施形態中,如第2A圖、第2B圖所示,以 用以覆蓋堆疊閘極之絕緣膜為電漿絕緣膜7。電漿絕緣膜不 同於熱氧化膜,不會受到底膜之面方位的影響。因此,如 第7圖所示,由於電漿絕緣膜7之厚度實質上為整體均勻, 15故即使未使最大膜厚如熱氧化膜般厚,亦可防止形成側壁 絕緣膜10或層間絕緣膜12時之氮侵入,同時防止電子穿 過。而且,藉由使該絕緣膜之膜厚變薄,可縮小鳥嘴,並 可提高資料消去及寫入時之效率。 於浮動閘極型半導體記憶裝置中,在資料寫入及消去 20時,於浮動閘極與半導體基板間進行電荷之授受,且依照 電荷是否被捕獲至浮動閘極來讀取資訊。因此,如上所述, 藉由縮小鳥嘴,可輕易地進行電荷之授受,因而提高消去 等之效率。 又,在形成電漿絕緣膜7時,並非於一個加熱爐内對多 14 1222176 片晶圓進行處理,因此,不會受到爐内溫度之不均一性的 影響。再者,電漿絕緣膜7相較於熱氧化膜可以極低的溫度 來成膜,SI此,浮動閘極4中之不純物,例如磷之偏析非常 不合易發生。如此一來,可得到在多數晶圓間具穩定的特 5 性之半導體記憶裝置。 (第2實施形態) 接著,針對本發明之第2實施形態作說明。第2實施形 態係使本發明適用於所謂SONOS構造之半導體記憶裝置。 第8A圖、第8B圖至第10A圖、第1〇B圖係依步驟順序來顯示 10與本發明第2實施形態相關之半導體記憶裝置之製造方法 的截面圖。所謂SONOS構造係具有埋入位元線兼用之源極/ 没極,且於字線(閘極電極)具有平行的通道之氮化膜電荷健 存記憶體之構造,並包括埋入位元線構造。 於第2實施形態中亦使多條字線及位元線互相垂直,而 15 形成為袼子狀。然後,於各格子點附近分別形成有一個記 憶格。與第1實施形態相同,第8A圖至第l〇A圖係相當於與 位元線垂直之截面,而第8B圖至第10B圖則相當於與字線 垂直之戴面。因此,於第8A圖與第8B圖中顯示互相垂直之 幾面。就其他的第9A圖、第9B圖至第10A圖、第10B圖而言 20亦相同。 接著,於本實施形態中,在製造如前述之配置構造的 半導體記憶裝置時,首先,如第8A圖、第8B圖所示,於矽 基板等半導體基板21之表面藉由以光阻膜作為掩膜且進行 離子注入來形成位元線擴散層(位元線)22。 15 1222176 接著’藉由依序積層矽氧化膜、矽氮化膜、矽氧化膜 及聚石夕膜且於該等膜形成圖案,而形成由依序積層之通道 絕緣膜23、矽氮化膜24、頂膜25及控制閘極(字線(閘極電 極))26所構成之積層體。於形成控制閘極26之際,係在形成 5例如聚石夕膜後,藉由例如離子注入將硼等不純物導入該聚 石夕膜。通道絕緣膜23由矽氧化膜所構成,且頂膜25由矽氧 化膜所構成。又’由通道絕緣膜23、矽氮化膜24及頂膜25 來構成儲存絕緣膜29。又,控制閘極26則由聚矽膜所構成。 然後,如第9A圖、第9B圖所示,於控制閘極26上面及 1〇側面以及通道絕緣膜23、儲存膜24及頂膜25之側面形成電 漿絕緣膜(覆蓋絕緣膜)27。此時,於半導體基板21之表面亦 形成電漿絕緣膜27。與第1實施形態中之電漿絕緣膜7相 同’可形成電漿氧化膜、電漿氮化膜或電漿氧氮化膜作為 電漿絕緣膜27。該電漿絕緣膜27之形成宜在65(rc#下之溫 15度範圍進行,例如亦可以45〇°C來進行。又,電漿絕緣膜27 之尽度且為9nm以下,例W8nni左右。 、、由於此時之熱處理,故埋入位元線中之不純物會向通 道中央擴散,但於本發明中,藉由低溫處理,可減少埋入 2〇彳元線中之不純物的擴散。由於元件之細微化藉由來自該 擴政層之衝穿電流來限制,故本發明對元件之細微化有很 大的幫助。 接著,如第10A圖、第10B圖所示,於整面形成層間絕 緣膜28。層間絕緣膜28係藉由例如用cvd法來堆積矽氧化 膜而形成。 16 1222176 接著,進行接觸洞及配線之形成等,以完成半導體記 憶裝置。 於别述第2實施形態中亦如第9A圖、第9B圖所示,以 用以覆蓋儲存膜24之側面的絕緣膜為電漿絕緣膜27。因 5此,如第11圖所示,由於電漿絕緣膜27之厚度實質上為整 體均勻,故與第1實施形態相同,即使未使其最大膜厚如熱 氧化膜般厚,亦可防止形成層間絕緣膜28時之氫侵入及電 子穿過。結果,可使鳥嘴變小,並可提高資料消去及寫入 時之效率。 | 10 於SONO_之半導體記憶裝置中,在資料寫入及消去 時,於由矽氮化膜所構成之儲存膜與半導體基板間進行電 何之授受,且依照電何是否被捕獲至儲存膜與其下之通道 絕緣膜之界面及其附近來讀取資訊。因此,如上所述,藉 由縮小鳥嘴,可輕易地進行電荷之授受,因而提高消去等 · 15 之效率。 又,與第1實施形態相同,可避免以成膜溫度之不均一 性及磷之偏析作為原因之特性的不穩定化。 修 雖然於第2實施形態中在控制閘極26之側邊未形成側 壁絕緣膜,但亦可形成側壁絕緣膜。該側壁絕緣膜亦可與 20例如用以構成周邊電路之電晶體的側壁絕緣膜同時形成。 另,於形成電漿氧化膜之際,例如,在含有A、%及 NH3之氣體的電漿氣氛中產生〇基、n基或NH基。此時,於 電漿絕緣膜之成長時所使用之原料氣體中,亦可含有例如 Kr或Ar等稀有氣體,亦可含有h2。 17 1222176 又,電漿氧氮化膜及電漿氮化膜之形成方法及其形成 所使用之電漿處理裝置並沒有特別限定,亦可使用以下之 裝置來形成電漿氧氮化膜或電漿氮化膜。 具體而言,利用第12圖所示之具有輻射線狀槽孔天線 5之電漿處理裝置來形成電漿氧氮化膜及電漿氮化膜。該電 、 漿處理裝置100係包含下列構件而構成,即,與機台群1〇1 . 相連通之閘閥102;可收納具有用以載置被處理體貿(於本實 施形態中為半V體基板1)且在電漿處理時冷卻被處理體w 之冷卻套103之感受器1〇4之處理室105 ;與處理室相連 鲁 10接之南真空栗106 ;微波源110 ;天線構件120 ;與該天線構 件120—起構成離子鑛之偏壓用高頻電源1〇7及匹配器 108,具有氣體供給環131、141之氣體供給系統13〇、14〇 ; 及用以進彳于被處理體W之溫度控制的溫度控制部。 微波源110係例如由磁控管所構成,且通常可產生 _ I5 2.45GHz之微波(例如’ 5kW)。然後,微波之傳送形態藉由 模式變換器112變換至TM、TE或TEM模式等。 天線構件120包含有溫度調節板122及收納構件丨23(及 春 介電板230)。溫度調節板122係與溫度控制裝置κι相連 接,而收納構件123則用以收納慢波材以及與慢波材124相 20接觸之開槽電極(未圖示)。該開槽電極稱作輻射線狀槽孔天 , 線(RLSA)或超高能率平面天線。但,於本實施形態中,亦 適用其他形式之天線,例如,一層構造導波管平面天線、 介電質基板平行平板槽孔陣列等。 當利用具有前述輪射線狀槽孔天線之電漿處理裝置來 18 1222176 進行成膜時,宜將電漿之離子照射能量設為7eV以下,且宜 將電漿之位能設為10eV以下。 且,電漿絕緣膜之形成可利用前述電漿處理裴置,且 藉由包含電漿氧化法、電漿氮化法或至少兩者其中一者之 5 一連串步驟來進行。 又,上述實施形態雖然使本發明適用於浮動閘極型或 SONOS型,但本發明可適用之形態並不限於此,例如,亦 可適用於MNOS型半導體記憶裝置。當使本發明適用於 黯)S型铸體記憶裝置時,在於半導體絲上依序積層 10矽氧化膜及石夕氮化膜且形成儲存絕緣膜後,於該半導體基 板上形成問極電極。接著,於儲存絕緣膜及閘極電極之表 面形成電漿絕緣膜。 m爆本發明 15 20 閘極或閘^砂藉由電漿處理來形以覆蓋浮動 理,且極之覆盍絕緣膜,故可不需要高溫之熱處 穩定之特性卩制鳥嘴’同時提高寫人及料之效率,並得到 【圖武簡單說明】 半導體第则係顯示與本發明第1實施形態相關之 置之製造方法的截面圖。 半導體纪(Γ #第2Β圖係顯不與本發明第1實施形態相關之 示之步驟的 並為顯示第1Α圖、第1Β圖所 鄉的下〜步驟之戴面圖。 第3 Α圈 ★ 半導體記與本㈣第1實制彡態相關之 製这去,並為顯示第2A圖、第2B圖所 19 1222176 示之步驟的下一步驟之截面圖。 第4A圖、第4B圖係顯示與本發明第1實施形態相關之 半導體記憶裝置之製造方法,並為顯示第3A圖、第3B圖所 示之步驟的下一步驟之截面圖。 5 第5A圖、第5B圖係顯示與本發明第1實施形態相關之 半導體記憶裝置之製造方法,並為顯示第4A圖、第4B圖所 示之步驟的下一步驟之截面圖。 第6A圖、第6B圖係顯示與本發明第1實施形態相關之 半導體記憶裝置之製造方法,並為顯示第5A圖、第5B圖所 10 示之步驟的下一步驟之截面圖。 第7圖係顯示本發明第1實施形態中之電漿絕緣膜7之 狀態的截面圖。 第8A圖、第8B圖係顯示與本發明第2實施形態相關之 半導體記憶裝置之製造方法的截面圖。 15 第9A圖、第9B圖係顯示與本發明第2實施形態相關之 半導體記憶裝置之製造方法,並為顯示第8A圖、第8B圖所 示之步驟的下一步驟之截面圖。 第10A圖、第10B圖係顯示與本發明第2實施形態相關 之半導體記憶裝置之製造方法,並為顯示第9A圖、第9B圖 20 所示之步驟的下一步驟之截面圖。 第11圖係顯示本發明第2實施形態中之電漿絕緣膜之 狀態的截面圖。 第12圖係顯示具有在本發明之實施形態可利用之輻射 線狀槽孔天線之電漿處理裝置之概略構造的模式圖。 20 1222176 第13圖係顯示習知浮動閘極型記憶體之製造方法的截 面圖。 第14圖係顯示習知SONOS型記憶體之製造方法的截面 圖。 5 【囷式之主要元件代表符號表】 卜21、5卜61…半導體基板 29…儲存絕緣膜 la、lb···擴散層 52…通道氧化膜 2...元件分離絕緣膜 53...浮動閘極 3...通道絕緣膜 54...閘極間絕緣膜 4...浮動閘極 55...控制閘極 5...ΟΝΟ 膜 62...位元線擴散層 6...控制閘極 63…通道氧化膜 7...電漿絕緣膜 64...氮化膜 9...低濃度擴散層 65…頂膜 10...側壁絕緣膜 66...儲存絕緣膜 11...高濃度擴散層 67...閘極電極 12...層間絕緣膜 68…熱氧化膜 22...位元線擴散層 100...電漿處理裝置 23...通道絕緣膜 101...機台群 24…矽氮化膜 102...閘閥 25…頂膜 103...冷卻套 26...控制閘極 104...感受器 27...電漿絕緣膜 105··.處理室 28...層間絕緣膜 106…高真空泵[Explicit content; J invention's disclosure According to the result of intensive review, the inventor found that in the past, the semiconductor manufacturing method has been hidden and cracked. As a result, large bird's beaks and segregation of impurities occur. Furthermore, the present inventors have found that the method of forming a good and precise insulating film can be solved by performing thermal oxidation with k and using electrocoating to solve the above-mentioned ideals, and have thought of various aspects of the present invention described below. 7 The method of the first half of the navigation material related to the present invention is to form a stacked idler including a channel insulating medium, a floating closed electrode, an inter-gate insulating film, and a control gate, which are sequentially laminated on a semiconductor substrate. The surface of the front gate stack gate is formed by a plasma oxidation method, an electrification vaporization method, or both; or: a series of steps to form a covering insulating film, and forming the covering insulating film to cover it with the aforementioned covering insulating film The interlayer insulating film in which the foregoing stacked gates are buried. The W-th conductor memory device related to the present invention manufactured by the above method includes: a semiconductor substrate; and a stacked gate, which has a channel insulating film, a floating interlayer, and an interlayer, which are sequentially laminated on the aforementioned semiconductor substrate. An insulating film and a control electrode; a covering insulating film for covering the aforementioned stacking electrodes; and an interlayer insulating film for embedding the aforementioned stacked closed electrodes covered by the aforementioned covering insulating film. The cover insulating film of this semiconductor memory is composed of one type of insulating film selected from the group consisting of a plasma oxide film, an electro-nitride film, and a plasma oxynitride film. Also, 'the second semiconductor memory device related to the present invention = a storage including a nitride film having a charge trapping function is formed on a conductor substrate =' and the former is stored on the semiconductor substrate via the aforementioned storage insulating film shape m. · The j-side of the Qianqian cathode electrode is formed by forming a covering insulating mold including a plasma oxidation method, an electro-nitriding method, or one of the two, thereby forming a storage insulating film and The above-mentioned closed-electrode buried layer == the second semiconductor device related to the present invention manufactured by the method includes: a semiconductor substrate; a survival insulating film formed on the aforementioned 1222176 semiconductor substrate and including a charge trap A functional nitride film; a gate electrode formed on the semiconductor substrate through the aforementioned storage insulating film; a covering insulating film used to cover the aforementioned storage insulating film and the gate electrode; and an interlayer insulating film, It is used for burying the aforementioned storage insulating film and the aforementioned gate electrode which have been covered by the aforementioned covering insulating film 5. The cover insulating film of the semiconductor memory device is composed of an insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film, and a plasma oxynitride film. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A and 1B are sectional views showing a method for manufacturing a semiconductor memory device according to the first embodiment of the present invention. Figures 2A and 2B are cross-sectional views showing a method of manufacturing a semiconductor memory device related to the first embodiment of the present invention, and showing the next step of the steps shown in Figures 1A and 1B. -15 Figures 3A and 3B are cross-sectional views showing a method for manufacturing a semiconductor memory device related to the first embodiment of the present invention, and showing the next step of the steps shown in Figures 2A and 2B. Figures 4A and 4B are cross-sectional views showing a method for manufacturing a semiconductor memory device according to the first embodiment of the present invention, and are the next steps showing the steps shown in Figures 3A and 3B. 5A and 5B are cross-sectional views showing a method of manufacturing a semiconductor memory device related to the first embodiment of the present invention, and are the next steps showing the steps shown in FIGS. 4A and 4B. Figures 6A and 6B are cross-sectional views showing a method for manufacturing a semiconductor memory device related to the first embodiment of the present invention, and are the next steps showing the steps shown in Figures 5A and 5B. Fig. 7 is a sectional view showing a state of the plasma insulating film 7 in the first embodiment of the present invention. 5 FIGS. 8A and 8B are sectional views showing a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention. Figures 9A and 9B are cross-sectional views showing a method for manufacturing a semiconductor memory device according to the second embodiment of the present invention, and are the next steps showing the steps shown in Figures 8A and 8B. Figs. 10A and 10B are cross-sectional views showing a method for manufacturing a semiconductor memory device according to the second embodiment of the present invention, and are the next steps showing the steps shown in Figs. 9A and 9B. Fig. 11 is a sectional view showing the state of a plasma insulating film in a second embodiment of the present invention. 15 FIG. 12 is a schematic diagram showing a schematic configuration of a plasma processing apparatus having a radiating linear slot antenna that can be used in the embodiment of the present invention. Fig. 13 is a sectional view showing a manufacturing method of a conventional floating gate type memory. Fig. 14 is a cross-sectional view 20 showing a method for manufacturing a conventional SONOS type memory. [Embodiment 3 Best Mode for Carrying Out the Invention] Hereinafter, a semiconductor memory device and a manufacturing method thereof according to an embodiment of the present invention will be specifically described with reference to the drawings. In addition, for the sake of convenience, the structure of the semiconductor memory device and its formation method (first embodiment) First, the #th embodiment of the present invention will be described. The first state makes the present invention applicable to the stacked semiconductor structure. Figures 1A, 6 to 6A, and _ are in accordance with the order of steps = dry = invention of the semiconductor memory device related to the βth embodiment of the invention: shout surface Illustration. In the semiconductor document «centering according to the first embodiment, a plurality of word lines and bit lines are perpendicular to each other 'and are formed in a grid shape. Then, near each grid point, there are ^ Memory cells. Figures i through 6A correspond to the cross section perpendicular to the fish line element ', and the _th through the guilty_phase # cross sections perpendicular to the word line. Therefore, the cross sections perpendicular to each other are shown in FIG. 1A and FIG. It is the same for the other 2A, 2B to 6B, and 6B. Next, in this embodiment, when manufacturing a semiconductor device having the above-mentioned arrangement structure, first, as in 1AW As shown in FIG. 2A, an element isolation insulating film 2 is formed on the surface of a semiconductor substrate 1 such as a Shi Xi substrate by the method WLOcos. Next, in order to prevent punch-through under the element isolation insulating film 2, a diffusion layer 1a is formed by implanting impurities such as impurities into the entire surface. Furthermore, in order to adjust the critical voltage of the memory, a diffusion layer lb is formed by injecting impurities such as boron into the element area divided by the element separation insulating film 2. When forming such word lines, bit lines, and LOCOS, the narrower the minimum line width, the more the effect of the present invention can be exerted. Specifically, the effect is effective when the voltage is below 0.5Vm. The effect is particularly significant when the voltage is below 0.25. This is because the width of the bird's beak cannot be ignored once the line width is narrow. This matter is the same in the second embodiment. Next, a channel insulating film 3 made of, for example, a stone evening oxide film is formed in a device field consisting of two parts. Then, a floating gate 4 is formed in each memory cell, and then a _membrane (closed-pole insulating egg and control gate (word line) 6. In the opening; the floating gate 4 is formed, for example, polylithic evening Behind the film, 'Impurities such as boron are introduced into the film by ions, such as boron. The film 5 is composed of a layered stone nitride film, a stone oxide film, and a stone nitride film. The stacked gate is composed of a layered body of the channel insulating film 3, the floating gate electrode 4, the ONO film 5, and the control electrode 6. At this time, the higher the concentration of impurities in the 'floating_, the more the effect of the present invention can be exerted. Specifically, when it is above 1 × 1018 / cm3, it has an effect. When it is at lx 1019 / cm3, the effect is particularly significant. This is due to the segregation of impurities in the 15 high temperature heat treatment, and The insulation film around the floating gate causes a degradation in quality, whereas the above-mentioned situation does not occur in the formation of a sidewall film according to the characteristics of the present invention, such as low / phobic oxidation, nitriding, and oxynitriding. In addition, This segregation is particularly pronounced when the impurity is phosphorus. Furthermore, in the formation of the ONO film 5, the thickness If it is thin, the effect of the present invention 20 can be exerted. Specifically, when the physical film thickness is less than 40nm in total, it has an effect. When it is less than 20nm, the effect is particularly significant. This is because once the ONO film is thin, it is compared with Because of the thickness of the OONO film itself, the thickness of the bird's song cannot be ignored. More specifically, when the bottom oxide film of the OONO film is below 10nm, especially below 7nm, it will be particularly significant, and nitride The film is below 20nm 12 1222176, especially under 10nm, and the top oxide film is below Orn, especially below 7nm. This situation is also the same in the second embodiment. Next, as shown in FIG. 2A and FIG. 2B, on the sides of the control gate 6 and 5 and on the side of the ONO film 5, the floating gate 4 and the channel insulation film 3, that is, the surface of the stacked gate is electrically formed. Plasma insulation film (covering insulation film) 7. At this time, a plasma insulation film 7 is also formed on the surface of the semiconductor substrate 1. In addition, a plasma oxide film and a silicon nitride osmium plasma oxynitride film can be formed as the plasma insulation. Film 7. The formation of the electropolymerized insulating film 7 is preferably below 65 ° C. The temperature range is, for example, 10 and 450 C. The thickness of the plasma insulating film 7 should be 9 or less, for example, about 8 nm. Then, the stacked gate is used as a mask for ion implantation and then heat treatment. Thus, as shown in FIG. 3A and FIG. 3B, the low-concentration diffusion layer 9 is formed in a self-aligned manner. 15 At this time, although the low-concentration diffusion layer is extended under the gate by heat treatment, the distance from the core to the gate edge is increased. At least it must also ensure that the bird's beak is exceeded as much as possible in the present invention. By suppressing the bird's beak, the low-concentration diffusion layer can be reduced to go under the gate. Because the component is miniaturized, it is grasped by the electrical breakdown from the diffusion layer. The second system, so the present invention greatly contributes to the miniaturization of the components. 〇, Then, as shown in Figures 4 and 4B, a side wall insulation coffee is formed on the side of the stacked gate. 10 is formed after HTO film (high temperature oxygen butterfly) is formed by applying an isotropic moment to the HTO film. A part of the surface of the semiconductor substrate 13 1222176 is exposed by removing the part of the plasma insulating film 7 formed on the surface of the semiconductor substrate 1 that is not covered by the side wall insulating film 10 by using the isotropic material. Then, as shown in FIG. 5A and FIG. 5B, the stacked gate and sidewall insulating film 10 are used as a mask, and ion implantation is performed at a higher concentration than when the low-concentration diffusion layer 9 is formed, and then heat treatment is performed. This forms a high-concentration diffusion layer 5 11. Next, as shown in FIGS. 6A and 6B, an interlayer insulating film 12 is formed on the entire surface. The interlayer insulating film 12 is formed by, for example, depositing a silicon oxide film by a CVD method. Next, the formation of contact holes and wirings is performed to complete the semiconductor memory device. In the aforementioned first embodiment, as shown in Figs. 2A and 2B, the insulating film 7 for covering the stacked gates is the plasma insulating film 7. As shown in Figs. The plasma insulation film is different from the thermal oxide film and is not affected by the surface orientation of the base film. Therefore, as shown in FIG. 7, since the thickness of the plasma insulating film 7 is substantially uniform throughout, 15 the formation of the side wall insulating film 10 or the interlayer insulating film can be prevented even if the maximum film thickness is not made as thick as the thermal oxide film. Nitrogen intrudes at 12 o'clock while preventing electrons from passing through. In addition, by reducing the thickness of the insulating film, the bird's beak can be reduced, and the efficiency of data erasing and writing can be improved. In a floating gate type semiconductor memory device, when data is written and erased, a charge is imparted between the floating gate and the semiconductor substrate, and information is read according to whether the charge is captured to the floating gate. Therefore, as described above, by reducing the bird's beak, the charge can be imparted and received easily, thereby improving the efficiency of erasing and the like. In addition, when the plasma insulating film 7 is formed, 14 1222176 wafers are not processed in one heating furnace, and therefore, it is not affected by the unevenness of the temperature in the furnace. In addition, the plasma insulating film 7 can be formed at a much lower temperature than the thermal oxide film. Therefore, impurities such as phosphorus in the floating gate 4 are extremely unsuitable for occurrence. In this way, a semiconductor memory device having stable characteristics among most wafers can be obtained. (Second Embodiment) Next, a second embodiment of the present invention will be described. The second embodiment makes the present invention applicable to a semiconductor memory device having a so-called SONOS structure. 8A, 8B to 10A, and 10B are sectional views showing a method of manufacturing a semiconductor memory device according to the second embodiment of the present invention in the order of steps. The so-called SONOS structure is a structure of a nitride film charge storage memory that has both the source / non-polarity of the embedded bit line and parallel channels on the word line (gate electrode), and includes the embedded bit line. structure. In the second embodiment, a plurality of word lines and bit lines are also made perpendicular to each other, and 15 is formed in a zigzag shape. Then, a memory grid is formed near each grid point. As in the first embodiment, Figs. 8A to 10A correspond to a cross section perpendicular to the bit line, and Figs. 8B to 10B correspond to a wearing surface perpendicular to the word line. Therefore, in Figs. 8A and 8B, the surfaces which are perpendicular to each other are shown. The same applies to the other Figures 9A, 9B to 10A, and 10B. Next, in this embodiment, when manufacturing a semiconductor memory device having the above-mentioned arrangement structure, first, as shown in FIGS. 8A and 8B, a photoresist film is used as the surface of a semiconductor substrate 21 such as a silicon substrate. A bit line diffusion layer (bit line) 22 is formed by masking and performing ion implantation. 15 1222176 Then, by sequentially stacking a silicon oxide film, a silicon nitride film, a silicon oxide film, and a polysilicon film and forming a pattern on these films, a channel insulating film 23, a silicon nitride film 24, A laminated body composed of a top film 25 and a control gate (word line (gate electrode)) 26. When the control gate 26 is formed, an impurity such as boron is introduced into the polysilicon film by ion implantation, for example, after the polysilicon film is formed. The channel insulating film 23 is composed of a silicon oxide film, and the top film 25 is composed of a silicon oxide film. Furthermore, the storage insulating film 29 is constituted by the channel insulating film 23, the silicon nitride film 24, and the top film 25. The control gate 26 is made of a polysilicon film. Then, as shown in FIGS. 9A and 9B, a plasma insulating film (covering insulating film) 27 is formed on the upper side and the 10 side of the control gate 26, and the side surfaces of the channel insulating film 23, the storage film 24, and the top film 25. At this time, a plasma insulating film 27 is also formed on the surface of the semiconductor substrate 21. The same as the plasma insulating film 7 in the first embodiment, a plasma oxide film, a plasma nitride film, or a plasma oxynitride film can be formed as the plasma insulating film 27. The formation of the plasma insulating film 27 is preferably performed within a temperature range of 65 ° C under rc #, for example, it can also be performed at 45 ° C. Moreover, the extent of the plasma insulating film 27 is 9 nm or less, for example, about W8nni Due to the heat treatment at this time, the impurities embedded in the bit line will diffuse to the center of the channel, but in the present invention, the diffusion of the impurities embedded in the 20 彳 line can be reduced by low temperature treatment. Since the miniaturization of the element is limited by the breakdown current from the expansion layer, the present invention greatly helps the miniaturization of the element. Next, as shown in FIG. 10A and FIG. 10B, it is formed on the entire surface. Interlayer insulating film 28. The interlayer insulating film 28 is formed by, for example, depositing a silicon oxide film by a cvd method. 16 1222176 Next, a contact hole and a wiring are formed to complete a semiconductor memory device. The second embodiment is described separately. As shown in FIGS. 9A and 9B, the insulating film used to cover the side surface of the storage film 24 is the plasma insulating film 27. Therefore, as shown in FIG. 11, since the plasma insulating film 27 The thickness is substantially uniform throughout, so it is the same as the first embodiment Even if the maximum film thickness is not made as thick as a thermal oxide film, hydrogen intrusion and electron penetration when the interlayer insulating film 28 is formed can be prevented. As a result, the bird's beak can be made smaller, and the data can be erased and written. Efficiency. 10 In the semiconductor memory device of SONO_, during the data writing and erasing, the power is transmitted and received between the storage film composed of the silicon nitride film and the semiconductor substrate, and it is captured according to whether the power is captured. Information is read at the interface between the storage film and the channel insulation film below it and its vicinity. Therefore, as described above, by reducing the bird's beak, the charge can be easily received and received, thereby improving the efficiency of elimination, etc. The same as the first embodiment, it is possible to avoid the instability of the characteristics due to the non-uniformity of the film formation temperature and the segregation of phosphorus. Although the side wall insulating film is not formed on the side of the control gate 26 in the second embodiment However, a side wall insulating film can also be formed. The side wall insulating film can also be formed at the same time as the side wall insulating film of, for example, a transistor used to form a peripheral circuit. In addition, when forming a plasma oxide film, for example, 0, n, or NH groups are generated in the plasma atmosphere with A,%, and NH3 gas. At this time, the raw material gas used in the growth of the plasma insulating film may also contain rare metals such as Kr or Ar. The gas may also contain h2. 17 1222176 In addition, the plasma oxynitride film, the plasma oxynitride film formation method, and the plasma treatment device used for the formation are not particularly limited, and the following devices can also be used to form the electricity Plasma oxynitride film or plasma nitride film. Specifically, a plasma oxynitride film and a plasma nitride film are formed by using a plasma processing apparatus having a radiating linear slot antenna 5 as shown in FIG. 12. The electric and slurry processing apparatus 100 is composed of the following components, namely, a gate valve 102 which is connected to the machine group 101. It can be accommodated to have a body to be processed (in this embodiment, it is half V-body substrate 1) and during the plasma processing, the cooling jacket 103 of the processed object w, the processing chamber 105 of the susceptor 104, the south vacuum pump 106 connected to the processing chamber 10, the microwave source 110, and the antenna member 120 ; And the antenna member 120-from the high-frequency power supply 107 and a bias voltage constituting the ion mine 108, having a gas supply ring 131 and 141 of the gas supply system 13〇, 14〇; and a temperature control unit to be processed W is the temperature of the body to control the stimulation was on. The microwave source 110 is composed of, for example, a magnetron, and can generally generate a microwave of _ I5 2.45 GHz (for example, '5 kW). Then, the transmission form of the microwave is converted to the TM, TE or TEM mode by the mode converter 112. The antenna member 120 includes a temperature adjustment plate 122 and a storage member 23 (and a spring dielectric plate 230). The temperature adjustment plate 122 is connected to the temperature control device κι, and the storage member 123 is used to store the slow wave material and the slotted electrode (not shown) in contact with the slow wave material 124. This slotted electrode is called a radiating line slot antenna, RLSA or ultra-high-energy planar antenna. However, in this embodiment, other types of antennas are also applicable, for example, a one-layer structure waveguide antenna, a dielectric substrate parallel plate slot array, and the like. When using a plasma processing device having the aforementioned wheel-shaped slot antenna to form a film, it is desirable to set the plasma ion irradiation energy to 7 eV or less, and to set the plasma potential to 10 eV or less. In addition, the formation of the plasma insulating film may be performed by the aforementioned plasma treatment process, and may be performed by a series of steps including a plasma oxidation method, a plasma nitridation method, or at least one of the two. In addition, although the embodiment described above makes the present invention applicable to a floating gate type or a SONOS type, the form to which the present invention is applicable is not limited to this, and for example, it can also be applied to a MNOS type semiconductor memory device. When the present invention is applied to an S-type cast body memory device, a silicon oxide film and a silicon nitride film are sequentially stacked on a semiconductor wire and a storage insulating film is formed, and then an interrogation electrode is formed on the semiconductor substrate. Next, a plasma insulating film is formed on the surface of the storage insulating film and the gate electrode. The present invention 15 20 gate electrode or gate sand is formed by plasma treatment to cover the floating principle, and the pole is covered with an insulating film, so the characteristics of high temperature and heat stability can be eliminated. The efficiency of people and materials, and obtained [Simplified illustration of figure] The semiconductor rule is a cross-sectional view showing a manufacturing method related to the first embodiment of the present invention. Semiconductor Period (Γ # 第 2Β 图 shows the steps not related to the first embodiment of the present invention, and is a face-down view showing the steps down to the steps of Figures 1A and 1B. Circle 3 Α ★ The semiconductor device is related to the first implementation state of this document, and is a cross-sectional view showing the next step shown in Figs. 2A, 2B, 19 1222176. Figs. 4A, 4B show The method for manufacturing a semiconductor memory device according to the first embodiment of the present invention is a sectional view showing the next step of the steps shown in Figs. 3A and 3B. Figs. 5A and 5B are the same as those shown in Fig. 5A and 5B. The method for manufacturing a semiconductor memory device according to the first embodiment of the invention is a cross-sectional view showing the next step of the steps shown in Figs. 4A and 4B. Figs. 6A and 6B show the first embodiment of the present invention. The method for manufacturing a semiconductor memory device according to the embodiment is a cross-sectional view showing the next step of the steps shown in Figs. 5A and 5B. Fig. 7 shows the plasma insulation in the first embodiment of the present invention. A cross-sectional view of the state of the film 7. Figs. 8A and 8B show the same A cross-sectional view of a method of manufacturing a semiconductor memory device according to a second embodiment of the invention. Figures 9A and 9B show a method of manufacturing a semiconductor memory device according to the second embodiment of the invention, and are shown in Figure 8A, A cross-sectional view of the next step of the step shown in Fig. 8B. Figs. 10A and 10B show a method for manufacturing a semiconductor memory device related to the second embodiment of the present invention, and are shown in Figs. 9A and 9B. A cross-sectional view of the next step of the step shown in Fig. 20. Fig. 11 is a cross-sectional view showing the state of the plasma insulating film in the second embodiment of the present invention. Fig. 12 is a view showing the features available in the embodiment of the present invention. A schematic diagram of the general structure of a plasma processing device for a radiating linear slot antenna. 20 1222176 FIG. 13 is a cross-sectional view showing a manufacturing method of a conventional floating gate type memory. FIG. 14 is a view showing a conventional SONOS type A cross-sectional view of a manufacturing method of a memory. 5 [List of symbols of main elements of the formula] Bu 21, 5 Bu 61 ... Semiconductor substrate 29 ... Storage insulating film la, lb ... Diffusion layer 52 ... Channel oxide film 2 .. . Pieces of insulating film 53 ... floating gate 3 ... channel insulating film 54 ... inter-gate insulating film 4 ... floating gate 55 ... control gate 5 ... ΟΝΟ film 62 .. Bit line diffusion layer 6 ... control gate 63 ... channel oxide film 7 ... plasma insulating film 64 ... nitride film 9 ... low concentration diffusion layer 65 ... top film 10 ... side wall Insulating film 66 ... Storage insulating film 11 ... High-concentration diffusion layer 67 ... Gate electrode 12 ... Interlayer insulating film 68 ... Thermal oxide film 22 ... Bit line diffusion layer 100 ... Slurry processing device 23 ... channel insulation film 101 ... machine group 24 ... silicon nitride film 102 ... gate valve 25 ... top film 103 ... cooling jacket 26 ... control gate 104 ... receptor 27 ... Plasma insulation film 105 ... Processing chamber 28 ... Interlayer insulation film 106 ... High vacuum pump

21 1222176 107...偏壓用高頻電源 123…收納構件 108...匹配器 124…慢波材 110...微波源 130、140...氣體供給系統 112…模式變換器 131、141…氣體供給環 120…天線構件 150…溫度控制部 121...溫度控制裝置 122…溫度調節板 230...介電板 2221 1222176 107 ... Bias high-frequency power supply 123 ... Storage member 108 ... Matcher 124 ... Slow-wave material 110 ... Microwave source 130, 140 ... Gas supply system 112 ... Mode converters 131, 141 ... gas supply ring 120 ... antenna member 150 ... temperature control unit 121 ... temperature control device 122 ... temperature adjustment plate 230 ... dielectric plate 22

Claims (1)

拾、申請專利範圍: 1· 一種半導體記憶裝置,包含有·· 半導體基板; 堆疊閘極,係具有依序積層於前述半導體基板 上之通道絕緣膜、浮動閘極、閘極間絕緣膜及控制 閘極; 覆蓋絕緣膜,係用以覆蓋前述堆疊閘極;及 層間絕緣膜,係用以將業經前述覆蓋絕緣膜覆 蓋之前述堆疊閘極埋入者,其特徵在於·· 又’前述覆蓋絕緣膜係由選自於由電漿氧化 膜、電漿氮化膜及電漿氧氮化膜所構成之群之丨種絕 緣膜所構成。 2.如申請專利範圍第1項之半導體記憶裝置,其中於 前述浮動閘極導入磷。 •如申請專利範圍第1或2項之半導體記憶裝置,其 中前述覆蓋絕緣膜之厚度為9nm以下。 •如申睛專利範圍第1項之半導體記憶裝置,其中前 述浮動閘極中之不純物濃度為lx l〇18/cm3以上。 5·如申請專利範圍第1項之半導體記憶裝置,其中前 述閘極間絕緣膜之厚度為 40nm以下。 6.如申請專利範圍第1項之半導體記憶裝置,更具有 形成於前述覆蓋絕緣膜侧邊之側壁絕緣膜。 7· 種半導體記憶裝置,包含有: 半導體基板; 23 儲存絕緣膜,係形成於前述半導體基板上,且 包含具有電荷捕獲功能之氮化膜者; 閘極電極,係隔著前述儲存絕緣膜形成於前述 半導體基板上者; 覆蓋絕緣膜,係用以覆蓋前述儲存絕緣膜及前 述閘極電極者,·及 層間絕緣膜,係用以將業經前述覆蓋絕緣膜覆 蓋之前述儲存絕緣膜及前述閘極電極埋入者, 又,前述覆蓋絕緣膜係由選自於由電漿氧化 膜、電漿氮化膜及電漿氧氮化膜所構成之群之丨種絕 緣膜所構成。 8·如申請專利範圍第7項之半導體記憶裝置,其中於 前述閘極電極導入磷。 9·如申請專利範圍第7項之半導體記憶裝置,其中前 述儲存絕緣膜包括: 前述氮化膜;及 第1氧化膜,係形成於前述氮化膜與前述半導體 基板之間。 10.如申請專利範圍第9項之半導體記憶裝置,其中前 述儲存絕緣膜更包括形成於前述氮化膜與前述閘極 電極間之第2氧化膜。 11·如申請專利範圍第7項之半導體記憶裝置,更具有 形成於前述覆蓋絕緣膜側邊之側壁絕緣膜。 12· 一種半導體記憶裝置之製造方法,包括下列步驟: 24 形成包含依序積層於半導體基板上之通道絕緣 膜、浮動閘極'閘極間絕緣膜及控制閘極之堆疊閘 極; 於前述堆疊閘極之表面藉由包含電漿氧化法、 電漿氮化法或兩者其中一者之一連串步驟形成覆蓋 絕緣膜;及 形成用以將業經前述覆蓋絕緣膜覆蓋之前述堆 疊閘極埋入之層間絕緣膜。 13·如申請專利範圍第12項之半導體記憶裝置之製造方 去’更包括在形成前述覆蓋絕緣膜之步驟前,將磷 導入前述浮動閘極之步驟。 14·如申請專利範圍第12項之半導體記憶裝置之製造方 法’係將前述覆蓋絕緣膜之厚度設為9nm以下。 15·如申請專利範圍第12項之半導體記憶裝置之製造方 /套’係將前述浮動閘極中之不純物濃度設為1 χ l〇18/cm3 以上。 16·如申請專利範圍第12項之半導體記憶裝置之製造方 去’係將前述閘極間絕緣膜之厚度設為 40nm以下。 •如申請專利範圍第12項之半導體記憶裝置之製造方 去’更包括於前述絕緣膜之侧邊形成側壁絕緣膜之 步驟。 •申請專利範圍第12項之半導體記憶裝置之製造方 去’係於含有選自於由〇2、沁及nh3所構成之群之 至少1種分子之原料氣體之電漿之環境中進行用以 25 5 形成前述覆蓋絕緣膜之步驟。 置之製造方 以形成前述 19.如申請專利範圍第12項之半導體記憶裝 法’係在650°C以下之溫度範圍内進行用 覆蓋絕緣膜之步驟。 20. 一種半導體記«置之製造方法,包括下列步驟: 於半導録板上形成包含具㈣制獲功 氮化膜之儲存絕緣膜;Scope of patent application: 1. A semiconductor memory device including a semiconductor substrate; a stacked gate having a channel insulating film, a floating gate, an inter-gate insulating film and a control layer sequentially stacked on the semiconductor substrate; Gate; Covering insulating film to cover the aforementioned stacked gate; and Interlayer insulating film to embed the aforementioned stacked gate covered by the aforementioned covering insulating film, which is characterized by ... The film is composed of an insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film, and a plasma oxynitride film. 2. The semiconductor memory device according to item 1 of the patent application scope, wherein phosphorus is introduced into the floating gate. • For a semiconductor memory device in the scope of claims 1 or 2, the thickness of the aforementioned cover insulating film is 9 nm or less. • The semiconductor memory device as described in the first item of the patent scope, wherein the impurity concentration in the floating gate is 1x1018 / cm3 or more. 5. The semiconductor memory device according to item 1 of the application, wherein the thickness of the inter-gate insulating film is 40 nm or less. 6. The semiconductor memory device according to item 1 of the scope of patent application, further comprising a side wall insulating film formed on a side of the cover insulating film. 7. A semiconductor memory device including: a semiconductor substrate; 23 a storage insulating film formed on the semiconductor substrate and including a nitride film having a charge trapping function; a gate electrode formed through the storage insulating film On the aforementioned semiconductor substrate; a cover insulating film, which is used to cover the storage insulating film and the gate electrode, and an interlayer insulating film, which is used to cover the storage insulating film and the gate covered by the cover insulating film In the case where the electrode is embedded, the covering insulating film is composed of an insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film, and a plasma oxynitride film. 8. The semiconductor memory device according to item 7 of the patent application scope, wherein phosphorus is introduced into the gate electrode. 9. The semiconductor memory device according to item 7 of the application, wherein the storage insulating film includes: the aforementioned nitride film; and a first oxide film formed between the aforementioned nitride film and the aforementioned semiconductor substrate. 10. The semiconductor memory device according to item 9 of the application, wherein the storage insulating film further includes a second oxide film formed between the nitride film and the gate electrode. 11. The semiconductor memory device according to item 7 of the scope of patent application, further comprising a side wall insulating film formed on the side of the cover insulating film. 12. · A method for manufacturing a semiconductor memory device, comprising the following steps: 24 forming a stacked gate including a channel insulating film, a floating gate'-gate insulating film, and a control gate sequentially stacked on a semiconductor substrate; The surface of the gate electrode is formed by a series of steps including a plasma oxidation method, a plasma nitridation method, or one of the two to form a covering insulating film; and forming a layer for embedding the stacked gate covered by the covering insulating film. Interlayer insulation film. 13. The method of manufacturing a semiconductor memory device according to item 12 of the application, further includes a step of introducing phosphorus into the floating gate before the step of forming the aforementioned cover insulating film. 14. The method of manufacturing a semiconductor memory device according to item 12 of the scope of patent application 'is to set the thickness of the aforementioned cover insulating film to 9 nm or less. 15. The manufacturing method / set of the semiconductor memory device according to item 12 of the scope of the patent application is to set the impurity concentration in the floating gate to 1 x 1018 / cm3 or more. 16. The method of manufacturing a semiconductor memory device according to item 12 of the scope of patent application 'is to set the thickness of the foregoing inter-gate insulating film to 40 nm or less. • If the method of manufacturing a semiconductor memory device according to item 12 of the patent application 'further includes the step of forming a sidewall insulating film on the side of the aforementioned insulating film. • The manufacturer of the semiconductor memory device under the scope of patent application No. 12 is used in an environment containing a plasma containing at least one molecule of a raw material gas selected from the group consisting of 02, Qin, and nh3. 25 5 The step of forming the aforementioned cover insulating film. The manufacturing method for forming the semiconductor memory device according to item 12 of the aforementioned patent application method is to cover the insulating film in a temperature range below 650 ° C. 20. A method for manufacturing a semiconductor device, comprising the steps of: forming a storage insulating film including a nitride film having a work function on a semiconductor recording board; 於前述半導縣板上隔著前述儲存絕緣膜形 閘極電極; 10 ^ 於前述儲存絕緣膜及前述閘極電極之表面藉由 包含電聚氧化法、電漿氮化法或兩者盆中 連串步驟形成覆蓋絕緣膜;及 ' ~ 形成用以將業經前述覆蓋絕緣膜覆蓋之前述儲 15 存絕緣膜及前述閘極電極埋入之層間絕緣膜。- 15 21·如申請專利範圍第20項之半導體記憶裝置之製造方The aforementioned storage insulating film-shaped gate electrode is separated on the aforementioned semiconducting board; 10 ^ The surface of the aforementioned storage insulating film and the gate electrode is covered by an electropolymerization oxidation method, a plasma nitridation method, or both. A series of steps to form a cover insulating film; and to form an interlayer insulating film for embedding the storage insulating film and the gate electrode covered by the cover insulating film. -15 21 · Such as the manufacturer of the semiconductor memory device under the scope of patent application No. 20 法更包括在形成前述覆蓋絕緣膜之步驟前,將磷 導入前述閘極電極之步驟。 22·如申請專利範圍第2〇項之半導體記憶裝置之製造方 法’包括下列步驟·· 0 ^ 形成前述儲存絕緣膜; 於前述半導體基板上形成第1氧化膜;及 於前述第1氧化膜上形成前述氮化膜。 23·如申請專利範圍第22項之半導體記憶裝置之製造方 法’其中用以形成前述儲存絕緣膜之步驟更包括於 26 别述氮化膜上形成第2氧化膜之步驟。 24·如申請專利範圍第20項之半導體記憶裝置之製造方 法,更包括於前述絕緣膜之側邊形成側壁絕緣膜之 步驟。 25·如申請專利範圍第2〇項之半導體記憶裝置之製造方 去’係於含有選自於由〇2、乂及nH3所構成之群之 至少1種分子之原料氣體之電漿之環境中進行用以 形成前述覆蓋絕緣膜之步驟。 26.如申請專利範圍第25項之半導體記憶裝置之製造方 法’其中用以形成前述覆蓋絕緣膜之步驟包括於前 述每境中產生選自於至少由0基、N基及NH基所 構成之群之至少1種基的步驟。 27·如申請專利範圍第25項之半導體記憶裝置之製造方 去,其中別述原料氣體更含有稀有氣體。 28·如申請專利範圍第27項之半導體記憶裝置之製造方 法’其中前述稀有氣體含有選自於由Kr&Ar所構 成之群之至少一種分子。 29·如申請專利範圍第25項之半導體記憶裝置之製造方 法’其中前述原料氣體更含有h2。 3〇·如申請專利範圍第25項之半導體記憶裝置之製造方 去’其中在形成前述覆蓋絕緣膜之步驟中,前述電 衆之離子照射能量設為7eV以下。 31·如申請專利範圍第25項之半導體記憶裝置之製造方 去’其中在形成前述覆蓋絕緣膜之步驟中,前述電 1222176 漿之位能設為lOeV以下。 32·如申請專利範圍第25項之半導體記憶裝置之製造方 法’其中在形成前述覆蓋絕緣膜之步驟中,利用從 5 形成有多數縫隙之平面天線所放射之微波來激發葡 述原料氣體,藉此產生前述電漿。 33.如申請專利範圍第32項之半導體記憶裝置之製造方 法,係使用輻射線狀槽孔天線作為前述平面天線。 从如申請專利範圍第2G項之半導體記憶裝置之製造方 法,係於650°C以下之γ许銘阁咖& 10The method further includes a step of introducing phosphorus into the gate electrode before the step of forming the cover insulating film. 22. A method for manufacturing a semiconductor memory device according to the scope of application for patent No. 20 includes the following steps: 0 ^ forming the aforementioned storage insulating film; forming a first oxide film on the aforementioned semiconductor substrate; and on the aforementioned first oxide film The aforementioned nitride film is formed. 23. The method for manufacturing a semiconductor memory device according to item 22 of the application, wherein the step of forming the aforementioned storage insulating film further includes the step of forming a second oxide film on the other nitride film. 24. The method of manufacturing a semiconductor memory device as claimed in claim 20, further comprising the step of forming a sidewall insulating film on the side of the aforementioned insulating film. 25. If the manufacturer of a semiconductor memory device in the scope of application for patent No. 20 is to be used in an environment containing a plasma containing at least one molecule of a raw material gas selected from the group consisting of 0, 2, and nH3 A step for forming the aforementioned cover insulating film is performed. 26. The method of manufacturing a semiconductor memory device according to item 25 of the patent application, wherein the step of forming the aforementioned cover insulating film includes generating, in each of the foregoing circumstances, a member selected from the group consisting of at least 0, N, and NH groups. Group at least 1 base step. 27. If the manufacturer of the semiconductor memory device according to item 25 of the application, the raw material gas further contains a rare gas. 28. The method of manufacturing a semiconductor memory device according to item 27 of the patent application, wherein the aforementioned rare gas contains at least one molecule selected from the group consisting of Kr & Ar. 29. The method for manufacturing a semiconductor memory device according to the scope of application for patent No. 25 ', wherein the aforementioned raw material gas further contains h2. 30. The method of manufacturing a semiconductor memory device according to item 25 of the patent application, wherein in the step of forming the aforementioned cover insulating film, the ion irradiation energy of the aforementioned public is set to 7 eV or less. 31. If the method of manufacturing a semiconductor memory device according to item 25 of the patent application is to be used ′, in the step of forming the aforementioned cover insulating film, the position of the aforementioned electrical 1222176 paste can be set to 10 OV or less. 32. The method for manufacturing a semiconductor memory device according to item 25 of the patent application, wherein in the step of forming the aforementioned cover insulating film, microwaves radiated from a planar antenna having a large number of slots are used to excite the source gas in Portuguese. This results in the aforementioned plasma. 33. A method for manufacturing a semiconductor memory device according to item 32 of the scope of patent application, using a radiating linear slot antenna as the aforementioned planar antenna. From the method of manufacturing a semiconductor memory device, such as the scope of application for patent 2G, γ Xu Ming Ge Ka & 10 below 650 ° C 下之/皿度範圍内進行用以形成前述 覆蓋絕緣膜之步驟。The steps for forming the aforementioned cover insulating film are performed within the following range. 2828
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