KR20060009810A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

A tunnel insulating film (3) is formed in an element region demarcated by an element isolation insulating film (2). For each memory cell, a floating gate (4), an ONO film (5), and a control gate (6) are formed, and then a plasma insulating film (7) is formed on the surface of a stacked gate. The plasma insulating film is immune to the direction of crystal plane of the base film. Therefore, the thickness of the plasma insulating film (7) is substantially uniform as a whole. As a result, hydrogen is prevented from entering when an insulating film is formed even though the maximum thickness needs not to be as great as that of the thermal oxide film. Further, electrons are prevented from emerging. By decreasing the thickness of the insulating film, the size of the bird's beak can be decreased, and the efficiency of erase/write of data can be enhanced.

Description

Semiconductor memory device and manufacturing method therefor {SEMICONDUCTOR STORAGE DEVICE AND ITS MANUFACTURING METHOD}

The present invention relates to a semiconductor memory device suitable for a flash memory and a method of manufacturing the same.

A flash memory is a nonvolatile semiconductor memory device for storing data by holding charge in a storage film such as a floating gate or a nitride film under a gate electrode. When charge is accumulated in the floating gate, charge transfer is performed between the channel and the floating gate through the gate insulating film. When charge is accumulated in the nitride film in the ONO film as a storage film, charge is stored in the insulating film itself. Therefore, the electrical characteristics of these insulating films need to be stable. When the characteristics of these insulating films are unstable, even when the same control voltage is applied, there is a possibility that a state in which data of "0" is stored in a certain memory cell may be stored in another memory cell. Therefore, the reliability is considerably lowered.

In addition to these insulating films, stable characteristics are also required for insulating films formed around floating gates or gate electrodes. This insulating film is formed for the following purposes. After the floating gates or gate electrodes are formed, sidewall insulating films for later forming the LDD structure are formed laterally, and an interlayer insulating film covering the floating gates or gate electrodes is formed. At this time, if the floating gate or the gate electrode is in direct contact with the sidewall insulating film or the interlayer insulating film, electrons may escape from the floating gate or the gate electrode to the sidewall insulating film or the like. As a result, the electrical characteristics of the floating gate or gate electrode are varied. In addition, in the process for forming a sidewall insulating film and an interlayer insulation film, the gas containing hydrogen may be used. At this time, when this hydrogen reaches the gate insulating film or the storage film, hydrogen deterioration or the like occurs, and the characteristics of the gate insulating film or the storage film are changed.

In order to prevent such fluctuations, an insulating film is formed around the gate electrode. And this insulating film is formed by thermal oxidation about 900 degreeC so that it may become thickness of 12 nm or more in the thickest part in order to achieve such an objective. The thickness of the insulating film is set to 12 nm or more in the thickest portion, so that when the oxide film is formed by thermal oxidation, the surface orientation of the silicon film constituting the base, for example, the gate electrode, is used. ), The growth rate of the oxide film varies. This is because the thickness of the thermal oxide film is nonuniform, and in order to sufficiently prevent the intrusion of hydrogen even in the thinnest part, this thickness is required.

13 is a cross-sectional view showing a conventional method for manufacturing a floating gate type memory. In this conventional manufacturing method, a stacked gate made of a tunnel oxide film 52, a floating gate 53, an inter-gate insulating film 54, and a control gate 55 is formed on a semiconductor substrate 51, and then a column is formed. Oxidation is carried out. As a result, as shown in FIG. 13, large unevenness | corrugation exists and the thermal oxide film 56 whose thickness is nonuniform is formed.

14 is a cross-sectional view showing a conventional method for manufacturing a SONOS type memory. In this conventional manufacturing method, the bit line diffusion layer 62 is formed on the surface of the semiconductor substrate 61, and the storage insulating film which consists of the tunnel oxide film 63, the nitride film 64, and the upper layer film 65 on it. Form 66. A gate electrode 67 is formed on the storage insulating film 66, and then thermal oxidation is performed. As a result, as shown in FIG. 14, large unevenness | corrugation exists and the thermal oxidation film 68 with the thickness nonuniformity is formed.

However, in the semiconductor memory device formed by the above-described method, the bird's beak is large and the coupling is reduced. This coupling degradation is associated with the problem that the erase efficiency is lowered. In particular, in the memory in which the erase is performed near the end of the gate electrode and in the memory in which the erase is performed in the entire channel, the decrease in the erase efficiency is remarkable. In addition, since the insulation film of the portion becomes thicker with the occurrence of the buzz beak, not only the erase efficiency but also the data write efficiency is lowered.

There is also a problem that it is difficult to stabilize the characteristics of the finally manufactured semiconductor memory device. One of the causes is that a plurality of wafer processes are performed at the same time when thermal oxidation is performed, but it is very difficult to keep the temperature in the furnace constant at this time. In addition, one of the causes is that impurities such as phosphorous introduced into the floating gate and the like tend to segregate at its edges as a result of thermal oxidation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory device capable of improving the efficiency at the time of erasing and writing data and stabilizing characteristics thereof, and a manufacturing method thereof.

As a result of earnest examination, the inventors of the present invention perform thermal oxidation to form an oxide film covering a laminated gate or the like in the conventional method of manufacturing a semiconductor memory device, so that formation of a large buzz bequee and segregation of impurities occurs. Found. The inventors of the present invention have found that the above-described drawbacks can be eliminated by employing plasma treatment as a method of forming a good and dense insulating film without performing thermal oxidation, and thus have reached all aspects of the invention shown below.

In the method of manufacturing a first semiconductor memory device according to the present invention, after forming a laminated gate including a tunnel insulating film, a floating gate, an inter-gate insulating film, and a control gate, which are sequentially stacked on a semiconductor substrate, a plasma oxidation method is formed on the surface of the laminated gate. The insulating film is formed by a plasma nitriding method or a series of processes including any one of them, and an interlayer insulating film is formed in which the laminated gate covered with the covering insulating film is embedded.

A first semiconductor memory device according to the present invention manufactured by such a method includes a semiconductor substrate, a laminated gate including a tunnel insulating film, a floating gate, an inter-gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, and the stacked gate. And an interlayer insulating film filling the laminated gate covered with the covering insulating film. The semiconductor memory device is characterized in that the covering insulating film is made of one kind of insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film and a plasma oxynitride film.

In addition, in the method for manufacturing a second semiconductor memory device according to the present invention, a storage insulating film including a nitride film having a charge trapping function is formed on a semiconductor substrate, and a gate electrode is formed on the semiconductor substrate through the storage insulating film. Thereafter, a coating insulating film is formed on the surfaces of the storage insulating film and the gate electrode by a plasma oxidation method, a plasma nitridation method, or a series of processes including any of the above, and the storage insulating film and the cover insulating film are covered with the coating insulating film. An interlayer insulating film filling the gate electrode is formed.

A second semiconductor memory device according to the present invention manufactured by such a method comprises a storage insulating film comprising a semiconductor substrate, a nitride insulating film formed on the semiconductor substrate, and having a charge trapping function, and on the semiconductor substrate via the storage insulating film. And a gate insulating film formed thereon, a coating insulating film covering the storage insulating film and the gate electrode, an interlayer insulating film filling the storage insulating film and the gate electrode covered with the coating insulating film. The semiconductor memory device is characterized in that the covering insulating film is made of one kind of insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film and a plasma oxynitride film.

1A and 1B are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the first embodiment of the present invention.

2 (a) and 2 (b) are diagrams illustrating a method of manufacturing the semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing the steps following the steps shown in FIGS. .

3A and 3B are diagrams illustrating a method of manufacturing a semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing the steps following the steps shown in FIGS. 2A and 2B. .

4A and 4B are diagrams illustrating a method of manufacturing the semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing the steps following the steps shown in FIGS. 3A and 3B. .

5A and 5B are diagrams illustrating a method of manufacturing the semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing the steps following the steps shown in FIGS. 4A and 4B. .

6 (a) and 6 (b) are diagrams illustrating a method of manufacturing a semiconductor memory device according to the first embodiment of the present invention, and are cross-sectional views showing the steps following the steps shown in FIGS. .

Fig. 7 is a sectional view showing a state of the plasma insulating film 7 in the first embodiment of the present invention.

8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the second embodiment of the present invention.

9A and 9B are diagrams illustrating a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention, and are cross-sectional views showing the steps following the steps shown in FIGS. 8A and 8B. .

10A and 10B are diagrams illustrating a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention, and show cross-sectional views of steps following the steps shown in FIGS. 9A and 9B. .

Fig. 11 is a sectional view showing a state of the plasma insulating film in the second embodiment of the present invention.

Fig. 12 is a schematic diagram showing a schematic configuration of a plasma processing apparatus having a radial line slot antenna that can be used in the embodiment of the present invention.

Fig. 13 is a sectional view showing a conventional method for manufacturing a floating gate type memory.

Fig. 14 is a sectional view showing a conventional method for manufacturing a SONOS type memory.

EMBODIMENT OF THE INVENTION Hereinafter, the semiconductor memory device and its manufacturing method which concern on an Example of this invention are demonstrated concretely with reference to an accompanying drawing. In addition, the structure of a semiconductor memory device is demonstrated with the formation method for convenience.

(First embodiment)

First, the first embodiment of the present invention will be described. In the first embodiment, the present invention is applied to a semiconductor memory device having a stacked gate structure. 1 (a), 1 (b) to 6 (a), and 6 (b) are cross-sectional views showing the manufacturing method of the semiconductor memory device according to the first embodiment of the present invention in the order of steps.

In the semiconductor memory device according to the first embodiment, a plurality of word lines and bit lines are formed in a lattice shape so as to be perpendicular to each other. One memory cell is formed near each grid point. 1 (b) to 6 (a) correspond to the cross section orthogonal to the bit line, and FIGS. 1 (b) to 6 (b) correspond to the cross section orthogonal to the word line. Therefore, in FIG. 1 (a) and FIG. 1 (b), the cross section orthogonal to each other is shown. The same applies to other Figs. 2 (a), 2 (b) to 6 (a) and 6 (b).

In the present embodiment, when manufacturing a semiconductor memory device having the above-described layout configuration, first, as shown in Figs. 1A and 1B, the semiconductor substrate 1, such as a silicon substrate, is placed on the surface. For example, the element isolation insulating film 2 is formed by the LOCOS method. Next, in order to prevent punch-through below the element isolation insulating film 2, the diffusion layer 1a is formed by ion implanting impurities such as boron into the entire surface. In addition, in order to adjust the threshold voltage of the memory cell, the diffusion layer 1b is formed by ion implantation of impurities such as boron into the element region partitioned by the element isolation insulating film 2.

In forming these word lines, bit lines, and LOCOS, the narrower the minimum line width, the more effective the present invention is. Specifically, it is effective when it is 0.5 micrometer or less, and it is especially remarkable when it is 0.25 micrometer or less. This is because a narrow line width makes it impossible to ignore the width of Buzzbeek. This is also the same in the second embodiment.

Next, a tunnel insulating film 3 made of, for example, a silicon oxide film is formed in the device region partitioned by the device isolation insulating film 2. Thereafter, a floating gate 4 is formed for each memory cell, and an ONO film (inter-gate insulating film) 5 and a control gate (word line) 6 are formed. When the floating gate 4 is formed, for example, after the polysilicon film is formed, impurities such as boron are introduced into the polysilicon film by ion implantation, for example. The ONO film 5 is composed of a silicon nitride film, a silicon oxide film, and a silicon nitride film that are sequentially stacked. The laminated gate is composed of a laminate of the tunnel insulating film 3, the floating gate 4, the ONO film 5, and the control gate 6.

At this time, the deeper the impurity concentration in the floating gate, the more the effect of the present invention is exerted. Specifically, it is effective if it is 1x10 <^18> / cm <3> or more, and it is especially remarkable if it is about 1x10 <^19> / cm <3>. This is because segregation of impurities occurs in the high temperature heat treatment and deterioration of the quality of the insulating film around the floating gate does not occur in the sidewall film formation by the low temperature oxidation, nitridation and oxynitride, which is a feature of the present invention. This segregation is particularly remarkable when the impurity is phosphorus (P).

In the formation of the ONO film 5, the thinner the thickness, the more the effect of the present invention is exhibited. Specifically, it is effective when the physical film thickness is 40 nm or less as a whole, and particularly remarkable when it is 20 nm or less. This is because, if the ONO film is thin, the thickness of the Buzzbeek cannot be ignored compared with the thickness of the ONO film itself. Specifically, the bottom oxide film of the ONO film is remarkable at 10 nm or less, in particular 7 nm or less, the nitride film is remarkable at 20 nm or less, particularly 10 nm or less, and the top oxide film is 10 nm or less, especially 7 nm or less. It is remarkable below. This is also the same in the second embodiment.

Subsequently, as shown in FIGS. 2A and 2B, the top and side surfaces of the control gate 6 and the side surfaces of the ONO film 5, the floating gate 4, and the tunnel insulating film 3, that is, the stacked gates. On the surface of the plasma insulating film (coating insulating film) 7 is formed. At this time, the plasma insulating film 7 is formed on the surface of the semiconductor substrate 1. As the plasma insulating film 7, a plasma oxide film, a plasma nitride film or a plasma oxynitride film can be formed. The formation of the plasma insulating film 7 is preferably performed at a temperature range of 650 ° C. or lower, and may be, for example, about 450 ° C. In addition, the thickness of the plasma insulating film 7 is preferably 9 nm or less, for example, about 8 nm.

Subsequently, ion implantation is performed using the laminated gate as a mask, and further heat treatment is performed to form the low concentration diffusion layer 9 in a self-aligned manner as shown in FIGS. 3A and 3B.

At this time, the low concentration diffusion layer is diffused under the gate by the heat treatment, but the reach distance from the gate edge must be secured to at least exceed the Buzzbeek. In the present invention, it is possible to reduce the inflow below the gate of the low concentration diffusion layer by suppressing the Burj beak. Since the miniaturization of the device is limited by the punch-through current from this diffusion layer, the present invention greatly contributes to the miniaturization of the device.

Next, as shown in FIGS. 4A and 4B, the sidewall insulating film 10 is formed on the side surfaces of the stacked gates. The side wall insulating film 10 is formed by, for example, forming an HTO film (high temperature oxide film) and then isotropically etching it. By this isotropic etching, a portion of the plasma insulating film 7 formed on the surface of the semiconductor substrate 1 that is not finally covered by the sidewall insulating film 10 is removed, and a part of the surface of the semiconductor substrate 1 is exposed.

Thereafter, as shown in Figs. 5A and 5B, ion implantation is performed at a higher concentration than when the low concentration diffusion layer 9 is formed using the laminated gate and the sidewall insulating film 10 as a mask, and the heat treatment is performed. By further performing, the high concentration diffusion layer 11 is formed.

Subsequently, as shown in Figs. 6A and 6B, an interlayer insulating film 12 is formed over the entire surface. The interlayer insulating film 12 is formed by depositing a silicon oxide film by, for example, CVD.

Subsequently, contact holes and wirings are formed to complete the semiconductor memory device.

In this first embodiment, as shown in Figs. 2A and 2B, the insulating film covering the laminated gate is the plasma insulating film 7. Unlike the thermal oxide film, the plasma insulating film is not affected by the surface orientation of the underlying film. Therefore, as shown in Fig. 7, the thickness of the plasma insulating film 7 becomes substantially uniform throughout, so that the sidewall insulating film 10 or the interlayer insulating film 12 is not required to be as thick as the thermal oxide film. Intrusion of hydrogen at the time of formation can be prevented, and an electron escape can also be prevented. By reducing the thickness of the insulating film, the buzz beak can be reduced, and the efficiency of erasing and writing data can be improved.

In the floating gate type semiconductor memory device, charge transfer is performed between the floating gate and the semiconductor substrate at the time of writing and erasing data, and information is read depending on whether or not the charge is trapped in the floating gate. Therefore, since the transfer of charge becomes easy to be performed by reducing the Buzzbee as described above, the efficiency of erasing or the like is improved.

In the formation of the plasma insulating film 7, the processing of a plurality of wafers in one heating furnace is not performed. Therefore, it is not affected by the nonuniformity of the temperature in the furnace. In addition, the plasma insulating film 7 can be formed at a considerably lower temperature than the thermal oxide film. Therefore, segregation of impurities such as phosphorus in the floating gate 4 is unlikely to occur considerably. For this reason, a semiconductor memory device having stable characteristics among a plurality of wafers can be obtained.

(Second embodiment)

Next, a second embodiment of the present invention will be described. The second embodiment applies the present invention to a so-called SONOS structure semiconductor memory device. 8 (a), 8 (b) to 10 (a), and 10 (b) are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention in the order of steps. The SONOS structure has a buried bit line structure as a structure of a nitride film charge accumulation memory having a source / drain for both a buried bit line and a channel parallel to a word line (gate electrode).

Also in the second embodiment, a plurality of word lines and bit lines are formed in a lattice shape so as to be orthogonal to each other. One memory cell is formed in the vicinity of each lattice point. As in the first embodiment, Figs. 8A to 10A correspond to cross sections orthogonal to the bit lines, and Figs. 8B to 10B are orthogonal to the word lines. It corresponds to the cross section. Therefore, cross sections orthogonal to each other are shown in FIGS. 8A and 8B. The same applies to other Figs. 9 (a), 9 (b), 10 (a) and 10 (b).

In the present embodiment, when manufacturing the semiconductor memory device having the layout configuration as described above, first, as shown in Figs. 8A and 8B, a resist is formed on the surface of a semiconductor substrate 21 such as a silicon substrate. By performing ion implantation using the film as a mask, a bit line diffusion layer (bit line) 22 is formed.

Next, the silicon oxide film, the silicon nitride film, the silicon oxide film, and the polysilicon film are sequentially stacked and patterned, so that the tunnel insulating film 23, the silicon nitride film 24, the upper film 25, and the control gate (word line) Gate electrode)) 26 to form a laminate. When the control gate 26 is formed, for example, after forming a polysilicon film, impurities such as boron are introduced into the polysilicon film by ion implantation, for example. The tunnel insulating film 23 is made of a silicon oxide film, and the upper film 25 is made of a silicon oxide film. The storage insulating film 29 is composed of the tunnel insulating film 23, the silicon nitride film 24, and the upper film 25. In addition, the control gate 26 is made of a polysilicon film.

Thereafter, as shown in FIGS. 9A and 9B, the plasma insulating film is formed on the top and side surfaces of the control gate 26, the tunnel insulating film 23, the storage film 24, and the top film 25. A coating insulating film 27 is formed. At this time, the plasma insulating film 27 is also formed on the surface of the semiconductor substrate 21. As the plasma insulating film 27, a plasma oxide film, a plasma nitride film or a plasma oxynitride film can be formed similarly to the plasma insulating film 7 in the first embodiment. It is preferable to form this plasma insulating film 27 at the temperature range of 650 degreeC or less, for example, can also be performed at about 450 degreeC. In addition, the thickness of the plasma insulating film 27 is preferably 9 nm or less, for example, about 8 nm.

By the heat treatment at this time, the impurities in the buried bit lines are diffused toward the center of the channel, but in the present invention, the diffusion of impurities in the buried bit lines can be reduced by low temperature treatment. Since the miniaturization of the device is limited by the punch-through current from this diffusion layer, the present invention greatly contributes to the miniaturization of the device.

Subsequently, as shown in FIGS. 10A and 10B, an interlayer insulating film 28 is formed over the entire surface. The interlayer insulating film 28 is formed by depositing a silicon oxide film by, for example, CVD.

Then, contact holes and wirings are formed to complete the semiconductor memory device.

Also in this second embodiment, as shown in FIGS. 9A and 9B, the insulating film covering the side surface of the storage film 24 is used as the plasma insulating film 27. Therefore, as shown in FIG. 11, since the thickness of the plasma insulating film 27 becomes substantially uniform throughout, the interlayer insulating film (even if the maximum film thickness is not as thick as that of the thermal oxide film) as in the first embodiment. 28) can be prevented from invading hydrogen and releasing electrons. As a result, it is possible to suppress the Buzzbee small and improve the efficiency of erasing and writing data.

In the SONOS type semiconductor memory device, charge transfer is performed between a storage film made of a silicon nitride film and a semiconductor substrate at the time of data writing and erasing, and at the interface between the storage film and the tunnel insulating film below it, and the vicinity thereof. The information is read depending on whether or not the charge is trapped. Therefore, since the transfer of charge becomes easy to be performed by reducing the Buzzbee as described above, the efficiency of erasing or the like is improved.

In addition, in the same manner as in the first embodiment, destabilization of characteristics caused by nonuniformity of film formation temperature and segregation of phosphorus can be avoided.

In the second embodiment, the sidewall insulating film is not formed on the side of the control gate 26, but the sidewall insulating film may be formed. This sidewall insulating film may be formed simultaneously with the sidewall insulating film of a transistor constituting the peripheral circuit, for example.

In the formation of the plasma oxide film, for example, radical O *, radical N * or radical NH * is generated in a plasma atmosphere of a gas containing O ₂ , N ₂ or NH ₃ . At this time, the source gas used at the time of growth of the plasma insulating film may contain a rare gas such as Kr or Ar, or may contain H ₂ .

In addition, the plasma oxynitride film and the plasma nitride film formation method and the plasma processing apparatus used for formation are not specifically limited, A plasma oxynitride film or a plasma nitride film can also be formed using the following apparatus.

Specifically, a plasma oxynitride film or plasma nitride film is formed using a plasma processing apparatus having a radial line slot antenna as shown in FIG. The plasma processing apparatus 100 includes a gate valve 102 in communication with a cluster tool 101, and an object to be processed W (in this embodiment, the semiconductor substrate 1). Is connected to the processing chamber 105 and the processing chamber 105 capable of storing a susceptor 104 having a cooling jacket 103 for cooling the target object W during plasma processing. A high vacuum pump 106, a microwave source 110, an antenna member 120, a bias high frequency power supply 107 and a matching box 108 constituting ion plating together with the antenna member 120, The gas supply systems 130 and 140 having the gas supply rings 131 and 141 and the temperature control part 150 which controls the temperature of the to-be-processed object W are comprised.

The microwave source 110 is made of, for example, a magnetron, and can usually generate 2.45 GHz of microwaves (for example, 5 GHz). The microwave is then converted by the mode converter 112 into a TM, TE or TEM mode or the like.

The antenna member 120 has a temperature control plate 122 and a storage member 123 (dielectric plate 230). The temperature control plate 122 is connected to the temperature control device 121, and the housing member 123 accommodates the slow wave material 124 and the slot electrode (not shown) in contact with the slow wave material 124. have. This slot electrode is called a radial line slot antenna (RLSA) or an ultra-high efficiency planar antenna. In this embodiment, however, other types of antennas, for example, a single-layer waveguide planar antenna, a dielectric substrate parallel flat slot array, and the like may be applied.

When performing film formation using a plasma processing apparatus equipped with such a radial line slot antenna, the ion irradiation energy of the plasma is preferably 7 eV or less, and the potential energy of the plasma is preferably 10 eV or less.

The plasma insulating film can be formed by a plasma oxidation method, a plasma nitridation method, or a series of steps including at least any one of them using the above-described plasma processing apparatus.

In addition, although the above-mentioned embodiment applies this invention to a floating gate type or a SONOS type, the form which can apply this invention is not limited to these. For example, the present invention can also be applied to an MNOS type semiconductor memory device. When the present invention is applied to an MNOS type semiconductor memory device, a silicon oxide film and a silicon nitride film are sequentially stacked on a semiconductor substrate to form a storage insulating film, and then a gate electrode is formed thereon. Subsequently, a plasma insulating film is formed on the surfaces of the storage insulating film and the gate electrode.

According to the present invention, since the coating insulating film covering the floating gate or the gate electrode is formed by plasma treatment, it does not require a high temperature heat treatment, suppresses the buzz beak, and has high efficiency of writing and erasing, and stable characteristics. Can be obtained.

Claims (34)

A semiconductor substrate, A stacked gate including a tunnel insulating layer, a floating gate, an inter-gate insulating layer, and a control gate, which are sequentially stacked on the semiconductor substrate; A covering insulating film covering the stack gate; A semiconductor memory device having an interlayer insulating film for filling the stacked gate covered with the covering insulating film, And the coating insulating film is formed of one type of insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film and a plasma oxynitride film. The method of claim 1, Phosphorus is introduced into the floating gate. The method according to claim 1 or 2, And the thickness of the covering insulating film is 9 nm or less. The method of claim 1, And the impurity concentration in the floating gate is 1 × 10 ¹⁸ / cm 3 or more. The method of claim 1, And the thickness of the inter-gate insulating film is 40 nm or less. The method of claim 1, And a sidewall insulating film formed on a side of said covering insulating film. A semiconductor substrate, A storage insulating film formed on the semiconductor substrate and including a nitride film having a charge trapping function; A gate electrode formed on the semiconductor substrate through the storage insulating layer; A covering insulating film covering the storage insulating film and the gate electrode; A semiconductor memory device having the storage insulating film covered with the covering insulating film and an interlayer insulating film filling the gate electrode. And the coating insulating film is formed of one type of insulating film selected from the group consisting of a plasma oxide film, a plasma nitride film and a plasma oxynitride film. The method of claim 7, wherein Phosphorus is introduced into the gate electrode. The method of claim 7, wherein The storage insulating film is the nitride film, And a first oxide film formed between the nitride film and the semiconductor substrate. The method of claim 9, And said storage insulating film further has a second oxide film formed between said nitride film and said gate electrode. The method of claim 7, wherein And a sidewall insulating film formed on the side of said covering insulating film.  Forming a stacked gate including a tunnel insulating film, a floating gate, an inter-gate insulating film, and a control gate sequentially stacked on the semiconductor substrate; Forming a coating insulating film on the surface of the laminated gate by a series of processes including any one of plasma oxidizing method, plasma nitriding method, and the like; And forming an interlayer insulating film filling the laminated gate covered with the covering insulating film. The method of claim 12, And a step of introducing phosphorus into the floating gate before the step of forming the coating insulating film. The method of claim 12, The thickness of the said coating insulating film is 9 nm or less, The manufacturing method of the semiconductor memory device characterized by the above-mentioned. The method of claim 12, The impurity concentration in the floating gate is 1 × 10 ¹⁸ / cm 3 or more. The method of claim 12, A method of manufacturing a semiconductor memory device, characterized in that the thickness of said inter-gate insulating film is 40 nm or less. The method of claim 12, And forming a sidewall insulating film on the side of said insulating film. The method of claim 12, And forming the coating insulating film in a plasma atmosphere of a source gas containing at least one molecule selected from the group consisting of O ₂ , N ₂ and NH ₃ . The method of claim 12, A method of manufacturing a semiconductor memory device, characterized in that the step of forming the coating insulating film is performed within a temperature range of 650 ° C or lower. Forming a storage insulating film including a nitride film having a charge trapping function on the semiconductor substrate; Forming a gate electrode on the semiconductor substrate through the storage insulating layer; Forming a coating insulating film on the surfaces of the storage insulating film and the gate electrode by a plasma oxidation method, a plasma nitridation method, or a series of steps including any one of them; And forming an interlayer insulating film filling said storage insulating film and said gate electrode covered with said covering insulating film. The method of claim 20, And a step of introducing phosphorus into the gate electrode before the step of forming the coating insulating film. The method of claim 20, The forming of the storage insulating layer may include forming a first oxide layer on the semiconductor substrate; And a step of forming the nitride film on the first oxide film. The method of claim 22, And the step of forming the storage insulating film further comprises forming a second oxide film on the nitride film. The method of claim 20, And forming a sidewall insulating film on the side of said insulating film. The method of claim 20, And forming the coating insulating film in a plasma atmosphere of a source gas containing at least one molecule selected from the group consisting of O ₂ , N ₂ and NH ₃ . The method of claim 25, The step of forming the coating insulating film includes a step of generating at least one radical selected from the group consisting of at least radical O *, radical N *, and radical NH * in the atmosphere. Method of preparation. The method of claim 25, And the source gas further contains a rare gas. The method of claim 27, The rare gas comprises at least one molecule selected from the group consisting of Kr and Ar. The method of claim 25, The raw material gas further contains H ₂ . The method of claim 25, A method of manufacturing a semiconductor memory device, characterized in that, in the step of forming the coating insulating film, ion irradiation energy of the plasma is set to 7 eV or less. The method of claim 25, In the step of forming the coating insulating film, the potential energy of the plasma is set to 10 eV or less. The method of claim 25, And in the step of forming the coating insulating film, the plasma is generated by exciting the source gas using microwaves radiated from a planar antenna on which a plurality of slits are formed. The method of claim 32, And a radial line slot antenna is used as the planar antenna. The method of claim 20, A method of manufacturing a semiconductor memory device, characterized in that the step of forming the coating insulating film is performed within a temperature range of 650 ° C or lower.

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