KR100493004B1 - Non volatile memory device having improved program and erase effeciency and fabricating method therefor - Google Patents

Abstract

Disclosed are a nonvolatile memory device having improved program and erase efficiency and a method of manufacturing the same. A nonvolatile memory device according to the present invention includes a semiconductor substrate which is divided into an active region and an isolation region, and has a recess having an inclined surface having a predetermined angle on a surface of a region in which a source and a drain are to be formed in the active region, and a neighboring recess. A gate electrode pattern of a memory cell formed on a surface of a semiconductor substrate disposed between the recesses and having a gate insulating film, a floating gate, an interlayer insulating film, and a control gate stacked thereon, and a source and a drain formed under the recesses disposed on both sides of the gate electrode pattern; The source and drain and the floating gate portion overlap with each other through the inclined surface of the recess.

Description

Non volatile memory device having improved program and erase effeciency and fabricating method therefor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device and a method of manufacturing the same having improved program and erase efficiency through an increase in electric field.

Nonvolatile memory devices, such as flash memory devices, are generally divided into NOR and NAND types. Unlike NAND flash memory devices having 8 or 16 cell transistors connected in series on one bit line, NOR flash memory devices have multiple cell transistors connected in parallel on one bit line. Therefore, the NAND flash memory, which is advantageous for high integration due to its small cell size, is mainly used for a large-capacity memory device and can store and read information in a plurality of cells connected in parallel to one bit line. Flash memory is widely used in computers and communication devices.

However, Noah type flash memory uses a flow diagram method using channel hot electrons and a source erasing method using Fowler-Nordheim (F-N) tunneling. Therefore, a sufficient source overlap region must be secured, a high voltage of about 10V is required for F-N tunneling, and a program and erase time according to hot electron injection efficiency is required.

Meanwhile, as the integration and speed of semiconductor memory devices are accelerated, efforts have been made to store more information in a smaller area. This tendency to speed up is a factor that increases the power consumption of the memory device. In particular, as the demand for products using a battery as a power source, such as a notebook or a portable communication device, has increased recently, various studies on how to minimize the power consumption of a memory device have been conducted. .

Therefore, even in a nonvolatile memory device, in order to achieve low voltage and low power consumption, it is required to increase the hot electron injection efficiency or to reduce the program and erase voltages.

Accordingly, an object of the present invention is to provide a nonvolatile memory device capable of increasing hot electron injection efficiency and lowering program and erase voltages.

Another object of the present invention is to provide a manufacturing method suitable for manufacturing the nonvolatile memory device.

A nonvolatile memory device according to the present invention for achieving the above object is divided into an active region and a device isolation region, the semiconductor is formed with a recess having an inclined surface of a predetermined angle on the surface of the region in which the source and drain will be formed A gate electrode pattern of a memory cell formed on a surface of a semiconductor substrate positioned between a substrate and a neighboring recess, and having a gate insulating film, a floating gate, an interlayer insulating film, and a control gate stacked thereon, and under a recess located on both sides of the gate electrode pattern. A source and a drain are formed, and the source and drain and the floating gate portion overlap with each other through the inclined surface of the recess.

The source and drain formed below the inclined surface are formed at a lower concentration than at the center of the recess.

According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, the method including exposing a portion where a source and a drain are to be formed on one surface of a semiconductor substrate of a first conductivity type divided into an active region and an isolation region. A mask pattern is formed, the first mask pattern is applied as an etch mask, and the substrate is etched to a predetermined depth to form a recess having an inclined surface on the surface of the active region in which the source and the drain are to be formed. After removing the first mask pattern, a gate electrode pattern including a gate insulating film, a floating gate, an interlayer insulating film, and a control gate is formed on the entire surface of the resultant product. The recess consists of anisotropic etching of the substrate to a depth of about 20 nm to 100 nm. After anisotropic etching, anisotropic etching is performed after oxidation of a predetermined amount of substrate to prevent field leakage current or direct tunneling due to a sudden increase in the electric field. You may.

After the recess is formed, the first mask pattern is used as an ion implantation mask, and the second conductivity type impurities are implanted at low concentration, and after forming the gate electrode pattern, impurities for forming the source and drain of the memory cell are ionized at a high concentration. It is implanted to form a source and a drain in the substrate.

As a result, according to the present invention, the electric field between the floating gate and the substrate is increased to improve the injection efficiency of the channel hot electrons into the floating gate, thereby improving the program efficiency of the nonvolatile memory device. In addition, since the electric field is concentrated in the corner portion, the electric field intensity increases, so that the tunneling current between the floating gate and the source and drain is increased, thereby improving the erase efficiency.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and only the embodiments of the present invention may be completed by the present invention to those skilled in the art. It is provided to fully inform the category. In the embodiments disclosed below, when either film is referred to as being on another film or substrate, it is noted that it may be directly over the other film or substrate and an interlayer film may be present.

1 is a cross-sectional view of a nonvolatile memory cell according to a preferred embodiment of the present invention, wherein reference numeral 100 denotes a first conductive type semiconductor substrate, for example, a p-type semiconductor substrate, and 110 a gate insulating film. Denotes a floating gate, “130” denotes an interlayer insulating film, “140” denotes a control gate, and “150 and 160” denotes a source and a drain, respectively.

According to the cross-sectional view, the control gate 140 is stacked on the semiconductor substrate 100 with the floating gate 120 through which electrons can be injected and the interlayer insulating film 130 having a predetermined thickness interposed therebetween. A gate insulating layer 110 is formed between the floating gate 120 and the semiconductor substrate 100 to tunnel the channel hot electrons.

The interlayer insulating layer 130 may be, for example, an ONO structure in which an oxide layer, a nitride layer, and an oxide layer are stacked. The gate insulating layer 110 may be formed of an oxide layer or an oxynitride layer, and the floating gate 120 may be controlled. The gate 140 may be formed of polysilicon doped with impurities as in the general case. In addition, the source and drain 150 and 160 according to the preferred embodiment of the present invention may be formed of an LDD structure having low concentration regions 150 ′ and 160 ′ in a portion adjacent to the channel.

As shown, the memory cell according to the present invention has a source and drain 150 and 160 substrate level lower than a channel region, and has an inclined surface at an angle on the surface of the active region where the source and drain 150 and 160 are to be formed. A recess is formed. That is, an inclined surface is formed on the surface of the source and drain 120 edge portions adjacent to the channel region, and the inclined surface and the floating gate 140 sufficiently overlap with each other. Such inclined surfaces of the source and drain edge portions increase the electric field between the source and drain 150 and 160 and the floating gate 120 to improve program efficiency or erase efficiency. This will be described with reference to FIGS. 2A and 2B.

2A is a cross-sectional view illustrating the program efficiency improvement of the nonvolatile memory cell according to the present invention, and FIG. 2B is a cross-sectional view for explaining the improvement of the erase efficiency, and the same reference numerals as in FIG. 1 denote the same members.

Referring to FIG. 2A, a program operation of a nonvolatile memory cell is performed by injecting channel hot electrons into the floating gate 120 using a gate potential (+ Vg) and a drain potential (+ Vd) higher than the source potential Vs. By increasing the threshold voltage. At this time, the substrate voltage (-Vbb) or the ground voltage (Vss) is applied to the substrate 100, and the intensity of the electric field between the floating gate 120 and the substrate is directly related to the implantation efficiency of the floating gate 120 of the channel hot electrons. Affect That is, since the strength of the electric field is large due to the strengthening of the vertical electric field formed on the inclined surface, the injection efficiency of the channel hot electrons becomes considerably large.

In the nonvolatile memory cell configured as shown in FIG. 2A, since the source and drain surfaces adjacent to the channel are configured to be inclined, the flat gate as well as the inclined surface are included between the floating gate and the substrate. Therefore, in the cell proposed in the present invention, between the floating gate 120 and the substrate 100, the first electric field f1 in a direction perpendicular to the substrate and an angle of about 90 degrees or less with respect to the substrate are provided. The second electric field f2 is present. As a result, the effective electric field s may be expressed as a vector sum of the first electric field f1 and the second electric field f2, as shown, and the first electric field f ₁ and the second electric field are shown. It appears as a diagonal of a parallelogram with (f ₂ ) on each side.

That is, according to the present invention, the effective electric field s is increased to improve the injection efficiency of the channel hot electrons into the floating gate, and as a result, the program efficiency of the nonvolatile memory device is improved. In other words, the gate current increases even under low gate and drain voltages, thereby reducing the voltage applied to the device for programming, in particular the control gate voltage. This improved program efficiency allows the voltage applied to the control gate to be lowered, which not only reduces the boost voltage level, but also reduces the breakdown voltage that the individual transistors constituting the memory cell must withstand, thereby improving reliability of the nonvolatile memory device. It works.

Referring to FIG. 2B, the erase operation of the nonvolatile memory cell is controlled from the floating gate 120 by keeping the gate potential (-Vg) lower than the substrate voltage (-Vbb) or the ground voltage (Vss) applied to the substrate. This is achieved by drawing electrons into the source and drain 150 and 160 and bulk (channel) to lower the threshold voltage of the cell. In this case, as illustrated, the source and drain 150 and 160 are floated for uniform erase in which degradation of the gate insulating layer 110 where tunneling is performed is reduced. As in the program operation, the erase efficiency is affected by the strength of the electric field between the floating gate 120 and the substrate.

According to the present invention configured so that the source and drain surfaces adjacent to the channel are inclined, the electric field is concentrated at the corner portion, thereby increasing the strength of the electric field, and thus, the tunneling oxide layer between the floating gate 120 and the source and drain 150 and 160 is formed. The energy band slope becomes large. As a result, in the F-N tunneling for the erase operation of the nonvolatile memory cell, the tunneling current flowing from the conduction band of the floating gate to the conduction band of the source and the drain is increased, thereby improving the erase efficiency.

3 to 6 are cross-sectional views illustrating a manufacturing method of a nonvolatile memory device in accordance with a preferred embodiment of the present invention in order of processing. In the following figures, "CELL-X" in the cell array section is a cross-sectional view taken in a direction parallel to the control gate and "CELL-Y" in a direction perpendicular to the control gate.

3 is a cross-sectional view illustrating a step of forming an isolation layer.

Referring to FIG. 3, a device isolation layer 102 is formed on a surface of a first conductive semiconductor substrate 100, for example, a P-type silicon substrate, for example, by using a local oxidation (LOCOS) process. It is limited.

Although not shown here, in the semiconductor substrate 100 of the first conductivity type before forming the device isolation layer 102, the wells of the second conductivity type such as the N type and the first conductivity type, in which the elements of the peripheral circuit part are to be formed, are formed. A well may be formed, and a well of a first conductivity type in which a memory cell is to be formed may be formed. This well forming process proceeds according to a conventional process procedure.

In addition to the typical local oxidation method, the device isolation layer 102 may use an improved method, for example, a polyspacer LOCOS method, a polysilicon buffered LOCOS method, or a trench device isolation method using a polysilicon spacer. Can be formed.

4 is a cross-sectional view illustrating a step of forming a recess r having an inclined surface by etching a surface of a memory cell in which a source and a drain are to be formed.

Referring to FIG. 4, a mask pattern, for example, a first photoresist pattern 104 is formed on a resultant device isolation layer 102 to expose a portion where a source and a drain are to be formed in the memory cell array. By applying the first photoresist pattern 104 as an etching mask and performing an anisotropic etching process using a silicon substrate as an etching target, the surface of the substrate in the memory cell array in which the source and the drain are to be formed has a predetermined depth, for example, about 20 to 100 nm. By etching deeply, a recess r having an inclined surface is formed.

Here, it is preferable to perform the anisotropic etching so that the inclined surface is formed on the surface of the source and drain regions adjacent to the channel. Tunneling current is affected by the inclination angle of the inclined surface formed by the anisotropic etching. According to an embodiment of the present invention, the inclined surfaces of the recesses formed in the source and the drain may be asymmetrically formed so that the amount of tunneling current through the source and the drain may be adjusted.

On the other hand, in order to prevent the field leakage current or direct tunneling due to the sudden increase of the electric field that may occur at the sharp edge and to consider the change of the slope that may occur during the anisotropic etching, the silicon etchant is used after the anisotropic etching. It is preferable to perform a predetermined amount of isotropic etching, or to oxidize the predetermined amount, and then to etch the oxide by isotropic etching and to grow a subsequent tunnel oxide film. Thereby, rounded edges can be formed by relieving the angle of the non-uniform staircase structure that may be caused by anisotropic etching.

According to a preferred embodiment of the present invention, ion-implanted low concentrations of impurities of a second conductivity type, for example, N-type impurities such as arsenic (As) or phosphorus (P), are formed on the entire surface of the resultant recess. This is to form a high concentration source and drain edge portions, i.e., source and drain portions adjacent to the channel at low concentration, and is diffused by Rapid Thermal Processing (RTP) or subsequent heat treatment processes to form a high concentration source and drain region. Ion implantation so that it has sufficient energy and dose amount to be connected. In this case, in order to increase the over-lap region of the source and drain edge portions and the impurity junction region, ion implantation of the first photoresist pattern 104 used for etching the substrate 100 is performed without a separate mask process as shown. Can be used as a mask. Thereby, the over-lap between the floating gate and the source and drain can be adjusted, and the coupling can be adjusted. In addition, after forming the gate according to the degree of subsequent heat treatment, low concentration ion implantation may be performed again.

5 is a cross-sectional view illustrating a process of forming the gate insulating layer 110 and the floating gate 120.

Referring to FIG. 5, the first photoresist pattern 104 is removed, a gate insulating film 110 obtained by, for example, a thermal oxidation process is formed on the surface of the active region where the recess is formed, and then the entire surface of the resultant is electrically conductive. Polysilicon doped with water such as impurities is deposited to a thickness of about 1000 kPa to 2000 kPa to form a conductive layer. The second photoresist pattern 122 is formed on the conductive layer, and the conductive layer is patterned in one direction by applying the second photoresist pattern 122 as an etching mask to form the floating gate 120 of the nonvolatile memory device. Thereafter, a P-type impurity such as, for example, boron (B) is implanted under the device isolation layer 102 to enhance device isolation.

For example, when the gate insulating film is formed while the substrate surface is uneven or the defect due to etching is formed on the surface, leakage current is generated through the gate insulating film during tunneling, thereby degrading the charge retention property of the nonvolatile memory cell. To prevent this, before the gate insulating layer 110 is formed, the semiconductor substrate surface defects in which the tunneling is to be removed are removed, and after the sacrificial oxide film is formed on the substrate surface with a predetermined thickness so that a high quality gate insulating layer can be formed, it is removed. It is desirable to go through the process. More preferably, before the gate insulating film 110 is formed, a defect curing process is performed in which an annealing process is performed for about 10 to 60 minutes in nitrogen or a small amount of oxygen.

The gate insulating film 110 is formed to a thickness of about 70 Pa to 100 Pa, and in addition to the thermal oxide film obtained by the thermal oxidation process, a film having little charge trapping, for example, an oxynitride film grown in an N ₂ O, NH ₃ , NO atmosphere ( oxynitride). The gate insulating film 110 may also be grown in a conventional resistive furnace or RTP chamber.

As shown in FIG. 5, low concentration sources and drains 150 ′ and 160 ′ are formed on the surface of the cell array substrate by the heat treatment processes.

6 is a cross-sectional view illustrating a step of forming the interlayer insulating film 130 and the control gate 140.

Referring to FIG. 6, after removing the second photoresist pattern 122 (refer to FIG. 5), for example, an oxide film / nitride film / oxide film is sequentially stacked on the entire surface of the resultant surface on which the floating gate 120 is formed, to form an interlayer of an ONO structure. The insulating film 130 is formed. Subsequently, a conductive layer is formed on the interlayer insulating layer 130 and then patterned to form a control gate 140. When the control gate 140 is patterned, the interlayer insulating film and the floating gate in the word line direction are also patterned at the same time. Subsequently, after the control gate 140 is formed, ion implantation, for example, a high concentration of N-type impurities, is implanted to form a source and a drain of the memory cell, thereby forming a high concentration source and drain 150 and 160 in the substrate. In this case, the ion implantation may be performed after forming a spacer with an oxide film or a nitride film.

At this time, the pre-injected low concentration source and drain 150 'and 160' are sufficiently overlapped with the floating gate 120.

In addition to the ONO structure, the interlayer insulating layer 130 may be formed of a single material having a high dielectric constant such as thallium oxide, aluminum oxide, or oxynitride.

For example, the control gate 140 may have a polyside structure in which a polysilicon layer doped with impurities of about 500 GPa to 2000 GPa and a silicide layer of about 500 GPa to 2000 GPa are stacked. At this time, as the polysilicon layer doped with impurities, for example, a polysilicon layer deposited by depositing polysilicon and then depositing a phosphorus (POCl ₃ ) containing phosphorus (PCl) or by directly ion implantation of impurities to become conductive Can be used.

After the interlayer insulating layer 130 is formed, ion implantation is performed to control threshold voltages of the transistors to be formed in the peripheral circuit unit, although not shown, and gate oxide layers of the peripheral circuit unit transistors are formed.

In addition, although not shown, the conductive layer for forming the control gate 170 is used to form the gate conductive layer of the peripheral circuit transistors. For example, after ion implantation to form the source drains 150 and 160, the memory cell array unit is covered and the conductive layer of the peripheral circuit portion is patterned to form gates for the transistors in the peripheral circuit portion. The process of forming the peripheral circuit portion transistor or the subsequent processes for forming the unit cell are similar to those of forming a nonvolatile memory device.

The present invention has been described in detail with reference to specific embodiments, but the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. It is possible.

As described above, in the nonvolatile memory cell according to the preferred embodiment of the present invention, an inclined surface is formed on the surface of the source and drain edge portions overlapping the floating gate. That is, an inclined step is formed on the surface of the source and drain edge portions adjacent to the channel region, and the inclined surface and the floating gate overlap with each other.

Therefore, the electric field between the floating gate and the substrate is increased, thereby improving the injection efficiency of the channel hot electrons into the floating gate, and consequently, the program efficiency of the nonvolatile memory device. As a result, it is possible to lower the voltage applied to the control gate, thereby reducing the boost voltage level and reducing the breakdown voltage that the individual transistors constituting the memory cell must withstand, thereby improving reliability of the nonvolatile memory device. In addition, since the electric field is concentrated at the corner portion, the intensity of the electric field is increased, so that the tunneling current between the floating gate and the source and the drain is increased, so that the erase efficiency is improved.

1 is a cross-sectional view of a nonvolatile memory cell according to a preferred embodiment of the present invention.

2A is a cross-sectional view illustrating the program efficiency improvement of a nonvolatile memory cell according to the present invention, and FIG.

3 to 6 are cross-sectional views illustrating a manufacturing method of a nonvolatile memory device in accordance with a preferred embodiment of the present invention in order of processing.

<Explanation of symbols for the main parts of the drawings>

100: semiconductor substrate, 110: gate insulating film

120: floating gate, 130: interlayer insulating film

140: control gate, 150,150 ', 160,160': source, drain

Claims (12)

In a nonvolatile memory device capable of electrically erasing and storing data, A semiconductor substrate which is divided into an active region and a device isolation region, and has a recessed surface having a predetermined angle on a surface of a region where a source and a drain are to be formed, and a recess having an asymmetric slope with respect to the source and the drain. ; A gate electrode pattern of a memory cell formed on a surface of a semiconductor substrate located between neighboring recesses and having a gate insulating film, a floating gate, an interlayer insulating film, and a control gate stacked thereon; And And a source and a drain formed under the recesses disposed at both sides of the gate electrode pattern, and the source and drain and the part of the floating gate overlap with each other through an inclined surface of the recess. The nonvolatile memory device of claim 1, wherein the source and the drain formed below the inclined surface are formed at a lower concentration than the center of the recess. The nonvolatile memory device of claim 1, wherein the gate insulating layer is formed of an oxide layer or an oxynitride layer. In the method of manufacturing a nonvolatile memory device capable of electrically erasing and storing data, Forming a first mask pattern on one surface of the first conductive semiconductor substrate, which is divided into an active region and an isolation region, to expose a portion where a source and a drain are to be formed; By applying the first mask pattern as an etch mask and etching the substrate to a predetermined depth, a recess having an inclined surface on the surface of the active region in which the source and the drain are to be formed and having an asymmetric inclination with respect to the source and the drain is formed. Forming a second step; A third step of removing the first mask pattern; And And forming a gate electrode pattern including a gate insulating film, a floating gate, an interlayer insulating film, and a control gate on the entire surface of the resultant material. The method of claim 4, wherein the second step comprises anisotropically etching the substrate to a depth of about 20 nm to about 100 nm. The method of claim 5, wherein after the anisotropic etching step, And isotropically etching a predetermined amount of substrate to prevent field leakage current or direct tunneling due to a sudden increase in electric field. The method of claim 4, wherein after the second step, And implanting impurities of a second conductivity type on the surface of the recess substrate at a low concentration by using the first mask pattern as an ion implantation mask. The method of claim 4, wherein before the fourth step, And forming a sacrificial oxide film having a predetermined thickness on the surface of the substrate and removing the semiconductor substrate surface defect to be tunneled and forming a high-quality gate insulating film. Manufacturing method. The method of claim 4, wherein before the fourth step, A method of manufacturing a nonvolatile memory device, characterized by further comprising a defect curing step of performing an annealing process in nitrogen or a small amount of oxygen for about 10 to 60 minutes. The method of claim 4, wherein in the fourth step, the gate insulating layer is formed of an oxynitride grown in N ₂ O, NH ₃ , or NO atmosphere. The nonvolatile memory device of claim 4, wherein the interlayer insulating layer is formed of any one selected from ONO, thallium oxide, aluminum oxide, and oxynitride. Method of preparation. The method of claim 4, wherein after the fourth step: And implanting impurities for forming the source and the drain of the memory cell to form a high concentration source and the drain in the substrate.