TWI220294B - A triple gate oxide process with high-k gate dielectric - Google Patents

A triple gate oxide process with high-k gate dielectric Download PDF

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TWI220294B
TWI220294B TW092120331A TW92120331A TWI220294B TW I220294 B TWI220294 B TW I220294B TW 092120331 A TW092120331 A TW 092120331A TW 92120331 A TW92120331 A TW 92120331A TW I220294 B TWI220294 B TW I220294B
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Chew-Hoe Ang
Wenhe Lin
Jia-Zhen Zheng
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Chartered Semiconductor Mfg
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L29/51—Insulating materials associated therewith
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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Description

1220294
導體元件製造，特 厚度及組成的閘極 五、發明說明（1) (一）、【發明所屬之技術領域】 本發明係有關於一種積體電路中半 別是關於一種需要形成具有多種程度的 氧化層之電路。 (二）、【先前技術】 積體電路的製造通常需要形成具有多 組成的介電層，諸如問極氧化層。多種厚； 包含有操作不同電壓上的半導體元件的例+，例：：古： 壓功率電晶體且使用於程式化EEPR0M元件 = 比使用於DRAM中記體儲存阿的柄雷厭+ 电日曰體 需要 介展u :: 電壓電晶體厚的閘極氧 化層。再者，隨者元件尺寸持續減少，需要排除如 MOSFETs中短通道效應問題的超薄閘極 / :有=電常f高介電常數介電質)的介電曰質/料最所好形以 因此’不僅須使製程能夠形成具有多種厚度的介電 = 供形成具有不同成份的介電質。顯然地，此 類製程亦應有效且產生具有完整性及品f佳的介電層。 ,Hattangady等（美國專利第5, 97〇, 345號）係教 用於，體電路中兩種不同厚度的氧化層之方法，其係 二氧:壓刪電晶體，此方法包含有形成一第 氧化：’ -犧牲層係覆蓋於第一氧化層上且局部地移 :’以谷許將第一氧化層選擇性餘刻掉’然後一第-氧化 牲層上，藉以犧牲層藉由ί 一 第一氧化層區上的犧 猎由第一氧化層所消耗掉，且殘留的 1220294 五、發明說明（2) _ 第一氧化層及第二氧化屉脔 度。 $ &化層覆盍於其上’以形成一層雙厚 有-===(厂美國專利第6’147’ _號）係教導 ?二種不同厚度的閘極氧化層之方法 種形成具 :，卜個希望的最大厚度，想要留下該層的沈” 阻所覆蓋’-氮離子植人係進人到基板的小-光 化層未被覆蓋的部#，離子植入 二：：： =二且Ϊ變第二氧化層的厚度。然後移 層？： 第一氧化層，然後成長-第二較薄 第m有-個㈣部份覆蓋於氮離子植入區。 Song(美國專利第6, 191，〇49β1號）亦教導一種 有夕種厚度的閘極氧化層之方法，其係、 :基板，以修改在植入區上基板的氧化物成子 方法教導使用兩種不同離子種類，氮 度及濃度，藉此方法而獲致隨後不同氧化層成長
Zhong等（美國專利第6,268,25 1Β1號）係教導一種製造 多種厚度閘極氧化層之方法，根據此方法，一第一戶 氧化層係沈積達到一第一厚度，其係為氧化層的厚^。一 層多晶矽層係沈積覆蓋於第一閘極氧化層上且將其$坦 化，罩幕多晶矽層，以定義一必要的第二氧化層厚度‘， 然後蝕刻掉基板表面的多晶矽及在其下的氧化層，然後成 長一第二氧化層於基板的暴露表面上，以達到一第:厚 度，其係為中間厚度，一第二多晶矽層沈積於第二氧化層 上且平坦化之。在此之前，罩幕多晶矽，以定義出第三氧
第7頁 1220294 五、發明說明（3) 化層厚度的區，其係最薄的。然後重覆先前的步驟。 隨著元件尺寸變得愈來愈小，使用選擇性離子植人以 控制閘極氧化層成長（如上述所教導的習用技藝一樣），將 會變得不切實際的。此外，希望儘可能的形成多種厚度 層，其係需要將製造步驟減到最小。本發明達到無須離子 植入的目的，且具有比那些習用技藝較少數量及較簡單製 程步驟。 發明内容 第一目的，係在於提供 介電層簡單且有效之方 第二目的，係在於提供 的介電層簡單且有效之 第三目的，係在於提供 的介電層簡單且有效之 "電常數材料，且中間 常數材料形成於一層氧 第四目的，係在於提供 及組成的M0S/CM0S元件 方法， 及最大 化矽上 簡單且 :二，供一種在半導體基板上形成 且有效之方法，其係包括 二 '曰覆蓋於一半導體基板上；2)移除 一部份，以暴露出其下半導體基板表、 本發明之一 形成多種厚度的 本發明之一 上形成多種組成 本發明之一 上形成多種組成 層係為單層的高 括有一層高介電 本發明之一 閘極氧化層厚度 法。 根據本發明 多種厚度及組成 有·· 1 )形成一第 其下的該層的
一種半導體基板上 法 一種在半導體基板 方法。 一種在半導體基板 其中最薄的 的層係為包 的雙層。 一種形成需要多種 有效之方
第8頁 1220294 五、發明說明（4) :品3)形成一第二、較薄的介電層覆蓋藉以 表面上，· 4)移除第一介電声的一笫一 恭路出的基板 的半導體矣而.^電曰的第一°卩伤，以暴露出其下 第二介電i當：成一第三全面性地介電層覆蓋於 丨H第一介電層的殘留部份、及暴露的半導體某 f上。在本發明的較佳實施例中，第一 ^ 氧化石夕声ς 1· η、 Ό咕一 禾一"電層係為 數居。=$ 一2i，第二全面性地介電層係為一高介電常 m 一^的指出，一層閘極電極材料（如摻雜夕曰 ⑽S元件的閘極介電f。電層且將其圖案化’以形顧0S或 (四）、【實施方式】 方法本ϊ:ΐ:較佳實施例係提供一種形成閘極介電層之 八係匕括有一單獨形成高介電常數材料的最薄Α
Li:成高介電常數材料覆蓋於-層氧化石夕上ίΐ:及 最大厚度的部份。 』τ間及 2參閱第1圖’係顯示一半導體基板1〇之橫 圖’其中在此實施例中係為—Si基板，其上覆蓋、面 介電層12，在此實施例中係為一層氧 一 的厚度係獅侧埃之㈤。 減州叫，氧切 :著，參閱第2圖’係顯示第一氧化層12的殘 展：係由一層抗蝕刻材料14所覆蓋’在此實施例中传A :層光阻，已圖案化光阻（未顯示於圖中）進人 1為 J，以使-部份的第一氧化層移除掉，且暴露出其2 板10的表面16。氧化層的蝕刻可藉由一 、 基 刻或已知習用技藝的其他方法而達成。 虱氟酸）蝕 1220294 五、發明說明（5) 接著，參閱第3圖，係顯示第2圖的费、▲ 層介電質材料1 8 (在此實施例中第二声A 其中一第二 成覆蓋於基板10表面16上’其係藉由〜多除二氧，石”係形 *來。氧化層係形成達到一個厚度在10到：‘而f露 的光阻“(第2圖中)藉由化學光阻 殘留 同習用技藝的方法。 溉已移除掉，如 接著，參閱第4圖，係顯示第3圖的製 層抗钱刻材料（#此實施例亦為一層光阻2〇)已开;^第二 第二氧化層18及第-氧化層12上 阻覆盍於 ^的第-氧化層12移除掉，且暴露 光阻2〇 (第4圖中)第藉Ξ化ΐ i: : f造件其中殘留的 4圖相同）而被已移除掉 去除（所有兀件符號均與第 接著，#閱第6圖’係顯示第5圖的製造其
Dn第三介電層24已形成覆蓋;-板10表面上22，第三介電層係為 及基 以，屬氧化物者為較佳，諸如,、ΖΓ〇2、;η〇係 kO3、或其矽酸鹽或鋁酸鹽’此層可^ = (A^VD)或⑽金屬的熱氧化處❹沈積。此層氧^目 ε〇χ/ )T-k)c ^ t ε〇χ^ ；h.^w :氧化物及同"電常數介電質的電容率，且了係 》；， 最好介於4到15埃之間。從圖式可知，已形成介電層；产 的三個區：“ ’《具有中間介電層厚度；區B，其具有度最 im 第10頁 1220294 五、發明說明（6) =電層厚度；及區C，具有最小介電層厚度。區c僅包含 有同介電常數介電質24，而區A及6具有高介 24分別覆蓋於氧化層18及12上。 电申数’丨罨質 於？ίιί閱第7圖，係為三個區Α、β、及C的圖案化部 伤，母個具有一閘極電極（係以多晶矽為較佳）形成於1上 30，其預期形成MOS或CMOS元件覆蓋於適當介電質厚度的 區上若夕B曰矽使用作為閘極電極材料時，可藉由低壓化 學氣相沈積（LPCVD)而形成一層覆蓋於介電層上，適當的 圖案化及蝕刻將會導致第7圖的最後配置。若閘極電極係 為金屬時，則如TiN、TaN、或Mo的金屬將會藉由物理氣相 沈積而沈積，且在類比方式蝕刻處圖案化。 以上所述係藉由貫施例說明本發明之特點，其目的在 使熟習該技術者能暸解本發明之内容並據以實施，、而非限 定本發明之專利範圍，故，凡其他未脫離本發明所揭示之 精神所完成之等效修飾或修改，仍應包含在形成製造M〇s 及CMOS兀件的本發明方法中，且同時提供一種製造M〇s及 CMOS元件之方法。 圖號簡單說明 10 半導體基板 12 第一介電層 層 第11頁 1220294 五、發明說明（7) 20 光阻 22 表面 24 第三介電層 30 閘極電極 1220294 圖式簡單說明 、________
第13頁 底下藉由具體實施例配合所附的圖 =易瞭解本發明…、技術内容、當更 效。 行點及其所達成之功 圖式說明： 同厚Ϊ 2到第6圖係為橫剖面圖，係說明形成具有=葙 t及:俜成::成電二二^ ^ … 閑極電極形成於其成上，•電層之橫剖面圖，係圖案化且具有 _

Claims (1)

1220294 六、申請專利範圍 形成一具有多種厚度及組成的介 種在一半導體基板上 電層之方法，係包括有·· 提供一半導體基板； 具電層覆蓋於該基板上，其該第-介電層係 一第一層抗蝕刻材料覆蓋於該第一介電 ； 電層的第一區刻材料，以暴露出該第-介 藉由一银刻步驟移除該第一介 露其下的-第-基板表面L 的第—區，且糟以暴 ，移除抗蝕刻材料的殘留第一層； 第二介電層’其係在該第二基板表面區上具有一第 第！材料的-全面性第二層覆蓋於第二介電層及 移除一部份的抗姓刻材料的第 電層的第二區； 从暴路出該第一介 區，且藉以暴 藉由一蝕刻步驟移除該第一介 露其下的一第二基板表面區； ㈢的第 移除抗蝕刻材料第二層的殘留部份；及 厚度 形成一全面性第三層的介電材料，1 覆蓋於第二介電層、第-介電層的殘留in… 表面區上。 p份、及第二基板 2.如申請專利範圍第1項所述之方法，其中該基板係為〜 Ml 第14頁 ^^0294 六、申請專利範圍 - 矽基板。 3·如申請專利範圍第2項所述之方法，其中第一及第二介 電層係為S i 〇2層。 4·如申請專利範圍第3項所述之方法，其中該抗蝕刻材料 為光阻。 5·如申請專利範圍第3項所述之方法，其中該蝕刻為一HF 溼式蝕刻。 6·如申請專利範圍第3項所述之方法，其中該第一厚度係 介於30到60埃之間。
7·如申請專利範圍第3項所述之方法，其中該第二厚度係 介於10到30埃之間。 8·如申請專利範圍第3項所述之方法，其中該第三介電層 係為一層高介電常數介電質材料。 9·如申請專利範圍第8項所述之方法，其中該高介電常數 介電質材料係選自於包含有下列：Hf02、Zr02、Ti02、 1〇1 2 3、及LaO3、及其矽酸鹽及鋁酸鹽所組成的組群之一 〇
1 0·如申請專利範圍第8項所述之方法，其中該第三厚度係 2 為’該高介電常數介電質材料具有在4到15埃間的氧當 量厚度的厚度。 3 11·如申請專利範圍第10項所述之方法，其中該高介電常 數介電質係藉由原子層化學氣相沈積（ALCVD)而沈積。 12·如申請專利範圍第iq項所述之方法，其中該高介電常 數介電質係藉由濺鍍金屬的熱氧化處理而形成。 U20294 六、申請專利範圍 13· —種在一半導體基板上形成具有多種厚户 極介電層MOS或CMOS元件之方法，係包括f .，’成的閉 層 提供一半導體基板，其係、具有多種厚度及組成的—介電 形成一層閘極電極材料於該介電層上； 圖案化及蝕刻該閘極電極材料及介電層之下，以製造 依閘極電極厚度所需的元件。 W出 14,如申請專利範圍第13項所述之方法，其中該基板 一矽基板。 、馬 15·如申請專利範圍第14項所述之方法，其中第一及第二 介電層係為Si〇2層。 一 16·如申請專利範圍第15項所述之方法，其中第一厚度係 介於30到60埃之間。 a、 1 7·如申請專利範圍第1 5項所述之方法，其中第二厚度係 介於10到30埃之間。 、 18·如申請專利範圍第15項所述之方法，其中該第三介電 層係為一層高介電常數介電質材料。
六、申請專利範圍 22如^申^/專係^错^•由@原@子層化學氣相沈積ULCVD)而沈積。 23如二直係猎由錢鑛金屬的熱氧化處理而形成、 極材二a利範圍第1 3項所述之方法，其中該層閘極電 極材枓係為一層多晶矽。 24.如中請專利範圍第23項所述之m中該多晶石夕係 籍由低壓化學氣相沈積（LPCVD)而沈積。 25枭如申:青/專利範圍第23項所述之方法，其中該層閘極電 f材料係為一層選自於包含有TiN、TaN、及M〇所組成的 金屬之一。 26·如申請專利範圍第25項所述之方法、其中該金屬係藉 由物理氣相沈積（PVD)而沈積。
第17頁
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