587365 五、發明說明（l) 【發明所屬之技術領域 本發明係有關於一插& 移量消降雪敗，胜W Η 應用於可變增益放大器之吉、六 除輸出狀恶之直流偏移量 々去，消 的直/爪偏移！消除電路。 【先前技術】 :解調程序的系統中，可變增益放大器⑺587365 V. Description of the invention (l) [Technical field to which the invention belongs] The present invention relates to a plug & displacement reduction snowfall win, W Η applied to the variable gain amplifier of the gain, six divide the output-like DC offset Measure away, offset straight / claw offset! Eliminate the circuit. [Prior art]: Variable gain amplifier in a demodulation system
Gain Amplifiers)可蔣齡入於 口占 » D ^ e 」肘翰入^號放大成所需的電题y 且廣泛地運用在透過電4覽僂#彳> $ + '^仇準， 必π电、、見1寻达仏唬的家庭網路1綠恭 機。使用可變增益放大器時，内部操作放大哭在电話 端時，具有本身偏移量的問題。並且，本:二同輸入 總是在幾mV到十幾mV之間。在無線或有線通 ^量範園 益放大器的最大增益可到十幾dB ;因此，本 可變增 放大之後，將會影響接收信號恢復的能力、變 ^量在 圍特，以及信號雜訊比（Signa卜t〇_ nQise 動態範 第1圖顯示習知應用於可變增益放大器之=。 消除電路。第1圖之電路架構被於揭露美國專利=移量 640J 6 3 0、,B1 ’·如圖所示，直流偏移量消除電路⑼應： 可變增益放大器2 5。可變增益放大器2 5包括：—第一放； 器21、一第二放大器22、複數個開關2〇1〜2〇8以及 =Gain Amplifiers) can be used by Jiang Ling in the account »D ^ e” The elbow han ^ is enlarged to the required title y and is widely used in televiewing # 电 > $ + '^ 仇 准 ， 必 π Electricity, see 1 find the bluffing home network 1 green respect machine. When a variable gain amplifier is used, the internal operation amplifier has a problem of offset when it is crying on the phone. And, this: the same input is always between a few mV and a dozen mV. The maximum gain of the Fan Yuanyi amplifier in wireless or wired communication can reach more than ten dB; therefore, after this variable gain amplification, the ability to recover the received signal will be affected, the variation is in the range, and the signal to noise ratio (Signabu t〇_ nQise dynamic range Figure 1 shows the conventional application of variable gain amplifier =. Elimination circuit. The circuit architecture of Figure 1 was disclosed in the US patent = displacement 640J 6 3 0 ,, B1 '· As shown in the figure, the DC offset cancellation circuit should: Variable gain amplifier 25. Variable gain amplifier 25 includes:-a first amplifier; a device 21, a second amplifier 22, a plurality of switches 2101 ~ 2〇8 and =
電阻器。 夂双1U 直流偏移量消除電路2 6包括：一跨導放大哭 (transconductance amplifier)23 以及至少 _ 内部電六口口 24。開關20卜204用以調整第一放大器21的增益。°例如^:Resistor.夂 Dual 1U DC offset cancellation circuit 26 includes: a transconductance amplifier 23 and at least _ internal electrical six-port 24. The switches 20 and 204 are used to adjust the gain of the first amplifier 21. ° For example ^:
587365 五、發明說明（2) :開=關閉’則增益提高；當開關2〇2關閉，則增益減 Ρ m用以調整第：放大器22。例如：假設開 ： tP^i 2 0 7 ^^ ^ 〇 -輸出^ 二放大器Μ的-輸出電壓按比例轉換成 作铲ί器23的輸出端耦接到内部電容器24，並且將 二二Ζ到弟一放大器21的輸入端，用以消除可變辦兴 放大斋2 5的直流偏移量。跨導放” 曰羞 士协in r ^ 7 V狡大為23與容值大約10PF或 ==内部電容器24搭配’為-G“濾波器。由於内 值很小，可以簡單地製造於IC内部，且不合 佔據輸入/輸出腳位。 不a …ΐ 一 ί大器21和第二放大器22的直流偏移量可利用 （跨導放大器23和電容器24)消除，但跨導放大 為3的直流偏移量並未被消除。故需要一新的消除， 用以消除最後狀態的直流偏移量。 〃电 上述習知方式需要非常大的晶片面積以消除 益所造成的直流偏移量。而本發 ffl 大 低直流偏移量。 Μ明揭路了，利用截波器降 【發明内容】 有鑑於此，本發明目的係為 路的可變增益放大器。 巧杈仏直-偏矛夕！消除電 為達到上述目的’本發明祖 . Θ徒出一種直流偏移量消降雷 路，包括：一跨導放大器、至小一 + —抑 ^ 里均除^ ^ 電谷^、以及一截波電587365 V. Description of the invention (2): ON = OFF ', the gain will increase; when the switch 202 is closed, the gain minus Pm will be used to adjust the first: amplifier 22. For example: Suppose ON: tP ^ i 2 0 7 ^^ ^ 〇-output ^ The output voltage of the second amplifier M is proportionally converted into an output terminal of the shovel 23 and coupled to the internal capacitor 24, and two two Z to The input terminal of the first amplifier 21 is used to eliminate the DC offset of the variable amplifier amplifier 2.5. The transconductance amplifier is said to be a shishi in r ^ 7 V with a value of 23 and a capacitance of about 10 PF or == internal capacitor 24 with a ′ -G ”filter. Because the internal value is small, it can be simply manufactured inside the IC and does not fit in the input / output pins. No a… ΐ The DC offset of amplifier 21 and second amplifier 22 can be eliminated by using transconductance amplifier 23 and capacitor 24, but the DC offset of transconductance amplification to 3 is not eliminated. Therefore, a new cancellation is needed to eliminate the DC offset in the final state. Power saving The above-mentioned conventional method requires a very large chip area to eliminate the DC offset caused by the gain. The ffl of this issue is large and low DC offset. The circuit was unveiled, and it was lowered by the interceptor. [Summary of the Invention] In view of this, the object of the present invention is a variable gain amplifier of a circuit. Clever branch straight-partial spear! To eliminate the electricity in order to achieve the above purpose, the ancestor of the present invention. Θ presents a DC offset reduction lightning circuit, which includes: a transconductance amplifier, a minimum of + +-^ ^ divided by ^ ^ electric valley ^, and a section Wave electricity
587365 五、發明說明（4) =3圖顯示應用於可變增益放大器之截波電路方塊圖 制戴Ϊ ί路3〇和35被互不重疊的時脈信號CK和CKB所控 制。!：fVU’是非期望信號，由截波電路35所調整。 二放UE圖二示非期望信號範圍。期望信號vin來自第 中，婉二一在％脈頻率fc和時脈的諧波（har_lc)頻率 帶和非期望P _ v # ^ 1 n仏號，在原本的頻 非别位移成非期望W 。 非J 1化號^的範圍斑日士 ρ 脈頻率fc大於期望信號的哼脈頻率fc的頻帶重疊。時 值在期望信號的頻寬會大;^減期望信號Vu’的總 括直流偏移量和跨導放大哭 由於非期望信號Vu包 號在期望信號的範圍之外了 、 f雜訊，使得非期望信 第5 A圖顯示應用於本發 應用於本發明之跨導放大：：波電路圖。第5B圖顯示 二截波電路35均是由兩個交 f。弟一截波電路30和第 6 B圖顯示截波器電路之 的開關所組成。第6 A〜 第一截波電路30和第二截波二§CK，on，CKB為off時， 等效非期望信號Vueq在跨導二為第6A圖所示之狀態。 期望信號Vu。當CK為〇f f，ckb a扣^的輸入端是相等於非 第二戴波電路35為第6Β圖所示第一截波電路30和 Vueq等於負的非期望信號。 ^。等效非期望信號 、^ k號平均接近於零， 0702-8720TWF(nl)；9]p49;J〇anne>ptd 587365 五、發明說明（5) 非期望信號Vu超出平均。 第7圖顯示本發明應用於可變增益放大器之直流偏移 量消除電路之第二實施例。第一截波電路3 0被合併在跨導 放大器2 3的輸入端，如跨導放大器5 0 2所示。第二截波電 路3 5耦接於跨導放大器5 〇 2的輸出端和電容器2 4之間。 第8圖顯示本發明應用於可變增益放大器之直流偏移 量消除電路之第三實施例。第二截波電路35被合併在跨導 放大器2 3的輸出端，如跨導放大器5 0 4所示。第一截波電 路3 0麵接於第一放大器2 2和跨導放大器5 〇 4的輸入端之 間。 第9圖顯示本發明應用於可變增益放大器之直流偏移 $消除電路之第四實施例。截波電路3 〇和3 5被合併在妗 放大器2 3中，如跨導放大器5 〇 6所示。 1、 雖然本發明已以較佳實施例揭露如上，然1並 限定本發明，任何熟習此技藝者，在不脫離本發明之 和範圍内，當可作些許之更動與潤飾，因此本發明之= 範圍當視後附之申請專利範圍所界定者為準。 邊587365 V. Description of the invention (4) = 3 The diagram shows the block diagram of the cut-off circuit applied to the variable gain amplifier. Dai Dai 30 and 35 are controlled by non-overlapping clock signals CK and CKB. !: FVU 'is an undesired signal and is adjusted by the clipping circuit 35. Second UE display Figure 2 shows the undesired signal range. The expected signal vin comes from the second, Wan Eryi in the% pulse frequency fc and the harmonic (har_lc) frequency band and the undesired P_v # ^ 1 n 仏, at the original frequency non-specific shift into undesired W . The range of non-J 1 化 ^ 斑 日 士 pulse frequency fc overlaps the frequency band of the hum pulse frequency fc of the desired signal. The time value will be larger in the bandwidth of the desired signal; ^ minus the overall DC offset of the desired signal Vu 'and the transconductance amplification Figure 5A of the Expected Letter shows a transconductance amplifier :: wave circuit diagram applied to the present invention and applied to the present invention. Fig. 5B shows that the two-cut circuit 35 is composed of two intersections f. The first cut-off circuit 30 and FIG. 6B show the composition of the switch of the cut-off circuit. From 6A to 1st interception circuit 30 and second interception §CK, on, and CKB are off, the equivalent undesired signal Vueq is in the state shown in FIG. 6A at transconductance 2. Expected signal Vu. When CK is 0 f, the input of ckb a is equal to the non-desired signal. The second wave-breaking circuit 35 is the first undesired signal 30 and Vueq shown in FIG. 6B. ^. The equivalent undesired signal, ^ k number is close to zero on average, 0702-8720TWF (nl); 9] p49; Joanne > ptd 587365 V. Description of the invention (5) Unexpected signal Vu exceeds the average. Fig. 7 shows a second embodiment of the DC offset cancellation circuit of the present invention applied to a variable gain amplifier. The first chopping circuit 30 is incorporated at the input of the transconductance amplifier 23, as shown in the transconductance amplifier 50.2. The second clipping circuit 35 is coupled between the output terminal of the transconductance amplifier 50 and the capacitor 24. Fig. 8 shows a third embodiment of a DC offset cancellation circuit of the present invention applied to a variable gain amplifier. The second chopping circuit 35 is incorporated at the output of the transconductance amplifier 23, as shown in the transconductance amplifier 504. The first clipping circuit 30 is connected between the first amplifier 22 and the input terminals of the transconductance amplifier 504. FIG. 9 shows a fourth embodiment of the DC offset cancellation circuit of the present invention applied to a variable gain amplifier. The clipping circuits 3 0 and 3 5 are incorporated in the Y amplifier 23 as shown in the transconductance amplifier 5 06. 1. Although the present invention has been disclosed as above with preferred embodiments, but 1 and the present invention is limited, anyone skilled in the art can make some modifications and retouching without departing from the scope of the present invention. = Scope shall be determined by the scope of the attached patent application. side
0702-8720TWF(n 1 );91P49; Joanne .ptd 587365 圖式簡單說明 第1圖顯示習知直流偏移量消除電路。 第2圖顯示本發明應用於可變增益放大器之直流偏移 量消除電路之第一實施例。 第3圖顯示應用於可變增益放大器之截波電路方塊 圖。 第4A〜4E圖顯示非期望信號範圍。 弟5 A圖絲員不應用於本發明之截波電路圖。 第5B圖顯示應用於本發明之跨導放大器電路圖。 第6 A〜6B圖顯示截波器電路之操作圖。 第7圖顯示本發明應用於可變增益放大器之直流偏移 量消除電路之第二實施例。 第8圖顯示本發明應用於可變增益放大器之直流偏移 量消除電路之第三實施例。 第9圖顯示本發明應用於可變增益放大器之直流偏移 量消除電路之第四實施例。 【符號說明】 2 1〜第一放大器； 2 2〜第二放大器； 201-208〜開關； 23〜跨導放大器； 2 4〜内部電容器； 2 6〜直流偏移量消除電路； 2 5〜可變增益放大器；3 0〜第一截波電路； 35〜第二截波電路。0702-8720TWF (n 1); 91P49; Joanne .ptd 587365 Brief description of the diagram Figure 1 shows the conventional DC offset cancellation circuit. Fig. 2 shows a first embodiment of a DC offset cancellation circuit of the present invention applied to a variable gain amplifier. Figure 3 shows a block diagram of a clipping circuit applied to a variable gain amplifier. Figures 4A to 4E show the undesired signal range. Brother 5 A is not applicable to the cut-off circuit diagram of the present invention. FIG. 5B shows a circuit diagram of a transconductance amplifier applied to the present invention. Figures 6A to 6B show operation diagrams of the chopper circuit. Fig. 7 shows a second embodiment of the DC offset cancellation circuit of the present invention applied to a variable gain amplifier. Fig. 8 shows a third embodiment of a DC offset cancellation circuit of the present invention applied to a variable gain amplifier. Fig. 9 shows a fourth embodiment of the DC offset cancellation circuit of the present invention applied to a variable gain amplifier. [Symbol description] 2 1 ~ first amplifier; 2 2 ~ second amplifier; 201-208 ~ switch; 23 ~ transconductance amplifier; 2 4 ~ internal capacitor; 2 6 ~ DC offset cancellation circuit; 2 5 ~ may Variable gain amplifier; 30 ~ first chopping circuit; 35 ~ second chopping circuit.
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