TW583541B - Using type bits to track storage of ECC and predecode bits in a level two cache - Google Patents
Using type bits to track storage of ECC and predecode bits in a level two cache Download PDFInfo
- Publication number
- TW583541B TW583541B TW091110329A TW91110329A TW583541B TW 583541 B TW583541 B TW 583541B TW 091110329 A TW091110329 A TW 091110329A TW 91110329 A TW91110329 A TW 91110329A TW 583541 B TW583541 B TW 583541B
- Authority
- TW
- Taiwan
- Prior art keywords
- instruction
- memory
- cache
- cache memory
- bit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
- G06F9/30152—Determining start or end of instruction; determining instruction length
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/382—Pipelined decoding, e.g. using predecoding
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Advance Control (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/892,328 US6804799B2 (en) | 2001-06-26 | 2001-06-26 | Using type bits to track storage of ECC and predecode bits in a level two cache |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW583541B true TW583541B (en) | 2004-04-11 |
Family
ID=25399796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW091110329A TW583541B (en) | 2001-06-26 | 2002-05-17 | Using type bits to track storage of ECC and predecode bits in a level two cache |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6804799B2 (https=) |
| EP (1) | EP1399824B1 (https=) |
| JP (1) | JP4170216B2 (https=) |
| KR (1) | KR100884351B1 (https=) |
| CN (1) | CN1287292C (https=) |
| DE (1) | DE60223023T2 (https=) |
| TW (1) | TW583541B (https=) |
| WO (1) | WO2003003218A1 (https=) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI470417B (zh) * | 2011-12-22 | 2015-01-21 | Intel Corp | 用於可靠度之內容感知快取 |
| US9317429B2 (en) | 2011-09-30 | 2016-04-19 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy over common memory channels |
| US9342453B2 (en) | 2011-09-30 | 2016-05-17 | Intel Corporation | Memory channel that supports near memory and far memory access |
| US9378142B2 (en) | 2011-09-30 | 2016-06-28 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy having different operating modes |
| US9600416B2 (en) | 2011-09-30 | 2017-03-21 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy |
| US10268547B2 (en) | 2015-10-15 | 2019-04-23 | Industrial Technology Research Institute | Memory protection device and method |
| US12079488B2 (en) | 2021-12-22 | 2024-09-03 | Samsung Electronics Co., Ltd. | Memory system and method of operating the same |
Families Citing this family (62)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6751707B2 (en) * | 2002-05-06 | 2004-06-15 | Sony Computer Entertainment Inc. | Methods and apparatus for controlling a cache memory |
| US7437593B2 (en) * | 2003-07-14 | 2008-10-14 | International Business Machines Corporation | Apparatus, system, and method for managing errors in prefetched data |
| US7555703B2 (en) * | 2004-06-17 | 2009-06-30 | Intel Corporation | Method and apparatus for reducing false error detection in a microprocessor |
| US7386756B2 (en) * | 2004-06-17 | 2008-06-10 | Intel Corporation | Reducing false error detection in a microprocessor by tracking instructions neutral to errors |
| JP4673584B2 (ja) * | 2004-07-29 | 2011-04-20 | 富士通株式会社 | キャッシュメモリ装置、演算処理装置及びキャッシュメモリ装置の制御方法 |
| US7415638B2 (en) * | 2004-11-22 | 2008-08-19 | Qualcomm Incorporated | Pre-decode error handling via branch correction |
| US7421568B2 (en) * | 2005-03-04 | 2008-09-02 | Qualcomm Incorporated | Power saving methods and apparatus to selectively enable cache bits based on known processor state |
| US8020047B2 (en) * | 2006-01-17 | 2011-09-13 | Xyratex Technology Limited | Method and apparatus for managing storage of data |
| US8065555B2 (en) * | 2006-02-28 | 2011-11-22 | Intel Corporation | System and method for error correction in cache units |
| US7337272B2 (en) * | 2006-05-01 | 2008-02-26 | Qualcomm Incorporated | Method and apparatus for caching variable length instructions |
| US7962725B2 (en) | 2006-05-04 | 2011-06-14 | Qualcomm Incorporated | Pre-decoding variable length instructions |
| US7644233B2 (en) * | 2006-10-04 | 2010-01-05 | International Business Machines Corporation | Apparatus and method for supporting simultaneous storage of trace and standard cache lines |
| US7945763B2 (en) * | 2006-12-13 | 2011-05-17 | International Business Machines Corporation | Single shared instruction predecoder for supporting multiple processors |
| US8001361B2 (en) * | 2006-12-13 | 2011-08-16 | International Business Machines Corporation | Structure for a single shared instruction predecoder for supporting multiple processors |
| US20080148020A1 (en) * | 2006-12-13 | 2008-06-19 | Luick David A | Low Cost Persistent Instruction Predecoded Issue and Dispatcher |
| US20080256419A1 (en) * | 2007-04-13 | 2008-10-16 | Microchip Technology Incorporated | Configurable Split Storage of Error Detecting and Correcting Codes |
| US8055975B2 (en) * | 2007-06-05 | 2011-11-08 | Apple Inc. | Combined single error correction/device kill detection code |
| FR2924836B1 (fr) * | 2007-12-11 | 2010-12-24 | Commissariat Energie Atomique | Dispositif de service de fiabilite, systeme et procede electroniques mettant en oeuvre au moins un tel dispositif et produit de programme informatique permettant de mettre en oeuvre un tel procede. |
| US7814300B2 (en) | 2008-04-30 | 2010-10-12 | Freescale Semiconductor, Inc. | Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access |
| US20090276587A1 (en) * | 2008-04-30 | 2009-11-05 | Moyer William C | Selectively performing a single cycle write operation with ecc in a data processing system |
| JP5202130B2 (ja) * | 2008-06-24 | 2013-06-05 | 株式会社東芝 | キャッシュメモリ、コンピュータシステム、及びメモリアクセス方法 |
| US8356239B2 (en) * | 2008-09-05 | 2013-01-15 | Freescale Semiconductor, Inc. | Selective cache way mirroring |
| US8145985B2 (en) | 2008-09-05 | 2012-03-27 | Freescale Semiconductor, Inc. | Error detection schemes for a unified cache in a data processing system |
| US8291305B2 (en) * | 2008-09-05 | 2012-10-16 | Freescale Semiconductor, Inc. | Error detection schemes for a cache in a data processing system |
| US8181005B2 (en) * | 2008-09-05 | 2012-05-15 | Advanced Micro Devices, Inc. | Hybrid branch prediction device with sparse and dense prediction caches |
| US8316186B2 (en) * | 2008-09-20 | 2012-11-20 | Freescale Semiconductor, Inc. | Method and apparatus for managing cache reliability based on an associated error rate |
| US8364896B2 (en) * | 2008-09-20 | 2013-01-29 | Freescale Semiconductor, Inc. | Method and apparatus for configuring a unified cache based on an associated error rate |
| US8117497B1 (en) * | 2008-11-17 | 2012-02-14 | Xilinx, Inc. | Method and apparatus for error upset detection and correction |
| KR101042197B1 (ko) * | 2008-12-30 | 2011-06-20 | (주)인디링스 | 메모리 컨트롤러 및 메모리 관리 방법 |
| US8266498B2 (en) * | 2009-03-31 | 2012-09-11 | Freescale Semiconductor, Inc. | Implementation of multiple error detection schemes for a cache |
| JP4865016B2 (ja) * | 2009-08-27 | 2012-02-01 | 株式会社東芝 | プロセッサ |
| JP5325159B2 (ja) * | 2010-05-12 | 2013-10-23 | インターナショナル・ビジネス・マシーンズ・コーポレーション | ファイルリストを抽出してクライアントにて表示するファイルサーバ、クライアントにて表示する方法及びファイルサーバで実行することが可能なコンピュータプログラム |
| CN102346715B (zh) * | 2010-07-30 | 2014-05-28 | 国际商业机器公司 | 保护内存中应用程序的方法、内存控制器和处理器 |
| CN102012872B (zh) * | 2010-11-24 | 2012-05-02 | 烽火通信科技股份有限公司 | 一种用于嵌入式系统的二级缓存控制方法及装置 |
| JP4862100B1 (ja) * | 2011-03-25 | 2012-01-25 | 好一 北岸 | 中央演算処理装置及びマイクロコンピュータ |
| US8516225B2 (en) | 2011-03-25 | 2013-08-20 | Koichi Kitagishi | Central processing unit and microcontroller |
| KR101178293B1 (ko) | 2011-03-25 | 2012-08-29 | 마사미 후쿠시마 | 중앙 처리 장치 및 마이크로컨트롤러 |
| KR101788737B1 (ko) | 2011-05-12 | 2017-10-24 | 에스케이하이닉스 주식회사 | 반도체 시스템 |
| US8572441B2 (en) * | 2011-08-05 | 2013-10-29 | Oracle International Corporation | Maximizing encodings of version control bits for memory corruption detection |
| US9043559B2 (en) | 2012-10-23 | 2015-05-26 | Oracle International Corporation | Block memory engine with memory corruption detection |
| CN102968355A (zh) * | 2012-11-13 | 2013-03-13 | 浪潮电子信息产业股份有限公司 | 一种基于Intel-Brickland-EX平台的内存纠错方法 |
| US20140244932A1 (en) * | 2013-02-27 | 2014-08-28 | Advanced Micro Devices, Inc. | Method and apparatus for caching and indexing victim pre-decode information |
| US9348598B2 (en) | 2013-04-23 | 2016-05-24 | Arm Limited | Data processing apparatus and method for pre-decoding instructions to be executed by processing circuitry |
| US9021334B2 (en) * | 2013-05-01 | 2015-04-28 | Apple Inc. | Calculation of analog memory cell readout parameters using code words stored over multiple memory dies |
| JP6140093B2 (ja) * | 2014-03-18 | 2017-05-31 | 株式会社東芝 | キャッシュメモリ、誤り訂正回路およびプロセッサシステム |
| US9672298B2 (en) | 2014-05-01 | 2017-06-06 | Oracle International Corporation | Precise excecution of versioned store instructions |
| US9195593B1 (en) | 2014-09-27 | 2015-11-24 | Oracle International Corporation | Hardware assisted object memory migration |
| US10210107B2 (en) * | 2014-10-29 | 2019-02-19 | Hewlett Packard Enterprise Development Lp | Trans-fabric instruction set for a communication fabric |
| US10795681B2 (en) * | 2014-12-23 | 2020-10-06 | Intel Corporation | Instruction length decoding |
| CN105938447B (zh) * | 2015-03-06 | 2018-12-14 | 华为技术有限公司 | 数据备份装置及方法 |
| JP6158265B2 (ja) | 2015-09-16 | 2017-07-05 | 株式会社東芝 | キャッシュメモリシステム |
| CN106445720A (zh) * | 2016-10-11 | 2017-02-22 | 郑州云海信息技术有限公司 | 一种内存错误恢复方法和装置 |
| US10268581B2 (en) * | 2017-04-05 | 2019-04-23 | Arm Limited | Cache hierarchy management |
| US10291258B2 (en) | 2017-05-25 | 2019-05-14 | Advanced Micro Devices, Inc. | Error correcting code for correcting single symbol errors and detecting double bit errors |
| KR102490104B1 (ko) | 2017-10-30 | 2023-01-19 | 삼성전자주식회사 | 데이터 보호를 사용하는 인-밴드 메모리에 액세스하기 위한 장치 및 방법 |
| US20190265976A1 (en) * | 2018-02-23 | 2019-08-29 | Yuly Goryavskiy | Additional Channel for Exchanging Useful Information |
| US11119909B2 (en) | 2018-12-11 | 2021-09-14 | Texas Instmments Incorporated | Method and system for in-line ECC protection |
| EP3683679B1 (en) | 2019-01-15 | 2026-03-18 | ARM Limited | Checksum generation |
| CN110311772A (zh) * | 2019-06-15 | 2019-10-08 | 上海来远电子科技有限公司 | 一种可编程加解密方法及其系统 |
| US11334491B1 (en) * | 2020-11-18 | 2022-05-17 | Centaur Technology, Inc. | Side cache array for greater fetch bandwidth |
| US11749333B2 (en) * | 2020-12-10 | 2023-09-05 | SK Hynix Inc. | Memory system |
| KR102664239B1 (ko) | 2023-10-06 | 2024-05-08 | 위더맥스(주) | Ecc 가변 적용 장치 및 방법 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4747043A (en) | 1984-02-10 | 1988-05-24 | Prime Computer, Inc. | Multiprocessor cache coherence system |
| JPS62151971A (ja) | 1985-12-25 | 1987-07-06 | Nec Corp | マイクロ・プロセツサ装置 |
| US5214769A (en) | 1987-12-24 | 1993-05-25 | Fujitsu Limited | Multiprocessor control system |
| US5265004A (en) | 1991-10-15 | 1993-11-23 | Allen-Bradley Company, Inc. | Sequence controller with combinatorial Boolean logic |
| EP0651321B1 (en) | 1993-10-29 | 2001-11-14 | Advanced Micro Devices, Inc. | Superscalar microprocessors |
| US5689672A (en) | 1993-10-29 | 1997-11-18 | Advanced Micro Devices, Inc. | Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions |
| US5721854A (en) | 1993-11-02 | 1998-02-24 | International Business Machines Corporation | Method and apparatus for dynamic conversion of computer instructions |
| US5604753A (en) * | 1994-01-04 | 1997-02-18 | Intel Corporation | Method and apparatus for performing error correction on data from an external memory |
| US6161208A (en) * | 1994-05-06 | 2000-12-12 | International Business Machines Corporation | Storage subsystem including an error correcting cache and means for performing memory to memory transfers |
| US5752264A (en) | 1995-03-31 | 1998-05-12 | International Business Machines Corporation | Computer architecture incorporating processor clusters and hierarchical cache memories |
| US5828895A (en) | 1995-09-20 | 1998-10-27 | International Business Machines Corporation | Methods and system for predecoding instructions in a superscalar data processing system |
| US5819067A (en) | 1996-02-23 | 1998-10-06 | Advanced Micro Devices, Inc. | Computer system configured to translate a computer program into a second computer program prior to executing the computer program |
| US5748978A (en) | 1996-05-17 | 1998-05-05 | Advanced Micro Devices, Inc. | Byte queue divided into multiple subqueues for optimizing instruction selection logic |
| US6115795A (en) * | 1997-08-06 | 2000-09-05 | International Business Machines Corporation | Method and apparatus for configurable multiple level cache with coherency in a multiprocessor system |
| US5951671A (en) | 1997-12-18 | 1999-09-14 | Advanced Micro Devices, Inc. | Sharing instruction predecode information in a multiprocessor system |
| US6108753A (en) * | 1998-03-31 | 2000-08-22 | International Business Machines Corporation | Cache error retry technique |
| US6092182A (en) | 1998-06-24 | 2000-07-18 | Advanced Micro Devices, Inc. | Using ECC/parity bits to store predecode information |
-
2001
- 2001-06-26 US US09/892,328 patent/US6804799B2/en not_active Expired - Lifetime
-
2002
- 2002-04-02 CN CNB028130103A patent/CN1287292C/zh not_active Expired - Lifetime
- 2002-04-02 DE DE60223023T patent/DE60223023T2/de not_active Expired - Lifetime
- 2002-04-02 KR KR1020037016529A patent/KR100884351B1/ko not_active Expired - Fee Related
- 2002-04-02 EP EP02780938A patent/EP1399824B1/en not_active Expired - Lifetime
- 2002-04-02 WO PCT/US2002/012768 patent/WO2003003218A1/en not_active Ceased
- 2002-04-02 JP JP2003509326A patent/JP4170216B2/ja not_active Expired - Fee Related
- 2002-05-17 TW TW091110329A patent/TW583541B/zh not_active IP Right Cessation
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10241943B2 (en) | 2011-09-30 | 2019-03-26 | Intel Corporation | Memory channel that supports near memory and far memory access |
| US10282323B2 (en) | 2011-09-30 | 2019-05-07 | Intel Corporation | Memory channel that supports near memory and far memory access |
| US9342453B2 (en) | 2011-09-30 | 2016-05-17 | Intel Corporation | Memory channel that supports near memory and far memory access |
| US9378142B2 (en) | 2011-09-30 | 2016-06-28 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy having different operating modes |
| US9600416B2 (en) | 2011-09-30 | 2017-03-21 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy |
| US9619408B2 (en) | 2011-09-30 | 2017-04-11 | Intel Corporation | Memory channel that supports near memory and far memory access |
| US9317429B2 (en) | 2011-09-30 | 2016-04-19 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy over common memory channels |
| US10719443B2 (en) | 2011-09-30 | 2020-07-21 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy |
| US10691626B2 (en) | 2011-09-30 | 2020-06-23 | Intel Corporation | Memory channel that supports near memory and far memory access |
| US10241912B2 (en) | 2011-09-30 | 2019-03-26 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy |
| US10102126B2 (en) | 2011-09-30 | 2018-10-16 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy having different operating modes |
| US10282322B2 (en) | 2011-09-30 | 2019-05-07 | Intel Corporation | Memory channel that supports near memory and far memory access |
| TWI470417B (zh) * | 2011-12-22 | 2015-01-21 | Intel Corp | 用於可靠度之內容感知快取 |
| US10268547B2 (en) | 2015-10-15 | 2019-04-23 | Industrial Technology Research Institute | Memory protection device and method |
| US12079488B2 (en) | 2021-12-22 | 2024-09-03 | Samsung Electronics Co., Ltd. | Memory system and method of operating the same |
| TWI864485B (zh) * | 2021-12-22 | 2024-12-01 | 南韓商三星電子股份有限公司 | 記憶體系統及其操作方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| DE60223023D1 (de) | 2007-11-29 |
| CN1522410A (zh) | 2004-08-18 |
| EP1399824A1 (en) | 2004-03-24 |
| JP2004531837A (ja) | 2004-10-14 |
| US20020199151A1 (en) | 2002-12-26 |
| EP1399824B1 (en) | 2007-10-17 |
| KR20040041550A (ko) | 2004-05-17 |
| JP4170216B2 (ja) | 2008-10-22 |
| US6804799B2 (en) | 2004-10-12 |
| CN1287292C (zh) | 2006-11-29 |
| DE60223023T2 (de) | 2008-07-31 |
| KR100884351B1 (ko) | 2009-02-18 |
| WO2003003218A1 (en) | 2003-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW583541B (en) | Using type bits to track storage of ECC and predecode bits in a level two cache | |
| EP1090345B1 (en) | Using ecc/parity bits to store predecode information | |
| US5249286A (en) | Selectively locking memory locations within a microprocessor's on-chip cache | |
| US6115792A (en) | Way prediction logic for cache array | |
| JP4195006B2 (ja) | ジャンプターゲットのための命令キャッシュウェイ予測 | |
| CN103238133B (zh) | 用于多地址矢量载入的矢量收集缓冲器 | |
| US6266752B1 (en) | Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache | |
| US6427192B1 (en) | Method and apparatus for caching victimized branch predictions | |
| US6157986A (en) | Fast linear tag validation unit for use in microprocessor | |
| US5500950A (en) | Data processor with speculative data transfer and address-free retry | |
| WO1996012231A1 (en) | A translation buffer for detecting and preventing conflicting virtual addresses from being stored therein | |
| US6212621B1 (en) | Method and system using tagged instructions to allow out-of-program-order instruction decoding | |
| TW200908009A (en) | Hierarchical cache tag architecture | |
| US6460132B1 (en) | Massively parallel instruction predecoding | |
| EP0855645A2 (en) | System and method for speculative execution of instructions with data prefetch | |
| TW200931261A (en) | Error detector in a cache memory using configurable way redundancy | |
| EP0459233A2 (en) | Selectively locking memory locations within a microprocessor's on-chip cache | |
| US5951671A (en) | Sharing instruction predecode information in a multiprocessor system | |
| US6640293B1 (en) | Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arrays | |
| TW200422832A (en) | Partial linearly tagged cache memory system | |
| JP2001522082A (ja) | より小さな数の分岐予測および代替ターゲットを用いて近似的により大きな数の分岐予測をすること | |
| US7234027B2 (en) | Instructions for test & set with selectively enabled cache invalidate | |
| JPH08212779A (ja) | メモリアレイ、キャッシュ、およびマイクロプロセッサ | |
| TWI606393B (zh) | 依據快取線決定記憶體所有權以偵測自修正程式碼的處理器與方法 | |
| JP3824657B2 (ja) | 1クロックサイクル内でデータをストアするよう構成されたデータメモリユニット、およびその動作方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK4A | Expiration of patent term of an invention patent |