CN1287292C - 使用类型位跟踪二级高速缓存中储存的错误校正码及预解码位 - Google Patents
使用类型位跟踪二级高速缓存中储存的错误校正码及预解码位 Download PDFInfo
- Publication number
- CN1287292C CN1287292C CNB028130103A CN02813010A CN1287292C CN 1287292 C CN1287292 C CN 1287292C CN B028130103 A CNB028130103 A CN B028130103A CN 02813010 A CN02813010 A CN 02813010A CN 1287292 C CN1287292 C CN 1287292C
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- Prior art keywords
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- instruction
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- information
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- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
- G06F9/30152—Determining start or end of instruction; determining instruction length
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/382—Pipelined decoding, e.g. using predecoding
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Advance Control (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/892,328 US6804799B2 (en) | 2001-06-26 | 2001-06-26 | Using type bits to track storage of ECC and predecode bits in a level two cache |
| US09/892,328 | 2001-06-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1522410A CN1522410A (zh) | 2004-08-18 |
| CN1287292C true CN1287292C (zh) | 2006-11-29 |
Family
ID=25399796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB028130103A Expired - Lifetime CN1287292C (zh) | 2001-06-26 | 2002-04-02 | 使用类型位跟踪二级高速缓存中储存的错误校正码及预解码位 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6804799B2 (https=) |
| EP (1) | EP1399824B1 (https=) |
| JP (1) | JP4170216B2 (https=) |
| KR (1) | KR100884351B1 (https=) |
| CN (1) | CN1287292C (https=) |
| DE (1) | DE60223023T2 (https=) |
| TW (1) | TW583541B (https=) |
| WO (1) | WO2003003218A1 (https=) |
Families Citing this family (69)
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| US7437593B2 (en) * | 2003-07-14 | 2008-10-14 | International Business Machines Corporation | Apparatus, system, and method for managing errors in prefetched data |
| US7555703B2 (en) * | 2004-06-17 | 2009-06-30 | Intel Corporation | Method and apparatus for reducing false error detection in a microprocessor |
| US7386756B2 (en) * | 2004-06-17 | 2008-06-10 | Intel Corporation | Reducing false error detection in a microprocessor by tracking instructions neutral to errors |
| JP4673584B2 (ja) * | 2004-07-29 | 2011-04-20 | 富士通株式会社 | キャッシュメモリ装置、演算処理装置及びキャッシュメモリ装置の制御方法 |
| US7415638B2 (en) * | 2004-11-22 | 2008-08-19 | Qualcomm Incorporated | Pre-decode error handling via branch correction |
| US7421568B2 (en) * | 2005-03-04 | 2008-09-02 | Qualcomm Incorporated | Power saving methods and apparatus to selectively enable cache bits based on known processor state |
| US8020047B2 (en) * | 2006-01-17 | 2011-09-13 | Xyratex Technology Limited | Method and apparatus for managing storage of data |
| US8065555B2 (en) * | 2006-02-28 | 2011-11-22 | Intel Corporation | System and method for error correction in cache units |
| US7337272B2 (en) * | 2006-05-01 | 2008-02-26 | Qualcomm Incorporated | Method and apparatus for caching variable length instructions |
| US7962725B2 (en) | 2006-05-04 | 2011-06-14 | Qualcomm Incorporated | Pre-decoding variable length instructions |
| US7644233B2 (en) * | 2006-10-04 | 2010-01-05 | International Business Machines Corporation | Apparatus and method for supporting simultaneous storage of trace and standard cache lines |
| US7945763B2 (en) * | 2006-12-13 | 2011-05-17 | International Business Machines Corporation | Single shared instruction predecoder for supporting multiple processors |
| US8001361B2 (en) * | 2006-12-13 | 2011-08-16 | International Business Machines Corporation | Structure for a single shared instruction predecoder for supporting multiple processors |
| US20080148020A1 (en) * | 2006-12-13 | 2008-06-19 | Luick David A | Low Cost Persistent Instruction Predecoded Issue and Dispatcher |
| US20080256419A1 (en) * | 2007-04-13 | 2008-10-16 | Microchip Technology Incorporated | Configurable Split Storage of Error Detecting and Correcting Codes |
| US8055975B2 (en) * | 2007-06-05 | 2011-11-08 | Apple Inc. | Combined single error correction/device kill detection code |
| FR2924836B1 (fr) * | 2007-12-11 | 2010-12-24 | Commissariat Energie Atomique | Dispositif de service de fiabilite, systeme et procede electroniques mettant en oeuvre au moins un tel dispositif et produit de programme informatique permettant de mettre en oeuvre un tel procede. |
| US7814300B2 (en) | 2008-04-30 | 2010-10-12 | Freescale Semiconductor, Inc. | Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access |
| US20090276587A1 (en) * | 2008-04-30 | 2009-11-05 | Moyer William C | Selectively performing a single cycle write operation with ecc in a data processing system |
| JP5202130B2 (ja) * | 2008-06-24 | 2013-06-05 | 株式会社東芝 | キャッシュメモリ、コンピュータシステム、及びメモリアクセス方法 |
| US8356239B2 (en) * | 2008-09-05 | 2013-01-15 | Freescale Semiconductor, Inc. | Selective cache way mirroring |
| US8145985B2 (en) | 2008-09-05 | 2012-03-27 | Freescale Semiconductor, Inc. | Error detection schemes for a unified cache in a data processing system |
| US8291305B2 (en) * | 2008-09-05 | 2012-10-16 | Freescale Semiconductor, Inc. | Error detection schemes for a cache in a data processing system |
| US8181005B2 (en) * | 2008-09-05 | 2012-05-15 | Advanced Micro Devices, Inc. | Hybrid branch prediction device with sparse and dense prediction caches |
| US8316186B2 (en) * | 2008-09-20 | 2012-11-20 | Freescale Semiconductor, Inc. | Method and apparatus for managing cache reliability based on an associated error rate |
| US8364896B2 (en) * | 2008-09-20 | 2013-01-29 | Freescale Semiconductor, Inc. | Method and apparatus for configuring a unified cache based on an associated error rate |
| US8117497B1 (en) * | 2008-11-17 | 2012-02-14 | Xilinx, Inc. | Method and apparatus for error upset detection and correction |
| KR101042197B1 (ko) * | 2008-12-30 | 2011-06-20 | (주)인디링스 | 메모리 컨트롤러 및 메모리 관리 방법 |
| US8266498B2 (en) * | 2009-03-31 | 2012-09-11 | Freescale Semiconductor, Inc. | Implementation of multiple error detection schemes for a cache |
| JP4865016B2 (ja) * | 2009-08-27 | 2012-02-01 | 株式会社東芝 | プロセッサ |
| JP5325159B2 (ja) * | 2010-05-12 | 2013-10-23 | インターナショナル・ビジネス・マシーンズ・コーポレーション | ファイルリストを抽出してクライアントにて表示するファイルサーバ、クライアントにて表示する方法及びファイルサーバで実行することが可能なコンピュータプログラム |
| CN102346715B (zh) * | 2010-07-30 | 2014-05-28 | 国际商业机器公司 | 保护内存中应用程序的方法、内存控制器和处理器 |
| CN102012872B (zh) * | 2010-11-24 | 2012-05-02 | 烽火通信科技股份有限公司 | 一种用于嵌入式系统的二级缓存控制方法及装置 |
| JP4862100B1 (ja) * | 2011-03-25 | 2012-01-25 | 好一 北岸 | 中央演算処理装置及びマイクロコンピュータ |
| US8516225B2 (en) | 2011-03-25 | 2013-08-20 | Koichi Kitagishi | Central processing unit and microcontroller |
| KR101178293B1 (ko) | 2011-03-25 | 2012-08-29 | 마사미 후쿠시마 | 중앙 처리 장치 및 마이크로컨트롤러 |
| KR101788737B1 (ko) | 2011-05-12 | 2017-10-24 | 에스케이하이닉스 주식회사 | 반도체 시스템 |
| US8572441B2 (en) * | 2011-08-05 | 2013-10-29 | Oracle International Corporation | Maximizing encodings of version control bits for memory corruption detection |
| EP3382556A1 (en) | 2011-09-30 | 2018-10-03 | INTEL Corporation | Memory channel that supports near memory and far memory access |
| CN107608910B (zh) | 2011-09-30 | 2021-07-02 | 英特尔公司 | 用于实现具有不同操作模式的多级存储器分级结构的设备和方法 |
| CN103946812B (zh) | 2011-09-30 | 2017-06-09 | 英特尔公司 | 用于实现多级别存储器分级体系的设备和方法 |
| EP2761480A4 (en) | 2011-09-30 | 2015-06-24 | Intel Corp | APPARATUS AND METHOD FOR IMPLEMENTING MULTINIVE MEMORY HIERARCHY ON COMMON MEMORY CHANNELS |
| US9112537B2 (en) | 2011-12-22 | 2015-08-18 | Intel Corporation | Content-aware caches for reliability |
| US9043559B2 (en) | 2012-10-23 | 2015-05-26 | Oracle International Corporation | Block memory engine with memory corruption detection |
| CN102968355A (zh) * | 2012-11-13 | 2013-03-13 | 浪潮电子信息产业股份有限公司 | 一种基于Intel-Brickland-EX平台的内存纠错方法 |
| US20140244932A1 (en) * | 2013-02-27 | 2014-08-28 | Advanced Micro Devices, Inc. | Method and apparatus for caching and indexing victim pre-decode information |
| US9348598B2 (en) | 2013-04-23 | 2016-05-24 | Arm Limited | Data processing apparatus and method for pre-decoding instructions to be executed by processing circuitry |
| US9021334B2 (en) * | 2013-05-01 | 2015-04-28 | Apple Inc. | Calculation of analog memory cell readout parameters using code words stored over multiple memory dies |
| JP6140093B2 (ja) * | 2014-03-18 | 2017-05-31 | 株式会社東芝 | キャッシュメモリ、誤り訂正回路およびプロセッサシステム |
| US9672298B2 (en) | 2014-05-01 | 2017-06-06 | Oracle International Corporation | Precise excecution of versioned store instructions |
| US9195593B1 (en) | 2014-09-27 | 2015-11-24 | Oracle International Corporation | Hardware assisted object memory migration |
| US10210107B2 (en) * | 2014-10-29 | 2019-02-19 | Hewlett Packard Enterprise Development Lp | Trans-fabric instruction set for a communication fabric |
| US10795681B2 (en) * | 2014-12-23 | 2020-10-06 | Intel Corporation | Instruction length decoding |
| CN105938447B (zh) * | 2015-03-06 | 2018-12-14 | 华为技术有限公司 | 数据备份装置及方法 |
| JP6158265B2 (ja) | 2015-09-16 | 2017-07-05 | 株式会社東芝 | キャッシュメモリシステム |
| TWI569279B (zh) | 2015-10-15 | 2017-02-01 | 財團法人工業技術研究院 | 記憶體保護裝置與方法 |
| CN106445720A (zh) * | 2016-10-11 | 2017-02-22 | 郑州云海信息技术有限公司 | 一种内存错误恢复方法和装置 |
| US10268581B2 (en) * | 2017-04-05 | 2019-04-23 | Arm Limited | Cache hierarchy management |
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| KR102490104B1 (ko) | 2017-10-30 | 2023-01-19 | 삼성전자주식회사 | 데이터 보호를 사용하는 인-밴드 메모리에 액세스하기 위한 장치 및 방법 |
| US20190265976A1 (en) * | 2018-02-23 | 2019-08-29 | Yuly Goryavskiy | Additional Channel for Exchanging Useful Information |
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| KR102878491B1 (ko) * | 2021-12-22 | 2025-10-30 | 삼성전자주식회사 | 메모리 시스템 및 이의 동작 방법 |
| KR102664239B1 (ko) | 2023-10-06 | 2024-05-08 | 위더맥스(주) | Ecc 가변 적용 장치 및 방법 |
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-
2001
- 2001-06-26 US US09/892,328 patent/US6804799B2/en not_active Expired - Lifetime
-
2002
- 2002-04-02 CN CNB028130103A patent/CN1287292C/zh not_active Expired - Lifetime
- 2002-04-02 DE DE60223023T patent/DE60223023T2/de not_active Expired - Lifetime
- 2002-04-02 KR KR1020037016529A patent/KR100884351B1/ko not_active Expired - Fee Related
- 2002-04-02 EP EP02780938A patent/EP1399824B1/en not_active Expired - Lifetime
- 2002-04-02 WO PCT/US2002/012768 patent/WO2003003218A1/en not_active Ceased
- 2002-04-02 JP JP2003509326A patent/JP4170216B2/ja not_active Expired - Fee Related
- 2002-05-17 TW TW091110329A patent/TW583541B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| DE60223023D1 (de) | 2007-11-29 |
| CN1522410A (zh) | 2004-08-18 |
| EP1399824A1 (en) | 2004-03-24 |
| JP2004531837A (ja) | 2004-10-14 |
| US20020199151A1 (en) | 2002-12-26 |
| EP1399824B1 (en) | 2007-10-17 |
| KR20040041550A (ko) | 2004-05-17 |
| JP4170216B2 (ja) | 2008-10-22 |
| US6804799B2 (en) | 2004-10-12 |
| DE60223023T2 (de) | 2008-07-31 |
| TW583541B (en) | 2004-04-11 |
| KR100884351B1 (ko) | 2009-02-18 |
| WO2003003218A1 (en) | 2003-01-09 |
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Effective date of registration: 20100708 Address after: Grand Cayman, Cayman Islands Patentee after: Globalfoundries Semiconductor Inc. Address before: American California Patentee before: Advanced Micro Devices Inc. |
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Effective date of registration: 20201214 Address after: California, USA Patentee after: Lattice chip (USA) integrated circuit technology Co.,Ltd. Address before: Greater Cayman Islands, British Cayman Islands Patentee before: GLOBALFOUNDRIES Inc. |
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Effective date of registration: 20210318 Address after: No.1, Duhang 1st Road, Hsinchu City, Hsinchu Science Park, Taiwan, China Patentee after: MEDIATEK Inc. Address before: California, USA Patentee before: Lattice chip (USA) integrated circuit technology Co.,Ltd. |
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Granted publication date: 20061129 |
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