582190 玖、發明說明 本發明是有關於一種增層法（build-up process)多層板 (multi layer board，MLB)的製造方法，且特別是有關於〜 種多層板之間的內連接（interconnect)爲實心的增層法多層 板的製造方法。 由於消費者對電子產品的要求除了功能強大外，更要 求要輕、薄、短、小，因此市面上的電子產品的積集度 (integration)越來越高，功能越來越強。爲了使晶片（die)的 封裝結構的體積減小，用以裝設晶片的基板（substrate)的 層數也由單層而變爲多層。尤其在一些密度及積集度較高 之封裝中，比如多晶片模組封裝（multi chip module， MCM)，更需要密度較高之多層板。 在基板爲多層的情況之下，各層之間必須要相互作內 連接，以便達到縮小佈線面積的目的。傳統的內連接的做 法是利用鍍通孔（plating through hole，PTH)，也就是先鑽 一個穿透整個基板的孔，然後再利用化學電鍍以及電鍍的 方式來鍍銅於孔中。以便連各導線層中欲連接在一起的部 分。然而，通孔會破壞多層板內在電壓層的完整性，使電 容損失而增加雜訊，且佔用相當大的面積，因而妨礙佈線° 因此業界開始使用增層法，也就是利用逐次壓合（sequential lamination)的方式來由內向外逐漸增加導線層，並利用目 孔（blind via)，也就是僅在需要連接的兩層導線層之間鑽 孔，然後再鍍銅，並塡入塡充材料或是塡入銅膏（CuPaste) 或是銀膏（Ag paste)，以便電性連接兩層導線層。如此便 4989twfl.doc/008 4 582190 可以大幅降低內連接所需要佔用的面積，維持多層板內在 電壓層的完整性，逝便佈線面積再縮小，而使整個多層板 的面積可以再縮小。 然而，連接各餍線路中的內連接若是僅靠一層薄薄的 鍍銅，由於銅的厚度較薄，因而使得兩層導線層之間的阻 抗（impedence)升高，因而妨礙多層板的電性。此外，由於 一般的增層法多層板係先將背膠銅箔貼在基板上之後才形 成孔洞，而塡充材料對於雷射（laser)鑽孔、機鑽式鑽孔（drill) 以及鈾刻等抵抗性較低，不足以作爲中止層，因此各層的 孔、洞之間必須交錯分離，以免在形成導線層或是孔洞的時 候孔洞穿透下層線路，而連接到不欲連接之處。若是以金 屬粉末以及樹脂混合的銅膏或是銀膏等來連接兩層導線 層’則有價格昂貴的缺點，且不易將銅膏或是銀膏塡滿整 個孔’因此電性亦不甚佳。因此業界對於可以具有較佳電 性的內連接的要求甚殷。 請參照第1A圖至第1C圖，其中繪示的是一種東芝公 司的具有實心的內連線的增層法多層板的製造方法，稱爲 埋入式凸塊內連線技術（buried bump interc〇nnecti〇n technology ’ B2IT)。首先，利用金屬模板以及銀膏在銅箔（Cu foil subStrate)l〇上，欲接觸線路16之處形成實心錐形凸 塊12，此日寸錐形凸塊12的外型與高度、硬度均需要嚴格 的控制。將銅箔10、非織狀的介電材料14，以及內面爲 介電材料18，表面已經具有導線層16的核心基材i9(c〇re substrate)|ln在—起’如第1B圖所示。此時由於錐形凸 4989twfl .doc/008 5 582190 塊12具有相當硬度，因此錐形凸塊12的尖端會穿透介電 材料14,並在接觸到線路16。此時由於錐形凸塊的硬度 的控制，因此錐形凸塊12在穿透絕緣層14之後便會因爲 與導線層16間的接觸而變爲碗形的凸塊12’。之後，如第 1C圖所示，再對銅箔10加工而使其形成導線層。如此重 複相同的步驟便可以得到所需的多層板。 然而，這種方法雖然可以得到實心的凸塊，因而所完 成的多層板會具有較佳的電性，但由於錐形凸塊12的製 造，包括其外型與硬度的控制均相當的困難，且所使用的 金屬模板以及銀膏的價格均相當的昂貴，且設備成本亦較 高。 因此本發明的觀點之一在於提出一種增層法多層板的 製造方法’可以簡化製程及設備，降低製造成本。 本發明的觀點之一在於提出一種增層法多層板的製造 方法，可以讓實心內連線疊合，縮短線路路徑並降低阻抗， 同時亦可縮小佈線面積。 本發明在此提出一種增層法多層板的製造方法。在導 電基材上，利用半蝕刻的方式形成凸塊，然後使凸塊間充 滿介電材料。其中介電材料的形成方法可以是在膠片（pre_ preg)上，相對於凸塊的位置上鑽孔，然後再將膠片與導電 基材疊合在一起。也可以直接應用網板印刷、點膠塗佈或 疋塗佈感光性（photosensitive)聚合物，搭配微影製程來使 凸塊間充滿介電材料。然後對凸塊作半蝕刻(halfetching)， 也就是使ΰ麵厚度随，而使凸塊之顧腿介電材料 4989twfl.doc/008 6 ，。接著’在介電材料中的凸塊 或疋銲錫，並將導電基材連同介電材 ' 其中核心基板中包括了铯椽==與核心基板疊合。 緣層C 及導線層，且導線層與絕 合:導電基材連同介電材料與核心基板疊 介電= 丽辟麵應，_加熱而 nt’使其流動塡滿於導電基材與核心基材之間並固 基材可以電性連接導線層。_，再_ 飽 :=_電基娜成導'贿，便可以得到本發明 =曾層法多層板。其中導電難形成之導電層、凸塊及 =材料碰-龍單元，可_上述步驟以形成多層積 層早兀疊合於核心基材上。 由於本發明中的增層法多層板的製造方法係利用實心 的凸塊來作爲各層之間的內連接，因此所製造出來的多層 板會具有較佳的難。而本發明巾髓接形成凸塊來連接 各導線層，因此內連接中不需要塡充材料，因此本發明中 的凸塊可以垂直的連接疊合在一起，而不需要交錯配置， 因此可以減少佈線所需要的面積並縮短線路長度，降低線 路阻ί/ι。此外’本發明係利用触刻方法來形成凸塊，其製 程簡單而谷易控制，且設備成本較低，因而不但簡化製程， 還可降低製造成本。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 4989twfl.doc/008 7 第1A圖到第1C圖係顯示一種習知的增層法多層板 的製造方法的剖面示意圖； 第2 Α圖到第2Η圖係顯示本發明中的增層法多層板 的製造方法中的剖面示意圖； 第3圖繪示本發明中增層法多層板的製造方法中的導 電基材上的另一種凸塊的剖面圖示意；以及 第4A圖繪示本發明中增層法多層板的製造方法中的 導電基材上的另一種凸塊的剖面圖。 第4B圖繪示對應於第2B圖之另一種製程選擇。 第5圖繪示對應於第2B圖之另一種製程選擇。 第6圖繪示對應於第2D、2E圖之另一種製程選擇。 第7圖繪示本發明一較佳實施例的的一種增層法多層 板結構。 圖式標號說明： 12、33 :錐形凸塊 14、18 :絕緣層 20 :導電基材 22、22’ ：凸塊 42 :孔洞 25 :積層單元 34 :絕緣層 37 :空隙 10 :銅箔 12’、32 :碗形凸塊 16 :導線層 20’ ：導線層 4〇、44 :膠片 24 :介電材料 26 :接著材料 36 :導線層 19、38 :核心基材 實施例 4989twfl .doc/008 8 582190 第2A [jj到第2H圖根據本發明一較佳實施例之多層印 刷電路板的_造程序之剖面圖。 首先，請參照第2A圖，在用以形成導線層的導電基 材20上，以半蝕刻(half etching)的方式，去除部分導電基 材20而形成多個凸塊22。鈾刻的方式可以利用乾式鈾刻 (d1^ etChin§)或是濕式蝕刻(wet etching)兩種蝕刻方式，導 la基材20通吊爲$到6 niil( 10·3 inch)的銅搭。在本發明中 則疋使用k式蝕刻的方式。凸塊的形狀除了可以是圓柱形 (Cylinder)之外，也可以製作成如第3圖中的碗形凸塊 33(bowl bumP域是第4A圖中的錐形凸塊(bit bump)。 接著’在凸塊22之間形成介電材料24(dielectric material)，並暴露出凸塊22頂面。其中介電材料24的形 成方法有幾種。請參照第5圖，其中一種是採用膠片 40(pre-preg)作爲介電材料24，在先在一膠片4〇上，對應 於凸塊22位置之處鑽出孔洞42，然後再將膠片40與具有 凸塊22之導電基材20壓合在一起。孔洞42的形成可以 利用機械來鑽孔（drill)，或是利用雷射燒灼等各種方式來 形成。當然也可以搭配第3圖所示的碗形凸塊32，使得膠 片40與導電基板20壓合時，凸塊更容易導入孔洞42中。 請參照第4B圖，若凸塊係採用第4A圖之錐形凸塊33， 則介電材質24則採用非織狀膠片44，直接將膠片44與具 有錐形凸塊33之導電基材20壓合，使得錐形凸塊33刺 破膠片44而露出。 如第2B圖所示，另一種方法則是利用塗佈（coating)的 9 4989twfl.doc/008 582190 方式’包括利用網板印刷（screetl printer)的方式來將今帝 材料24 —次塡入凸塊22之間，或是利用點膠 的方式，也就是將介電材料24 一處一處的塡入。甚至還 可以使用先感性聚合物（photosensitive polymer)，然後再 利用微影（lithography)的方式去除部分介電材料24，使凸 塊22暴露出來。在利用塗佈的方式來形成介電材料μ時， 通吊爵要進行一 _加熱處理（pre heating)做初步固化，以 便去除一部份的介電材料24中的溶劑(solvam)，使介電材 料24保持在B級的乾度(B_stage)，溫度通常爲攝氏8〇_9〇 度。 接下來請參照第2C圖，利用硏磨的方式將溢出於凸 塊22表面之介電材料24刷除，使其平整並露出凸塊22 表面。然後’請參照第2D圖，對凸塊22進行半蝕刻(half etching)。此時的蝕刻步驟的目的是爲了要使凸塊22的厚 度縮小而形成凸塊22,，使得凸塊22,頂面低於介電材料24 的表面。 接著，請參照第圖，在每一個凸塊22,的頂面形成 一接著材料26。其中接著材料26可以是銲錫或是導電膠。 然後，請參照第2F _，便可以將導電基材2〇連同介電材 料24與核心基材38貼合。核心基材38比如是一片雙面 板，係由中間的絕緣餍34以及位於絕緣層34的兩面的導 線層36所形成。欲形成四層板時，便可以同時將兩片導 電基材2〇分別由上下貼到核心基材38的上下方的導線層 36上。當然貼合時，凸塊22，必須朝向導線層36，以便接 4989twfl .doc/008 10 582190 著材料26可以接觸導線層36。此步驟中亦有另一種製程 選擇，請參照第6圖，雖然上述製程中接著材料26係形 成於凸塊22’之頂面，然而亦可形成於核心基材38的導線 層36表面，對應於凸塊22,的位置。然後再將導電基板20 與核心基材38貼合，此時凸塊22,即透過接著材料26電 性連接導線層36。 接著’如第2G圖所示，進行導電基材20與核心基材 38間的壓合，同時進行一後加熱處理。這個加熱步驟是爲 了要使原本尙未完全固化的介電材料24產生流動而塡滿 導線層36之間的空隙（如第2F圖之37)，並固化至c級的 乾度（C-stage)，也就是完全固化的程度。經過這個步驟之 後’不但介電材料24中的溶劑被大致完全趕走，且介電 材料24會滲入導線層36間的空隙37，而可以增加導電基 材20與核心基材38之間的接合性。 ί女者’ 5R參照第2H圖，便可以繼續應用蝕刻或是其 他方式定義導電基材2〇，以形成導線層2〇,，而形成本發 明中的增層法多層板。其中導線層2〇，、凸塊22，及介電材 料24則構成一積層單元Μ。請參照第7圖，因此，若欲 形成更多層之多層板的話，則可以將上述已形成的多層板 當爲核心基材，並重複執行第2Α圖到第2Η圖中所繪示 的步驟，將多層積層單元25疊合於核心基材38上，便可 以增加本發明中的增層法多層板的層數。 一般而言，製作增層法多層板常需要各式各樣精密的 機台，例如二氧化碳雷射機台、鈮（ne〇dymium):釔鋁柘 4989twfl .doc/008 11 582190 榴石（yttrium aluminum garnet)雷射機台等昂貴的鑽孔機 台’以及污染局且價値印貝的電鑛機台，以便形成盲孔 (blind via)。然而，本發明中則不需要應用這些機台，而 可以使用較便宜的生產機台’例如網印機、蝕刻機台等等 來完成。因此本發明之製程較爲簡化且控制較易，故能降 低製造成本。且由於用以作爲多層板之間的內連接的凸塊 爲實心的凸塊，阻抗較低，因此完成之後的增層法多層板 可以具有較佳的電性。此外，由於本案中未使用鑽孔製程， 因此各層的凸塊均可以垂直的疊合在一起（如第7圖所 示），而不需交錯配置，可以有效的縮小佈線所需面積， 並縮短線路路徑。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 4989twfl.doc/008 12582190 发明 Description of the invention The present invention relates to a method for manufacturing a build-up process multi-layer board (MLB), and in particular to ~ kinds of interconnections between multi-layer boards It is a solid multilayer build-up method. As consumers' demands for electronic products are not only powerful, they also require lightness, thinness, shortness, and smallness. Therefore, the integration of electronic products on the market is getting higher and higher, and the functions are getting stronger. In order to reduce the volume of the package structure of the die, the number of layers of the substrate on which the die is mounted is also changed from a single layer to a multilayer. Especially in some high-density and high-density packages, such as multi-chip module packages (MCM), multi-layer boards with higher density are needed. In the case of a multi-layer substrate, the layers must be interconnected with each other in order to reduce the wiring area. The traditional method of interconnecting is to use plating through hole (PTH), that is, to drill a hole that penetrates the entire substrate, and then use electroless plating and electroplating to plate copper in the hole. In order to connect the parts of each wire layer to be connected together. However, through-holes will destroy the integrity of the internal voltage layer of the multilayer board, increase the capacitance loss and increase noise, and occupy a considerable area, thus hindering the wiring. lamination) to gradually increase the wire layer from the inside to the outside, and use blind vias, that is, to drill holes only between the two wire layers that need to be connected, and then plate copper and pour into the filling material or CuPaste or Ag paste is used to electrically connect the two wire layers. In this way, 4989twfl.doc / 008 4 582190 can greatly reduce the area required for internal connection, maintain the integrity of the internal voltage layer of the multilayer board, reduce the wiring area, and make the entire multilayer board area smaller. However, if the inner connection in each connection is only based on a thin layer of copper plating, the thickness of copper will increase the impedance between the two wire layers, thereby preventing the electrical properties of the multilayer board. . In addition, since the general build-up multi-layer board is formed by attaching a self-adhesive copper foil to the substrate, the holes are formed by the filling material for laser drilling, machine drilling, and uranium engraving. The resistance is not enough to be used as a stop layer. Therefore, the holes and holes of each layer must be staggered and separated to prevent holes from penetrating the lower layer of the wiring when they are formed as a wire layer or a hole, and connected to places where they are not intended to be connected. If metal powder and resin mixed copper paste or silver paste are used to connect two layers of wires, it has the disadvantage of being expensive, and it is not easy to fill the entire hole with copper paste or silver paste, so the electrical properties are not very good. . Therefore, the industry has high requirements for interconnects that can have better electrical properties. Please refer to FIG. 1A to FIG. 1C, which shows a manufacturing method of Toshiba Corporation's build-up multilayer board with solid interconnects, which is called buried bump interc technology. 〇nnectin technology 'B2IT). First, a solid template and a silver paste are used to form a solid tapered bump 12 on a Cu foil subStrate 10, where the circuit 16 is to be contacted. The shape, height, and hardness of the inch-sized tapered bump 12 are uniform. Strict control is needed. The copper substrate 10, the non-woven dielectric material 14, and the core substrate i9 (c0re substrate) | ln with a conductive layer 16 on the surface and a dielectric material 18 on the inside are as shown in FIG. 1B. As shown. At this time, since the tapered protrusion 4989twfl.doc / 008 5 582190 block 12 has considerable hardness, the tip of the tapered protrusion 12 penetrates the dielectric material 14 and contacts the line 16. At this time, due to the hardness control of the tapered bump, after the tapered bump 12 penetrates the insulating layer 14, it will become a bowl-shaped bump 12 'due to the contact with the wire layer 16. Thereafter, as shown in FIG. 1C, the copper foil 10 is processed to form a lead layer. Repeat the same steps in this way to get the desired multilayer board. However, although this method can obtain solid bumps, the completed multilayer board will have better electrical properties. However, since the manufacture of the tapered bumps 12, including its shape and hardness control, is quite difficult, In addition, the price of the used metal template and silver paste is quite expensive, and the equipment cost is also high. Therefore, one of the viewpoints of the present invention is to propose a method for manufacturing a multi-layered board with a build-up method, which can simplify the manufacturing process and equipment and reduce the manufacturing cost. One of the viewpoints of the present invention is to provide a method for manufacturing a multilayer board with a build-up method, which can make solid inner wires overlap, shorten the line path and reduce the impedance, and also reduce the wiring area. The present invention proposes a method for manufacturing a multi-layer board by a build-up method. Bumps are formed on the conductive substrate by semi-etching, and the bumps are filled with a dielectric material. The dielectric material can be formed by drilling holes on the film (pre_preg) relative to the bumps, and then laminating the film with the conductive substrate. It is also possible to directly apply screen-printing, dispensing coating, or trowel-coating photosensitive polymers, and use a lithography process to fill the bumps with a dielectric material. Then, the bumps are half-etched, that is, the thickness of the base surface is changed, and the bumps are made of dielectric material 4989twfl.doc / 008 6. Then ‘bumps or thorium solder in the dielectric material, and the conductive substrate together with the dielectric material’ Wherein the core substrate includes cesium 椽 == superimposed on the core substrate. Edge layer C and wire layer, and the wire layer and insulation: conductive substrate together with the dielectric material and the core substrate are stacked. Dielectric = Lapi face, _ heating and nt 'make its flow full of conductive substrate and core substrate The solid substrate between the materials can be electrically connected to the wire layer. _, Then _ full: = _ Electric kina into a guide 'bribe, you can get the present invention = Zeng multilayer method. Among them, the conductive layer, the bump and the material contact-dragon unit, which are difficult to be formed by electricity, can be laminated on the core substrate by the above steps to form a multilayer laminate. Since the manufacturing method of the multilayer board of the present invention uses solid bumps as the internal connection between the layers, the manufactured multilayer board will have better difficulties. The towel joints of the present invention form bumps to connect the various wire layers. Therefore, no filling material is needed in the internal connection. Therefore, the bumps in the present invention can be vertically connected and superimposed, without staggered configuration, so it can reduce The area required for wiring and shorten the length of the line, reduce the line resistance. In addition, the present invention uses bumping method to form bumps. The process is simple and easy to control, and the equipment cost is low, so it not only simplifies the manufacturing process, but also reduces the manufacturing cost. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below in conjunction with the accompanying drawings to make a detailed description as follows: Brief description of the drawings: 4989twfl.doc / 008 7 FIGS. 1A to 1C are schematic cross-sectional views showing a conventional method for manufacturing a multilayered board; FIGS. 2A to 2H show a method for manufacturing a multilayered board according to the present invention. FIG. 3 is a schematic cross-sectional view of another bump on a conductive substrate in a method for manufacturing a multilayered board according to the present invention; and FIG. 4A is a schematic view of a layered method in the present invention. A cross-sectional view of another bump on a conductive substrate in a method for manufacturing a multilayer board. Figure 4B shows another process option corresponding to Figure 2B. Figure 5 shows another process option corresponding to Figure 2B. Figure 6 shows another process option corresponding to Figures 2D and 2E. FIG. 7 shows a multilayer structure of a build-up method according to a preferred embodiment of the present invention. Description of reference numerals: 12, 33: tapered bumps 14, 18: insulating layer 20: conductive substrate 22, 22 ': bump 42: hole 25: laminated unit 34: insulating layer 37: void 10: copper foil 12 ', 32: bowl-shaped bumps 16: wire layer 20': wire layer 40, 44: film 24: dielectric material 26: bonding material 36: wire layer 19, 38: core substrate example 4989twfl.doc / 008 8 582190 2A [jj to 2H] Sectional views of a manufacturing process of a multilayer printed circuit board according to a preferred embodiment of the present invention. First, referring to FIG. 2A, a part of the conductive substrate 20 is removed by half etching on the conductive substrate 20 for forming a conductive layer to form a plurality of bumps 22. Uranium engraving can be performed using dry uranium engraving (d1 ^ etChin§) or wet etching (wet etching). The substrate 20 can be suspended to $ 6 to 6 niil (10 · 3 inch) copper. . In the present invention, a k-type etching method is used. The shape of the bumps may be cylindrical (Cylinder), or they can be made into bowl bumps 33 (the bowl bumP domain is a bit bump in Figure 4A). 'A dielectric material 24 (dielectric material) is formed between the bumps 22, and the top surface of the bumps 22 is exposed. There are several ways to form the dielectric material 24. Please refer to FIG. 5, one of which is using a film 40 (pre-preg) As the dielectric material 24, a hole 42 is first drilled on a film 40 corresponding to the position of the bump 22, and then the film 40 is laminated with the conductive substrate 20 having the bump 22 Together, the holes 42 can be formed by drilling using machinery, or by laser cauterization. Of course, it can also be matched with the bowl-shaped bumps 32 shown in FIG. 3 to make the film 40 conductive. When the substrate 20 is pressed, the bumps are more easily introduced into the holes 42. Please refer to FIG. 4B. If the bumps use the tapered bumps 33 of FIG. 4A, the dielectric material 24 is a non-woven film 44. Pressing the film 44 with the conductive substrate 20 having the tapered projection 33 so that the tapered projection 33 pierces the film 44 As shown in Figure 2B, another method is to use coating 9 4989twfl.doc / 008 582190 method 'including the use of a screen printing (screetl printer) method to the Emperor material 24-times Into the bumps 22, or by means of dispensing, that is, injecting the dielectric material 24 one by one. It is even possible to use a photosensitive polymer and then use lithography ) Method to remove part of the dielectric material 24, so that the bumps 22 are exposed. When the dielectric material μ is formed using a coating method, Tong Diao Jue will perform a pre-heating treatment for preliminary curing in order to remove A part of the solvent (solvam) in the dielectric material 24 keeps the dielectric material 24 at a B-stage dryness (B_stage), and the temperature is usually 80-90 degrees Celsius. Next, please refer to FIG. 2C, The honing method is used to brush off the dielectric material 24 overflowing the surface of the bump 22 to make it flat and expose the surface of the bump 22. Then, 'refer to FIG. 2D, and perform half etching on the bump 22. The purpose of the etching step at this time is to The thickness of the bumps 22 is reduced to form the bumps 22, so that the top surface of the bumps 22 is lower than the surface of the dielectric material 24. Next, referring to the figure, a bond is formed on the top surface of each bump 22 ,. Material 26. The material 26 can be solder or conductive adhesive. Then, referring to 2F_, the conductive substrate 20 together with the dielectric material 24 and the core substrate 38 can be bonded. The core substrate 38 is, for example, a double-sided board, and is formed of an insulating ridge 34 in the middle and a wiring layer 36 on both sides of the insulating layer 34. When a four-layer board is to be formed, two conductive substrates 20 can be attached to the core layer 38 above and below the conductor layer 36 from above and below, respectively. Of course, when bonding, the bump 22 must face the wire layer 36 so that the material 26 can contact the wire layer 36 in order to connect to 4989twfl.doc / 008 10 582190. There is another process option in this step. Please refer to Figure 6. Although the bonding material 26 is formed on the top surface of the bump 22 'in the above process, it can also be formed on the surface of the lead layer 36 of the core substrate 38, corresponding to At the position of the bump 22 '. Then, the conductive substrate 20 and the core substrate 38 are bonded together. At this time, the bump 22 is electrically connected to the wire layer 36 through the bonding material 26. Next, as shown in FIG. 2G, the conductive base material 20 and the core base material 38 are pressed together, and a post-heating treatment is performed at the same time. This heating step is to make the previously incompletely cured dielectric material 24 flow and fill the space between the wire layers 36 (such as 37 in Figure 2F), and cure to the C-stage dryness (C-stage ), Which is the degree of complete curing. After this step, not only the solvent in the dielectric material 24 is completely driven away, but also the dielectric material 24 will penetrate into the gap 37 between the wire layers 36, and the bonding between the conductive substrate 20 and the core substrate 38 can be increased. Sex. [Ladies' 5R] Referring to FIG. 2H, it is possible to continue to define the conductive substrate 20 by using etching or other methods to form a conductive layer 20, and form a multilayer method in the present invention. The wiring layer 20, the bump 22, and the dielectric material 24 constitute a laminated unit M. Please refer to Figure 7. Therefore, if you want to form more layers of multilayer boards, you can use the above-mentioned multilayer boards as the core substrate and repeat the steps shown in Figures 2A to 2 By stacking the multilayer build-up unit 25 on the core substrate 38, the number of layers of the build-up multilayer board in the present invention can be increased. In general, various types of precision machines are often required to make multilayer boards such as carbon dioxide laser machines, niobium (neodymium): yttrium aluminum rhenium 4989twfl .doc / 008 11 582190 yttrium aluminum (Garnet) expensive drilling machines, such as laser machines, and electric mining machines from the Pollution Authority, which are expensive, in order to form blind vias. However, in the present invention, it is not necessary to use these machines, and it can be done using a cheaper production machine 'such as a screen printer, an etching machine, and the like. Therefore, the manufacturing process of the present invention is simplified and the control is easy, so the manufacturing cost can be reduced. And since the bumps used as the internal connection between the multilayer boards are solid bumps, the impedance is low, so the multilayer method after the completion can have better electrical properties. In addition, because the drilling process is not used in this case, the bumps of each layer can be vertically stacked together (as shown in Figure 7), without staggered configuration, which can effectively reduce the area required for wiring and shorten Line path. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. 4989twfl.doc / 008 12