、發明説明（1 ) 【發明領域】 本發明是關於一種調整水平同步信號與垂直同步信號 之方法及裝置，特別是指一種用來消除顯示器畫面跳動與 不穩情況之水平與垂直同步信號調整方法及裝置。 5 【習知技藝說明】 顯示器必須在一秒内顯示例如3〇幅晝面，以符合人眼 的視覺暫留現象而構成連續影像，各晝面分別包含多條掃 描線，各掃描線則包含多個像素；所以，顯示器接收自影 像處理系統的影像信號係一連串對應各像素之資料。為讓 °顯示器確認各資料應對應的像素位置，影像處理系統會與 影像信號同步送出代表一條掃描線啟始（又稱換行）之水平 同步信號、以及代表一幅晝面啟始（又稱換頁）之垂直同步信 號，為說明起見，以下敘述水平與垂直同步信號係取數位 脈波之上升緣（即由低位準變更成高位準之位址）分別代表 5換行與換頁，故當顯示器接收到水平同步信號脈衝之上升 緣時，即知其後將接收下一條掃描線的資料，而收到垂直 同步信號脈衝之上升緣時，知道其後接收為下一幅晝面的 資料，使影像信號被正確依序顯示。 然而，實際顯示時，受干擾、串音等外在因素影響， 〇致使水平同步信號與垂直同步信號之頻率產生些許浮動， 頻率或增或減。若恰巧兩者上升緣出現時間原本相差無幾 而幾近重疊時，-旦頻率浮動，將導致兩者互為先後而產 生跳動。如第_圖’橫軸表示時間，水平同步信號U與垂 直同步信號12之上升緣⑴、121幾乎重疊於同一時間位 566036 五、發明說明 B7 2 10 15 20 置，頻帛浮動將導致垂直同步信?虎上升緣121才目對水平同 步“唬111之上升緣超前一 T、或延後一 τ。若於第N張 晝面時，水平同步信號η上升緣lu在垂直同步信號^ 上升緣121之後，故被判定為該幅晝面之第一行；至第 張時，水平同步信號u上升緣丨n卻在垂直同步信號12 j升緣121之前，將使延續自第N幅晝面之第一行資;料被 誤判而不顯示，改以第二行資料作為[行而呈現。若第 二2張時，水平同步信號u上升緣lu又浮動至垂直同步 信號12上升緣121之後，會使延續的晝面中，第一行資料 時有時無，而讓影像畫面忽上忽了，呈現不穩、定之抖動而 劣化顯示之影像品質。反之，如第二圖，若垂直同步信號 12之上升緣121’落後水平同步信號u，之上升緣Η〗，大於 可能發生跳動之危險範圍，即使發生頻率浮動，依然不會 產生畫面不穩的情況。 然而，將此種嚴重危及顯像品質之因素交付予機率與 運氣，未免太不負責。故若能確保水平同步信號u，與垂直 同步信號12,之上升緣m，、121，間保持一定時距（即大於 危險範圍），將可有效遏止頻率浮動現象造成兩上升緣 in、121間的先後關係改變，避免此忽前忽後以徹底解決 前述問題。所以，本案主要特徵即在兩上升緣間的時距小 於危險範圍時，自動拉大兩者間距，確保兩者保持一定安 全時距，充分避免頻率浮動導致的晝面不穩與抖動情況。 【發明概要】 因此本發明之一目的，在提供一種調整水平同步信 第5 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公營）Description of the invention (1) [Field of the invention] The present invention relates to a method and a device for adjusting a horizontal synchronization signal and a vertical synchronization signal, in particular, a method for adjusting a horizontal and vertical synchronization signal used to eliminate display screen jitter and instability. And device. 5 [Know-how] The monitor must display, for example, 30 diurnal planes within one second to form a continuous image in accordance with the visual persistence of the human eye. Each diurnal plane contains multiple scanning lines, and each scanning line contains Multiple pixels; therefore, the image signal received by the display from the image processing system is a series of data corresponding to each pixel. In order for the ° display to confirm the corresponding pixel position of each data, the image processing system will send a horizontal synchronization signal representing the start of a scanning line (also known as line feed) in synchronization with the image signal, and a start of the day (also known as page feed). ) For the purpose of explanation, the horizontal and vertical synchronization signals described below take the rising edge of the digital pulse (that is, the address changed from a low level to a high level) to represent 5 line feeds and page feeds, so when the display receives When the rising edge of the horizontal synchronization signal pulse is known, it will know that it will receive the data of the next scan line, and when the rising edge of the vertical synchronization signal pulse is received, it will know that it will be received as the next daytime data, so that the image The signals are displayed correctly and sequentially. However, in the actual display, due to external factors such as interference and crosstalk, the frequency of the horizontal synchronization signal and the vertical synchronization signal may fluctuate slightly, and the frequency may increase or decrease. If it happens that the rise time of the two rising edges is almost the same and overlaps, the -denier frequency fluctuation will cause the two to jump one after the other. For example, the horizontal axis represents time. The rising edges ⑴, 121 of the horizontal synchronization signal U and the vertical synchronization signal 12 almost overlap at the same time. 566036 V. Description of the invention B7 2 10 15 20, frequency fluctuation will cause vertical synchronization It is believed that the rising edge of the tiger 121 is horizontally synchronized. The rising edge of the blunt 111 is one T ahead or one τ behind. If it is at the Nth day, the rising edge lu of the horizontal synchronization signal η is at the rising edge of the vertical synchronization signal ^ After 121, it is judged to be the first line of the daylight surface; at the first frame, the rising edge of the horizontal synchronization signal u is before the rising edge of the vertical synchronization signal 12j, and it will continue from the Nth daylight surface. The first line of funds; it is expected to be misjudged and not displayed. Instead, the second line of data will be used as the [line. If the second two frames, the horizontal synchronization signal u rising edge lu floats again after the vertical synchronization signal 12 rising edge 121. , The first day of data will sometimes disappear in the continuation of the daytime surface, and the image screen will suddenly appear, showing unstable, constant jitter and degrading the displayed image quality. On the contrary, as shown in the second picture, if vertical synchronization Signal 12's rising edge 121 'lags behind the horizontal synchronization signal u, the rising edge Η is greater than the dangerous range where the beating may occur, and even if the frequency fluctuates, the picture will not be unstable. However, it is inevitable to deliver such factors that seriously endanger the quality of the image to chance and luck. Too irresponsible. Therefore, if the rising edge m, 121 of the horizontal synchronization signal u and the vertical synchronization signal 12, can be ensured at a certain time interval (that is, greater than the dangerous range), it will effectively prevent the frequency rising phenomenon from causing two rising edges. The relationship between the in and 121 is changed to avoid this inadvertently to completely solve the aforementioned problem. Therefore, the main feature of this case is to automatically widen the distance between the two when the time interval between the two rising edges is less than the dangerous range. Maintain a certain safe time interval to fully avoid daytime instability and jitter caused by frequency fluctuations. [Summary of the Invention] Therefore, an object of the present invention is to provide an adjustable horizontal synchronization letter No. 5. This paper standard is applicable to the Chinese National Standard (CNS) A4 specifications (210X297 public)
、可 (請先閲讀背面之注意事項再填寫本頁) 566036 A7 _______B7_ 五、發明説明（)_ '~ "~ 3 號與垂直同步信號之方法，以達到自動避免因頻率浮動而 導致的晝面不穩之功效。 本發明之另一目的，在提供一種調整水平同步信號與 垂直同步#號之裝置，以達到確保水平與垂直同步信號之 5 上升/下降緣間恆保持安全時距之功效。 於是，本發明之調整水平同步信號與垂直同步信號之 方法，係供顯示器用，而該水平同步信號與垂直同步信號 分別具有多數個脈衝，該方法包含以下步驟： A) 疋義違垂直同步信號中各脈衝的上升/下降緣之前 10至之後一段時間為一危險範圍；及 B) 若該水平同步信號之脈衝的上升/下降緣位於該危 險範圍内時，則延遲該垂直同步信號，致使該危險範圍位 於該水平同步信號之脈衝的上升/下降緣後。 【圖式之簡單說明】 15 本發明之其他特徵及優點，在以下配合參考圖式之較 佳實施例的詳細說明中，將可清楚的呈現，在圖式中： 第一圖係一種習知的水平同步信號與垂直同步信號之 波形圖’其中’水平同步信號之一上升緣與垂直同步信號 之上升緣同時出現。 20 第二圖係一種習知的水平同步信號與垂直同步信號之 波形圖’其中’水平同步信號之一上升緣落後垂直同步信 號之上升緣。 第三圖係本發明之一較佳實施例之方塊示意圖，此較 佳實施例係結合於顯示器中。 --—第6百_ 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公爱） (請先閲讀背面之注意事項再填寫本頁)Yes (please read the precautions on the back before filling this page) 566036 A7 _______B7_ V. Description of the invention () _ '~ " ~ The method of No. 3 and vertical synchronization signal to automatically avoid daylight caused by frequency fluctuation The effect of face instability. Another object of the present invention is to provide a device for adjusting the horizontal synchronization signal and the vertical synchronization #, so as to achieve the effect of ensuring a constant time interval between the 5 rising / falling edges of the horizontal and vertical synchronization signals. Therefore, the method for adjusting the horizontal synchronization signal and the vertical synchronization signal of the present invention is for a display, and the horizontal synchronization signal and the vertical synchronization signal have a plurality of pulses, respectively. The method includes the following steps: A) Disregarding the vertical synchronization signal The rising / falling edge of each pulse within a period of time is a dangerous range from 10 to after; and B) if the rising / falling edge of the pulse of the horizontal synchronization signal is within the dangerous range, the vertical synchronization signal is delayed, causing the The dangerous range is behind the rising / falling edge of the pulse of the horizontal synchronization signal. [Simplified description of the drawings] 15 Other features and advantages of the present invention will be clearly shown in the following detailed description of the preferred embodiment with reference to the drawings. In the drawings: The first picture is a conventional The waveforms of the horizontal synchronization signal and vertical synchronization signal are shown in “Where” one of the rising edge of the horizontal synchronization signal and the rising edge of the vertical synchronization signal appear at the same time. 20 The second diagram is a conventional waveform diagram of a horizontal synchronization signal and a vertical synchronization signal. Among them, one of the rising edges of the horizontal synchronization signal is behind the rising edge of the vertical synchronization signal. The third figure is a schematic block diagram of a preferred embodiment of the present invention. This preferred embodiment is incorporated in a display. --- Article 600_ This paper size applies to China National Standard (CNS) A4 specification (210X297 public love) (Please read the precautions on the back before filling this page)
566036 A7 -------- - B7 五、發明説明（) 1 "一 - 5丨 (請先閲讀背面之注意事項再填寫本頁) 與影像處理電路5間。調整褒置4包含-危險脈衝形成電 路41、一判定電路42及-延遲迴路43。一般原始水平血 垂直同步信號V〇、Ho係由多數個脈衝所構成，並以上： 緣（或下降緣）觸發影像處理電路5換行或換頁，為說明方 5便，下文中係假定原始水平與垂直同步信號v〇、h〇均以 其上升緣進行觸發動作。 危險脈衝形成電路41分別對應原始垂直同步信號v〇 中各脈衝的上升緣之後一段時間形成一危險脈衝，以定義 一危險範圍，並由此連串的危險脈衝構成一危險脈衝信號 1〇 Vp。危險脈衝形成電路41具有一第一延遲電路411、一第 一延遲電路412及一脈衝產生器413。第一延遲電路411 係接收原始垂直同步信號v〇並將其延遲一段時間以形成 垂直同步信號VSi輸出。第二延遲電路412接收垂直同 步仏號vsi並再次延遲，以形成一第二垂直同步信號Vs2 15並輸入脈衝產生器413。脈衝產生器413同時接收原始垂直 同步信號V〇與第二垂直同步信號Vs2，比對兩信號，並對 應兩上升緣間的延遲時段形成一危險脈衝信號Vp而輸出 至判定電路42。 參照第四圖，本實施例之第一延遲電路41丨係由一或 20閘（〇R gate)60、一電阻61及一電容62所構成。電阻61 — 端電性連接傳輸原始垂直同步信號V〇之線路22，另一端 電性連接或閘60兩相互連接之輸入端601、602 ;電容62 一端電性連接或閘60之兩輸入端601、602，另一端接地。 如第五圖，當原始垂直同步信號V0饋入第一延遲電路411 -----第 8 頁__ 本紙張尺度適用中國國家標準A4規格（21〇><297公釐） 6566036 五、發明説明 10 15 20 電容62之延遲效應（即電容充放電效應），使整體 口 4位移一第一延遲時間，此第一延遲 一週期TYS百-， 4 ^ ”、、不為、3之時脈信號的週期）並可用可變電阻及電 合來:疋，如此，或閘60之輸出端603將輸出較原始垂直 同步信號V〇延遲-段時間之垂直同步信號VS1。 第二延遲電路412與第一延遲電路411相同，亦由一 電阻 64、一充 Λ _ 、卜 Α閘&與一電容66所構成。電阻64 —端電性 連接第延遲電路411或閘60之輸出端603，另一端電性 、或閑65之兩相互連接的輸入端μ 1、652 ;電容66 — =電性連接或閘65之兩輸入端65卜652,另一端接地。故 當垂直同步信號Vsi饋入第二延遲電路412後，經電容Μ 之延遲效應，使其再延遲一第二延遲時間，並由或閘以輸 出鈿653輸出（如第六圖）較垂直同步信號vsl延遲第二延遲 時間之一第二垂直同步信號vS2。 藉由前述第一與第二延遲電路411、412，第二垂直同 步#號Vs2之各上升緣落後原始垂直同步信號v〇之上升緣 一段時間（第一延遲時間加第二延遲時間），並以此時段為一 危險範圍。意即當水平同步信號H〇出現於此段時間内，一 旦頻率浮動，將使晝面不穩定，所以脈衝產生器413將分 別對應兩垂直同步信號V〇、VS2之上升緣間的時段形成一 危險脈衝，以作為其後的判定電路檢測用。 本例之脈衝產生器413包含一互斥或閘 (exClUSive-〇R)67 及一及閘（And gate)68。互斥或閘 67 — 輸入端671電性連接第二延遲電路412之或閘65的輸出端 (請先閲讀背面之注意事項再填寫本頁) #丨 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 566036 A7 ' ----- -B7__ 五、發明説明（7 ) " " ----- 53另輪入端電性連接至傳輸原始垂直同步信號V〇之 線=22 ;及閘68 一輸入端681電性連接互斥或閘67之輪 出端673,另一輸入端682電性連接傳輸原始垂直同步信號 V〇之線路22。配合第七圖，當互斥或閘67接收第二垂直 5 =步信號Vs2與原始垂直同步信號V〇時，僅兩信號之一為 阿位準時輸出高位準，而當兩者皆相同（即皆為高位準或皆 為低位準）則輸出低位準，所以第二垂直同步信號VS2與原 ί直Π步k號v0間位準不同始可被輸出，亦即對應第二 垂直同步信號Vs2與原始垂直同步信號V〇的上升緣（下降 10緣）間的延遲時段部分，可形成—連串的脈衝信號，並輸出 至及閘68與原始垂直同步信號v〇比對，以輸出僅對應兩 同步信號V〇、VS2上升緣間延遲時段之危險脈衝，而刪除 對應下降緣部分之脈衝，最後形成危險脈衝信號％輸出至 判定電路42。當然，如熟於此技者所能輕易理解，此處改 15 選擇下降緣間之延遲時段亦無不可。 由於危險脈衝信號Vp中的各危險脈衝即代表原始垂 直同步信號V〇中各上升緣附近的危險範圍，若水平同步信 號H〇上升緣落於其間，則可能在頻率浮動時發生晝面不 穩，反之則無此疑慮，因此判定電路42即用以判斷水平同 20 步信號H〇之上升緣是否落於此範圍内。 本例之判疋電路42包含一延遲正反器（又稱D型正反 器）69及一或閘70。或閘70之一輸入端7〇1電性連接至延 遲正反器69之正向輸出端q，另一輸入端7〇2電性連接脈 衝產生器413及閘68之輸出端683以接收危險脈衝信號 ______ 本紙張尺度巾關家鮮⑽）A4規格（21GX297公^ -- (請先閲讀背面之注意事项再填寫本頁) •、^τ— 8566036 五、發明説明（ 10 15 20 VP，輸出端7〇3則 D。延遲正反器69 、正反益69之信號輪入端 同步信號H。之線路端咖電性連接至傳輸水平 同步信號H。之上升缘乂收水平同步化就H。。當水平 上升緣饋入時，若延遲正反器69 端D之危險脈衝信號。唬輪入 向輸出端Q會將為产二 脈衝“位準)時’其正 V會將為危險脈衝(即高位準)輸出，作 信號VT饋入延遲迴路43 ^ 發 〒且由於或閘7 〇之回鶴批生,丨 使此觸發信號恆被保值輸出。 貝控制， 砰吕之’當判定電路42接收水平同步信號H j時’便將此時饋入之危險脈衝信號VP輸出，如第八圖， 右此=正好饋人有危險脈衝信號％，則輸出變成高位 觸發U vT ’而且此信號會回饋輸入判定電路 同步信號H。之下-上升緣饋人時，判定電路^仍維 位準輸出’而閃鎖觸發信號％。如此，_旦水平同步信: Ho落於危險範圍内時，判定電路42會持續輸出觸發信號^ 反之，如第九圖，當判定電路42於接收水平同步信號Η 之上升緣時，危險脈衝信號VP之脈衝並未饋入，則判定電 路42仍輸出低位準，而非觸發信號ντ。 延遲迴路43係接收垂直同步信號vsl與觸發信號Vp， 當收到觸發信號…時，則將垂直同步信號Vsi延遲後始^ 入影像處理電路5，致使危險脈衝位於水平同步信號^〇之 上升緣後；反之，若未收到觸發信號％時，則幾乎未延遲 垂直同步#號V s i即輸出至影像處理電路5。 本實施例之延遲電路43包含一開關元件43丨與一第二 (請先閲讀背面之注意事嗔再填寫本頁) 、一吓 . 11頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 566036 五、發明説明（ 10 15 20 延遲電路432。如第四圖，此關開元件431係一電晶體71， 其基極711經一電阻72電性連接至延遲正反器65之正輸 出端Q、其射極713則接地。第三延遲電路432與前述第 一與第二延遲電路41卜412類似，亦包含一電阻73、一或 閘74及一電容75。電阻73 —端電性連接至第一延遲電路 411之或閘60輸出端603、另一端電性連接或閘74之兩相 互連接的輸入端741、742。電容75 一端電性連接或閘74 之兩輸入端741、742、另一端電性連接電晶體71之集極 712 〇 如此，當觸發信號VT未饋入電晶體71時，則電晶體 71不導通，由於第三延遲電路432之電容乃並未接地，第 三延遲電路432之延遲功能不作用，垂直同步信號Vsi未 經延遲（此「未經延遲」係指未經電容75影響造成明顯的 時間延遲，但由於垂直同步信號Vsi通過第三延遲電路 輸出，所以輸出信號與饋入信號會有些許時間差，例如 9ns，但因甚小於延遲時間，而可忽略不計），即由或閘μ 之輸出端743輸出至影像處理電路5。在此實施例中，由於 饋入影像處理電路5之垂直同步信號為經第一延遲電路 4Π輸出的垂直同步信號Vsi，所以危險脈衝可視為相對於 垂直同步#號vs丨上升緣之前及之後的一段時間。 相反地，若脈衝信號VT饋入電晶體71時，電晶體71 被導通，電容75可經電晶體71之集極712與射極713而 接地，使第三延遲電路432發揮延遲功能，如第十圖，垂 直同步信號vsl會延遲一段安全時間（例如9〇ns)，而以第三566036 A7 ---------B7 V. Description of the invention () 1 " 一-5 丨 (Please read the precautions on the back before filling this page) and 5 image processing circuits. The adjustment device 4 includes a dangerous pulse forming circuit 41, a determination circuit 42 and a delay circuit 43. Generally, the original horizontal blood vertical synchronization signals V0 and Ho are composed of a plurality of pulses, and the above: The edge (or falling edge) triggers the image processing circuit 5 to change lines or pages. For the purpose of illustration, the following assumes that the original horizontal and The vertical synchronization signals v 0 and h 0 are triggered by their rising edges. The dangerous pulse forming circuit 41 forms a dangerous pulse corresponding to a rising edge of each pulse in the original vertical synchronization signal v0 to define a dangerous range, and a series of dangerous pulses constitute a dangerous pulse signal 10 Vp. The dangerous pulse forming circuit 41 includes a first delay circuit 411, a first delay circuit 412, and a pulse generator 413. The first delay circuit 411 receives the original vertical synchronization signal v0 and delays it for a period of time to form a vertical synchronization signal VSi output. The second delay circuit 412 receives the vertical synchronization signal vsi and delays it again to form a second vertical synchronization signal Vs2 15 and inputs it to the pulse generator 413. The pulse generator 413 receives the original vertical synchronization signal V0 and the second vertical synchronization signal Vs2 at the same time, compares the two signals, forms a dangerous pulse signal Vp corresponding to the delay period between the two rising edges, and outputs the dangerous pulse signal Vp to the determination circuit 42. Referring to the fourth figure, the first delay circuit 41 in this embodiment is composed of an OR gate 60, a resistor 61, and a capacitor 62. Resistor 61 — one end is electrically connected to the line 22 transmitting the original vertical synchronization signal V0, the other end is electrically connected to the two input ends 601, 602 of the gate 60; the one end of the capacitor 62 is electrically connected to the two input ends 601 of the gate 60 , 602, the other end is grounded. As shown in the fifth figure, when the original vertical synchronization signal V0 is fed into the first delay circuit 411 ----- page 8 __ This paper size applies the Chinese national standard A4 specification (21〇 > < 297 mm) 6566036 5 、 Explanation of the invention 10 15 20 The delay effect of the capacitor 62 (that is, the charge and discharge effect of the capacitor) shifts the overall port 4 by a first delay time. This first delay is a period of TYS hundred-, 4 ^, ", not, 3 of The period of the clock signal) can also be changed with a variable resistor and electric coupling: 疋, so, or the output terminal 603 of the gate 60 will output a vertical synchronization signal VS1 delayed by a period of time from the original vertical synchronization signal V0. Second delay circuit 412 is the same as the first delay circuit 411, and is also composed of a resistor 64, a charger Λ_, a gate A & and a capacitor 66. The resistor 64-terminal is electrically connected to the output terminal 603 of the delay circuit 411 or the gate 60 , The other end is electrically connected to the two input terminals μ 1, 652 which are electrically or freely connected; the capacitor 66 — = the two input terminals 65 and 652 which are electrically connected or connected to the gate 65, and the other end is grounded. Therefore, when the vertical synchronization signal Vsi is fed After entering the second delay circuit 412, it is delayed by the delay effect of the capacitor M A second delay time, and the OR gate output 钿 653 output (as shown in the sixth figure) is delayed from the vertical synchronization signal vsl by one of the second delay time the second vertical synchronization signal vS2. By the aforementioned first and second delay circuits 411, 412, each rising edge of the second vertical synchronization #No. Vs2 is behind the rising edge of the original vertical synchronization signal v0 for a period of time (the first delay time plus the second delay time), and this period is a dangerous range. When the horizontal synchronization signal H0 appears in this period of time, once the frequency fluctuates, the daytime surface will be unstable, so the pulse generator 413 will form a dangerous pulse corresponding to the period between the rising edges of the two vertical synchronization signals V0 and VS2, respectively. The pulse generator 413 in this example includes an exclusive OR gate (exClUSive-〇R) 67 and an exclusive gate (And gate) 68. Exclusive OR gate 67 — input 671 Electrically connected to the output terminal of OR gate 65 of the second delay circuit 412 (please read the precautions on the back before filling this page) # 丨 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 566036 A7 ' ----- -B7__ V. Description of the invention (7) " " ----- 53 The other round-in terminal is electrically connected to the line transmitting the original vertical synchronization signal V〇 = 22; and the gate 68-input terminal 681 is electrically connected to each other The output terminal 673 of the NOR gate 67 and the other input 682 are electrically connected to the line 22 transmitting the original vertical synchronization signal V0. With the seventh figure, when the mutator or gate 67 receives the second vertical 5 = step signal Vs2 and When the original vertical synchronization signal V0, only one of the two signals is output at a high level, and when both are the same (that is, both high level or low level), the low level is output, so the second vertical synchronization signal VS2 can be output only when the level is different from the original Π step k number v0, that is, corresponding to the portion of the delay period between the rising edge (falling 10 edges) of the second vertical synchronization signal Vs2 and the original vertical synchronization signal V0, Formation-a series of pulse signals, which are output to the AND gate 68 to compare with the original vertical synchronization signal v0 to output dangerous pulses corresponding to only the delay period between the rising edges of the two synchronization signals V0 and VS2, and delete the corresponding falling edge portion Pulse, finally forming a dangerous pulse signal% output to Decision circuit 42. Of course, as those skilled in the art can easily understand, it is also necessary to change the delay period between falling edges. Because the dangerous pulses in the dangerous pulse signal Vp represent the dangerous ranges near the rising edges in the original vertical synchronization signal V0, if the rising edge of the horizontal synchronization signal H0 falls between them, daytime instability may occur when the frequency fluctuates. Otherwise, there is no such doubt, so the judging circuit 42 is used to judge whether the rising edge of the level with the 20-step signal H0 falls within this range. The judging circuit 42 of this example includes a delay flip-flop (also called a D-type flip-flop) 69 and an OR gate 70. One of the input terminals 701 of the OR gate 70 is electrically connected to the positive output terminal q of the delay flip-flop 69, and the other input terminal 702 is electrically connected to the pulse generator 413 and the output terminal 683 of the gate 68 to receive danger. Pulse signal ______ This paper scale towel is closed at home. A4 size (21GX297) ^-(Please read the precautions on the back before filling this page) •, ^ τ—8566036 V. Description of the invention (10 15 20 VP, The output terminal 703 is D. The signal of the delay flip-flop 69 and the positive and negative 69 turns into the synchronization signal H. The line terminal is electrically connected to the transmission horizontal synchronization signal H. The rising edge of the signal is synchronized with the horizontal synchronization. H. When the horizontal rising edge is fed in, if the dangerous pulse signal at the terminal D of the flip-flop 69 is delayed. When the wheel Q is turned into the output terminal Q, it will be a "pulse" when the second pulse is generated, and its positive V will be dangerous. The pulse (ie high level) output is used as the signal VT to feed into the delay circuit 43 ^ and the trigger signal is constantly output due to the return of OR gate 〇 〇, so that this trigger signal is constantly maintained value output. Bay control, bang Lu Zhi 'when judged When the circuit 42 receives the horizontal synchronization signal H j ', it outputs the dangerous pulse signal VP fed in at this time, such as the eighth , Right this = Just when feeding a dangerous pulse signal%, the output becomes high-level trigger U vT 'and this signal will feed back the input determination circuit synchronization signal H. Below-When the rising edge is fed, the determination circuit is still level output 'And the trigger signal of the flash lock%. In this way, once the horizontal synchronization signal: Ho falls within the dangerous range, the determination circuit 42 will continue to output the trigger signal ^ Conversely, as shown in the ninth figure, when the determination circuit 42 is receiving the horizontal synchronization signal Η At the rising edge, the pulse of the dangerous pulse signal VP is not fed, the determination circuit 42 still outputs a low level instead of the trigger signal ντ. The delay circuit 43 receives the vertical synchronization signal vsl and the trigger signal Vp. When the trigger signal is received, …, The vertical synchronization signal Vsi is delayed and entered into the image processing circuit 5 so that the dangerous pulse is located after the rising edge of the horizontal synchronization signal ^ 〇; conversely, if the trigger signal% is not received, the vertical synchronization is hardly delayed # 号 V si is output to the image processing circuit 5. The delay circuit 43 of this embodiment includes a switching element 43 and a second (please read the precautions on the back first, and then fill out this page) A fright. 11 pages of this paper are in accordance with Chinese National Standards (CNS) A4 specifications (210X297 mm) 566036 V. Description of the invention (10 15 20 Delay circuit 432. As shown in the fourth figure, this switch element 431 is a transistor 71 Its base 711 is electrically connected to the positive output terminal Q of the delay flip-flop 65 through a resistor 72, and its emitter 713 is grounded. The third delay circuit 432 is similar to the aforementioned first and second delay circuits 41 and 412, It also includes a resistor 73, an OR gate 74, and a capacitor 75. Resistor 73—the terminal is electrically connected to the output terminal 603 of the OR gate 60 of the first delay circuit 411, and the other end is electrically connected to the two interconnected inputs of the gate 74 Ends 741, 742. One end of the capacitor 75 is electrically connected to the two input terminals 741, 742 of the gate 74, and the other end is electrically connected to the collector 712 of the transistor 71. Therefore, when the trigger signal VT is not fed into the transistor 71, the transistor 71 is not turned on. Because the capacitance of the third delay circuit 432 is not grounded, the delay function of the third delay circuit 432 does not work, and the vertical synchronization signal Vsi is not delayed (this "no delay" refers to a significant time delay without the influence of the capacitor 75) However, because the vertical synchronization signal Vsi is output through the third delay circuit, the output signal and the input signal will have a slight time difference, such as 9ns, but it is negligible because it is much shorter than the delay time), that is, the output terminal of OR gate μ 743 is output to the image processing circuit 5. In this embodiment, since the vertical synchronization signal fed into the image processing circuit 5 is the vertical synchronization signal Vsi output through the first delay circuit 4Π, the dangerous pulses can be regarded as relative to before and after the rising edge of the vertical synchronization ## vs 丨a period of time. Conversely, if the pulse signal VT is fed to the transistor 71, the transistor 71 is turned on, and the capacitor 75 can be grounded through the collector 712 and the emitter 713 of the transistor 71, so that the third delay circuit 432 can perform a delay function, such as the tenth Figure, the vertical synchronization signal vsl will be delayed for a safe time (for example 90ns), and the third
本紙張尺度適用中國國家標準（Q^；) A4規格（210X297公董）〇 (請先閲讀背面之注意事項再填寫本頁) 、-ir— 566036This paper size applies the Chinese national standard (Q ^;) A4 specification (210X297). (Please read the precautions on the back before filling this page), -ir— 566036
ίο 15 20 垂直同步：號VS3輸出至影像處理電路5,令危險脈衝位於 水平同步㈣H。上升緣之後，使輸人影像處理電路$之垂 直同步信號VS3與水平同步信號Η。之上升緣間保持一段不 j危險範圍之時間間隔。從而，即使發生頻率浮動，仍可 碟保垂直同步信號Vs3與水平同步信號H。之上升緣相互位 置關係不會改變，亦即不發生忽前忽後的情況，進而避免 晝面不穩之情況發生。 從而，在本實施例中，當顯示器3開始自影像處理系 統2接收信號時，原始垂直同步信號％會先輸人本例之裝 置4與原始水平同步信號H〇比對處理後，始會輸出至影像 處理裝置5’如此可讀保影像處理電路5所接收之水平同步 信號H〇上升緣與垂直同步信號Vsi上升緣間保持一安全距 離，有效避免因頻率浮動所導致之晝面抖動。所以下文中， 將依前述的元件與相互關係，配合第十一圖對本實施例中 信號處理流程作說明。 步驟81，利用危險脈衝形成電路41形成對應垂直同 步信號VS1(即經第一延遲電路411延遲之原始垂直同步信 號V〇)上升緣的危險脈衝信號Vp,亦即定義垂直同步信號 VS1各上升緣的危險範圍。在此，先讓原始垂直同步信號 V〇經第一與第二延遲電路411形成第二垂直同步信號 Yu，此第二垂直同步信號Vs2落後原始同步信號v〇 一段 可能發生頻率浮動會造成危險之時間（即第一延遲時間加 上第二延遲時間）’再利用脈衝產生器413之互斥或閘67 對於第二垂直同步信號VS2與原始同步信號v〇間位準差異ίο 15 20 Vertical synchronization: No. VS3 is output to the image processing circuit 5, so that the dangerous pulse is located at horizontal synchronization ㈣H. After the rising edge, the vertical synchronization signal VS3 and the horizontal synchronization signal 输 of the input image processing circuit $ are made. Maintain a period of time between the rising edge and the dangerous range. Therefore, even if a frequency fluctuation occurs, the vertical synchronization signal Vs3 and the horizontal synchronization signal H can be maintained. The positional relationship of the rising edges will not change, that is, there will be no sudden changes, and the situation of daytime instability will be avoided. Therefore, in this embodiment, when the display 3 starts to receive signals from the image processing system 2, the original vertical synchronization signal% is first input to the device 4 in this example after being compared with the original horizontal synchronization signal H0, and then it is output. It is so readable to the image processing device 5 'to ensure that a rising distance between the rising edge of the horizontal synchronization signal H0 and the rising edge of the vertical synchronization signal Vsi received by the image processing circuit 5 maintains a safe distance, effectively avoiding day-to-day jitter caused by frequency fluctuation. Therefore, in the following, the signal processing flow in this embodiment will be described with reference to the aforementioned components and their relationships in conjunction with the eleventh figure. Step 81: Use the dangerous pulse forming circuit 41 to form a dangerous pulse signal Vp corresponding to the rising edge of the vertical synchronization signal VS1 (that is, the original vertical synchronization signal V0 delayed by the first delay circuit 411), that is, to define each rising edge of the vertical synchronization signal VS1. Of danger. Here, the original vertical synchronization signal V0 is first formed through the first and second delay circuits 411 to form a second vertical synchronization signal Yu. This second vertical synchronization signal Vs2 is behind the original synchronization signal v0, and may cause a frequency fluctuation to cause danger. Time (that is, the first delay time plus the second delay time) 're-use the exclusive OR gate of the pulse generator 413 for the second vertical synchronization signal VS2 and the original synchronization signal v0 level difference
本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐) (請先閲讀背面之注意事項再填寫本頁)This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page)
566036 五、發明説明（n ) 的地方形成脈衝（此脈衝即為上升/下降緣附近的危險範 圍）’最後利用及閘68刪除此脈衝信號中對應下降緣的脈 衝，以形成對應上升緣之危險脈衝信號VP。 其次’在步驟82中，利用判定電路42來監測水平同 5步信號H〇是否位於危險脈衝信號VP之各危險脈衝中，亦 即是否落於危險範圍内，若有時，則輸出觸發信號告知延 遲迴路43。在此例中，判定電路42中的延遲正反器69係 接收危險脈衝信號VP並利用水平同步信號Η〇作為時序， 如此可在水平同步信號Η〇與危險脈衝信號Vp之脈衝同時 10存在的情況下（此情況意味水平同步信號h〇位於垂直同步 信號vsl之危險範圍内），輸出觸發信號Vt(因為正在由輸 入端D輸入為高位準之危險脈衝），並進入步驟83中，來 令延遲迴路43之延遲功能啟動。反之，若經判斷水平同步 信號Η〇之上升緣並未位於為危險範圍（即對應之危險脈衝 15内）時，則結束，而由於延遲迴路43之延遲功能並未被啟 動，所以饋入影像處理電路5之垂直同步信號為垂直同步 信號VSI。 在步驟83中，延遲迴路43接收觸發信號％後，會啟 動其延遲功能，令通過之垂直同步信號vsi延遲一段時間 U 90ns)’成為第二垂直同步信號Vs;再輸出至影像處理電 路5中。在本例中，由於延遲迴路43之開關元件431(即電 晶體71)接受到觸發信號％則會導通，使第三延遲電路432 之電容75接地，進而使垂直同步信號Vsi可延遲一段時 間，以令危險範圍變更為水平同步信號H〇的上升緣後，致 本紙張尺度翻巾(210Χ29^ΪΓ-~ - (請先閲讀背面之注意事項再填寫本頁)566036 V. Invention description (n) where a pulse is formed (this pulse is the dangerous range near the rising / falling edge) 'Finally, the sum gate 68 is used to delete the pulse corresponding to the falling edge in order to form the corresponding rising edge danger. Pulse signal VP. Secondly, in step 82, the determination circuit 42 is used to monitor whether the level of the five-step signal H0 is in each of the dangerous pulses of the dangerous pulse signal VP, that is, whether it falls within the dangerous range. If it is, then a trigger signal is output to inform Delay circuit 43. In this example, the delay flip-flop 69 in the determination circuit 42 receives the dangerous pulse signal VP and uses the horizontal synchronization signal Η〇 as a timing sequence, so that the horizontal synchronization signal Η and the pulse of the dangerous pulse signal Vp exist at the same time 10 In the case (this case means that the horizontal synchronization signal h0 is within the dangerous range of the vertical synchronization signal vsl), the trigger signal Vt is output (because the dangerous pulse is being input from the input terminal D to a high level), and the process proceeds to step 83 to make The delay function of the delay circuit 43 is activated. On the contrary, if it is judged that the rising edge of the horizontal synchronization signal Η is not in a dangerous range (that is, within the corresponding dangerous pulse 15), it ends, and because the delay function of the delay circuit 43 has not been activated, it is fed into the image The vertical synchronization signal of the processing circuit 5 is a vertical synchronization signal VSI. In step 83, after the delay circuit 43 receives the trigger signal%, it will start its delay function, so that the vertical synchronization signal vsi is delayed for a period of time U 90ns) 'to become the second vertical synchronization signal Vs; and then output to the image processing circuit 5 . In this example, since the switching element 431 (ie, the transistor 71) of the delay circuit 43 receives the trigger signal%, it will be turned on, so that the capacitor 75 of the third delay circuit 432 is grounded, and the vertical synchronization signal Vsi can be delayed for a period of time. After changing the dangerous range to the rising edge of the horizontal synchronization signal H0, the paper scale is turned over (210 × 29 ^ ΪΓ- ~-(Please read the precautions on the back before filling this page)
566036 A7 B7 五、發明説明（ 13 【元件標號對照】 2影像處理系統 3顯示器 4調整水平同步信號與垂直 41危險脈衝形成電路 412第二延遲電路 42判定電路 431開關元件 5影像處理電路 60 、 65 、 70 、 74 或閘 62 、 66 、 75 電容 68及閘 71電晶體 H〇水平同步信號 V〇原始垂直同步信號 Vsi、Vs2、Vs3垂直同步信 Vp危險脈衝信號 21、22、23 線路 同步信號之裝置 41 1第一延遲電路 4 1 3脈衝產生器 43延遲迴路 432第三延遲電路 61 、 64 、 72 電阻 67互斥或閘 69延遲正反器 Sv影像信號 號 VT觸發信號 第16頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)566036 A7 B7 V. Description of the invention (13 [Comparison of component numbers] 2 Image processing system 3 Display 4 Adjust horizontal synchronization signal and vertical 41 Dangerous pulse forming circuit 412 Second delay circuit 42 Judging circuit 431 Switching element 5 Image processing circuits 60, 65 , 70, 74 or gate 62, 66, 75 capacitor 68 and gate 71 transistor H horizontal synchronization signal V original vertical synchronization signal Vsi, Vs2, Vs3 vertical synchronization signal Vp dangerous pulse signal 21, 22, 23 line synchronization signal Device 41 1 First delay circuit 4 1 3 Pulse generator 43 Delay circuit 432 Third delay circuit 61, 64, 72 Resistor 67 mutually exclusive or gate 69 Delay flip-flop Sv image signal number VT trigger signal Page 16 Paper size Applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)