TWI430231B - Display device and operation method thereof - Google Patents

Description

Display device and its operation method

The present invention relates to a display device and a method of operating the same, and more particularly to a display device having a reset unit and a method of operating the same.

With the development of high technology, video products, especially digital video or video devices, have become a common product in everyday life. At present, the most noticeable display is a flat panel display developed by optoelectronic technology and semiconductor manufacturing technology, such as a liquid crystal display (LCD). Liquid crystal displays have become the main subject of display research in recent years due to their advantages of low voltage operation, no radiation scattering, light weight, and small size.

Generally speaking, the power supply timing of the liquid crystal display has certain regulations when it is turned on and off. However, in some operating states, the power supply timing will not meet the regulations, so that the operation of the liquid crystal display may cause errors. In the case of a misoperation of the liquid crystal display, the timing controller (TCON) of the liquid crystal display will work abnormally, so that the source driver of the liquid crystal display will take the wrong pixel data, thereby causing the liquid crystal display to display abnormal.

The invention provides a display device and a method for operating the same, which can prevent the source driver from capturing an erroneous pixel data and displaying an abnormality.

The invention provides a display device comprising a display panel, a reset unit, a timing controller and a source driver. The reset unit receives the data enable signal and the pulse signal, and counts according to the clock signal when the data enable signal is enabled, and generates a reset signal when the count reaches a preset value. The timing controller is coupled to the reset unit and outputs at least one internal clock signal and at least one control signal, and the timing controller resets according to the reset signal. The source driver is coupled to the display panel and the timing controller to output a plurality of pixel voltages to the display panel according to the internal clock signal and the control signal.

In an embodiment of the invention, the reset unit includes a detection circuit, a counting circuit, and a logic circuit. The detection circuit receives the data enable signal and outputs a notification signal when the data enable signal is enabled. The counting circuit receives the clock signal to output a counting result after counting according to the clock signal. The logic circuit is coupled to the detecting circuit and the counting circuit to control the counting circuit to perform counting according to the notification signal, and output a reset signal when the counting result is a preset value.

In an embodiment of the invention, the reset unit includes a switching circuit, a counting circuit, and a decision circuit. The switch circuit receives the data enable signal and the pulse signal, and outputs the clock signal when the data enable signal is enabled. The counting circuit is coupled to the switching circuit to receive the clock signal output by the switching circuit, and output the counting result according to the clock signal outputted by the switching circuit. The decision circuit is coupled to the counting circuit and outputs a reset signal when the counting result is a preset value.

In an embodiment of the invention, the reset unit includes a switch circuit and a control circuit. The switch circuit receives the data enable signal and the pulse signal, and outputs the clock signal when the data enable signal is enabled. The control circuit is coupled to the switch circuit to receive the clock signal output by the switch circuit, and is counted according to the clock signal output by the switch circuit, and outputs a reset signal when the count reaches a preset value.

In an embodiment of the invention, the timing controller receives the data enable signal and the pulse signal to generate the internal clock signal and the control signal according to the data enable signal and the pulse signal.

In an embodiment of the invention, the internal clock signal includes a first internal clock signal and a second internal clock signal, and the control signal includes a latch control signal. The timing controller includes a frequency dividing circuit, a first phase delay circuit, a second phase delay circuit, and a third phase delay circuit. The frequency removing circuit receives the data enable signal and the pulse signal, and the frequency dividing circuit generates a reference clock signal after dividing the clock signal, and outputs a reference clock signal according to the data enabling signal. The first phase delay circuit is coupled to the frequency dividing circuit and the reset unit to generate a first internal clock signal according to the reference clock signal and output after phase delay, and reset according to the reset signal. The second phase delay circuit is coupled to the frequency dividing circuit and the reset unit to generate a second internal clock signal according to the reference clock signal, output after phase delay, and reset according to the reset signal. The third phase delay circuit is coupled to the frequency dividing circuit and the reset unit to generate a latching control signal according to the reference clock signal, output after phase delay, and reset according to the reset signal. The delay phases of the first phase delay circuit, the second phase delay circuit, and the third phase delay circuit are different from each other.

In an embodiment of the present invention, the relationship between the delay phases of the first phase delay circuit, the second phase delay circuit, and the third phase delay circuit is as shown in the following Equation 1: the delay phase of the first phase delay circuit <the second phase The delay phase of the delay circuit < the delay phase of the third phase delay circuit (Equation 1).

In one embodiment of the invention, the frequency of the reference clock signal is one quarter of the frequency of the clock signal.

In an embodiment of the invention, the reset unit resets the count when the data enable signal is disabled.

The invention also provides a method for operating a display device, which is suitable for a display device having a timing controller, and the method for operating the display device comprises the following steps. Receive data enable signal and pulse signal. When the data enable signal is enabled, it is counted according to the clock signal. A reset signal is generated to reset the timing controller when the count reaches a preset value.

In an embodiment of the present invention, the operating method of the display device further includes: resetting the count when the data enable signal is disabled.

In an embodiment of the invention, wherein the preset value is 1.

Based on the above, the display device and the method for operating the same according to the embodiments of the present invention, when the data enable signal is enabled, is counted according to the clock signal, and generates a reset signal to reset the timing controller when the count reaches a preset value. . Therefore, the timing controller resets the data before the data is written during each picture, so that the waveforms of the internal clock signal and the latch control signal output by the timing controller are normal, thereby preventing the source driver from taking errors. The pixel data is displayed abnormally.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a system diagram of a display device in accordance with an embodiment of the present invention. Referring to FIG. 1 , in the embodiment, the display device 100 includes a reset unit 110 , a timing controller 120 , a source driver 130 , a gate driver 140 , and a display panel 150 . The reset unit 110 receives the data enable signal DE and the pulse signal CLK. The timing controller 120 receives the data enable signal DE and the pulse signal CLK and is coupled to the reset unit 110. The source driver 130 is coupled to the timing controller 120 and the display panel 150. The gate driver 140 is coupled to the timing controller 120 and the display panel 150.

In the embodiment, the display panel 150 is a dual-gate (Dual Gate) display panel, that is, each pixel column (not shown) of the display panel 150 corresponds to two scan lines (not shown). At this time, the source driver 130 separately captures the odd pixel data and the even pixel data of each pixel column to respectively correspond to two scan lines (not shown), so the timing controller 120 outputs two internal clock signals. (ie, the first internal clock signal iCLK1 and the second internal clock signal iCLK2) and a latch control signal LAT are used as the basis for the source driver 130 to extract pixel data. Moreover, the source driver 130 outputs a plurality of pixel voltages VP according to the captured pixel data. The gate driver 140 controls the timing controller 120 to sequentially output a plurality of scan signals SC to the display panel 150 to sequentially turn on each pixel (not shown) of the display panel 150.

In other embodiments, the display panel 150 may be a single gate display panel, and the first internal clock signal iCLK1 and the second internal clock signal iCLK2 may be integrated into an internal clock signal, and may even be omitted. The latching control signal LAT can vary depending on the design of those of ordinary skill in the art.

In this embodiment, the reset unit 110 counts according to the clock signal CLK when the data enable signal DE is enabled (for example, a high level), and when the count reaches a preset value (for example, 1) A reset signal RS is generated. The timing controller 120 generates a first internal clock signal iCLK1, a second internal clock signal iCLK2, and a latch control signal LAT according to the data enable signal DE and the pulse signal CLK, and is reset according to the reset signal RS. In addition, the reset unit 110 resets the count when the data enable signal DE is disabled (eg, low level).

In other words, the reset unit 110 outputs a reset signal RS once during each picture period (ie, between two adjacent rising edges of the data enable signal DE), and the reset signal RS is outputted to the pixel data (corresponding to The pixel voltage VP) is written before the display panel 150 (ie, the predetermined time after the data enable signal DE is enabled). Therefore, the timing controller 120 resets the data before the data is written during each picture, so that the first internal clock signal iCLK1, the second internal clock signal iCLK2, and the latch control signal LAT output by the timing controller 120 are made. The waveform is normal, thereby preventing the source driver 130 from capturing the wrong pixel data and displaying an abnormality.

2A is a circuit diagram of the timing controller of FIG. 1 according to an embodiment of the invention. 2B is a timing diagram of the data enable signal DE, the clock signal CLK, the first internal clock signal iCLK1, the second internal clock signal iCLK2, and the latch control signal LAT of FIG. Referring to FIG. 1 , FIG. 2A and FIG. 2B , in the embodiment, the timing controller 120 includes a frequency dividing circuit 210 , a first phase delay circuit 220 , a second phase delay circuit 230 , and a third phase delay circuit 240 .

The frequency dividing circuit 210 receives the data enable signal DE and the pulse signal CLK. The frequency dividing circuit 210 divides the clock signal CLK to generate a reference clock signal RCLK, and outputs a reference clock signal RCLK according to the data enable signal DE. In this embodiment, the frequency dividing circuit 210 generates a reference clock signal RCLK by dividing the clock signal CLK by 4 times, that is, the frequency of the reference clock signal RCLK is a quarter of the frequency of the clock signal CLK. And the reference clock signal RCLK is output after the data enable signal DE is enabled and after a preset time (ie, time T1). The preset time is, for example, a period during which the data enable signal DE is enabled until the pixel data is output.

The first phase delay circuit 220 is coupled to the frequency dividing circuit 210 and the reset unit 110 to generate the first internal clock signal iCLK1 according to the reference clock signal RCLK and output after phase delay, and reset according to the reset signal RS. . The second phase delay circuit 230 is coupled to the frequency dividing circuit 210 and the reset unit 110 to generate the second internal clock signal iCLK2 according to the reference clock signal RCLK and output after phase delay, and reset according to the reset signal RS. . The third phase delay circuit 240 is coupled to the frequency dividing circuit 210 and the reset unit 110 to generate the latching control signal LAT according to the reference clock signal RCLK and output after phase delay, and reset according to the reset signal RS. The relationship between the delay phases of the first phase delay circuit 220, the second phase delay circuit 230, and the third phase delay circuit 240 is, for example, as shown in the following formula 1: the delay phase of the first phase delay circuit 220 < the second phase delay circuit The delay phase of 230 < the delay phase of the third phase delay circuit 240 (Formula 1), that is, the delay phases of the first phase delay circuit, the second phase delay circuit, and the third phase delay circuit are different from each other.

In the present embodiment, for example, the delay phase of the first phase delay circuit 220 is 0, the delay phase of the second phase delay circuit 230 is 1 pulse wave (i.e., time T2), and the delay phase of the third phase delay circuit 230 is 3.5. Pulse waves (ie time T3). Moreover, the first phase delay circuit 220, the second phase delay circuit 230, and the third phase delay circuit 240 do not output a preset level before the data enable signal DE is enabled (ie, disabled) (here is low) The level is an example) and the non-preset level is output (here, the high level is taken as an example).

After the data enable signal DE is enabled, the reset unit 110 starts counting. If the count of the reset unit 110 is a positive edge trigger and the preset value is 1, the reset unit 110 outputs a reset signal RS after the data enable signal DE is the first positive edge of the enable clock signal. Therefore, the first phase delay circuit 220, the second phase delay circuit 230, and the third phase delay circuit 240 are reset to output a preset level (ie, a low level). Thereby, since the first phase delay circuit 220, the second phase delay circuit 230, and the third phase delay circuit 240 are reset to output a preset level, the level error can be avoided and the source driver 130 can be erroneously captured. Pixel data.

After the time T1, the frequency dividing circuit 210 outputs the reference clock signal RCLK to the first phase delay circuit 220, the second phase delay circuit 230, and the third phase delay circuit 240, and the first phase delay circuit 220 and the second phase delay The circuit 230 and the third phase delay circuit 240 respectively generate the first internal clock signal iCLK1, the second internal clock signal iCLK2, and the latch control signal LAT, and sequentially output the corresponding phase delays.

In addition, if the first phase delay circuit 220, the second phase delay circuit 230, and the third phase delay circuit 240 are output preset levels (eg, low level) before the data enable signal DE is enabled, the first The phase delay circuit 220, the second phase delay circuit 230, and the third phase delay circuit 240 are still output preset levels after resetting, and thus do not affect the operation of the circuit.

FIG. 3 is a circuit diagram of the reset unit of FIG. 1 according to an embodiment of the invention. Referring to FIG. 3, in the embodiment, the reset unit 110' includes a detection circuit 310, a logic circuit 320, and a counter circuit 330. The detecting circuit 310 receives the data enable signal DE, and outputs the notification signal NT to the logic circuit 320 when the data enable signal DE is enabled. The logic circuit 320 is coupled to the detection circuit 310 and the counting circuit 330 to control the counting circuit 330 to count after receiving the notification signal NT, that is, to control the counting circuit 330 to count according to the notification signal NT. The counting circuit 330 receives the clock signal CLK, and after being controlled by the logic circuit 320, counts according to the clock signal CLK and outputs the counting result CR. The logic circuit 320 outputs the reset signal RS when the count result CR is a preset value (for example, 1). The detection circuit 310 can be implemented by using a flip-flop, such as a D-type flip-flop.

4 is a circuit diagram of the reset unit of FIG. 1 according to another embodiment of the present invention. Referring to FIG. 4, in the embodiment, the reset unit 110" includes a switch circuit 410, a counting circuit 420, and a decision circuit 430. The switch circuit 410 receives the data enable signal DE and the pulse signal CLK, and the data enable signal DE The received clock signal CLK (immediate pulse signal CLK') is output when enabled. The counting circuit 420 is coupled to the switch circuit 410 to receive the clock signal CLK' output by the switch circuit 410, and according to the output of the switch circuit 410. The pulse signal CLK' is counted to output a count result CR. The decision circuit 430 is coupled to the counter circuit 420, and outputs a reset signal RS when the count result CR is a preset value (for example, 1). The switch circuit 410 can utilize the transistor. To achieve, for example, an NMOS transistor.

FIG. 5 is a circuit diagram of the reset unit of FIG. 1 according to still another embodiment of the present invention. Referring to FIG. 5, in the present embodiment, the reset unit 110''' includes a switch circuit 510 and a control circuit 520. The switch circuit 510 receives the data enable signal DE and the pulse signal CLK, and outputs the received clock signal CLK (immediate pulse signal CLK') when the data enable signal DE is enabled. The control circuit 520 is coupled to the switch circuit 510 to receive the clock signal CLK' output by the switch circuit 510, and is counted according to the clock signal CLK' output by the switch circuit 510, and when the count reaches a preset value (for example, 1) The reset signal RS is output. Wherein, the switch circuit 510 can be implemented by using a transistor, such as an NMOS transistor.

According to the above, an operation method can be integrated to be applied to the above display device. 6 is a flow chart of a method of operating a display device in accordance with an embodiment of the present invention. Referring to FIG. 6, in this embodiment, the data enable signal and the pulse signal are received first (step S610). When the data enable signal is enabled, it is counted according to the clock signal (step S620), and a reset signal is generated to reset the timing controller when the count reaches the preset value (step S630). And, the count is reset when the data enable signal is disabled (step S640). The steps S620, S630, and S640 are repeatedly performed, so that the timing controller is reset once during each picture, and the details of the above steps may be referred to the foregoing embodiment, and details are not described herein again.

In summary, the display device and the method for operating the same according to the embodiments of the present invention, when the data enable signal is enabled, are counted according to the clock signal, and generate a reset signal to reset the timing when the count reaches a preset value. Controller. Thereby, the timing controller resets the data before the data is written during each picture, so that the waveforms of the first internal clock signal, the second internal clock signal and the latch control signal output by the timing controller are normal. In addition, the source driver is prevented from capturing the wrong pixel data and displaying an abnormality.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Display device

110, 110', 110", 110'''... reset unit

120. . . Timing controller

130. . . Source driver

140. . . Gate driver

150. . . Display panel

210. . . Frequency dividing circuit

220. . . First phase delay circuit

230. . . Second phase delay circuit

240. . . Third phase delay circuit

310. . . Detection circuit

320. . . Logic circuit

330, 420. . . Counting circuit

410, 510. . . Switch circuit

430. . . Decision circuit

520‧‧‧Control circuit

CLK, CLK'‧‧‧ clock signal

CR‧‧‧ count results

DE‧‧‧ data enable signal

iCLK1, iCLK2‧‧‧ internal clock signal

LAT‧‧‧Latch control signal

RCLK‧‧‧ reference clock signal

RS‧‧‧Reset signal

T1, T2, T3‧‧‧ time

NT‧‧‧Notice signal

SC‧‧‧ scan signal

VP‧‧‧ pixel voltage

S610, S620, S630, S640‧‧‧ steps

1 is a system diagram of a display device in accordance with an embodiment of the present invention.

2A is a circuit diagram of the timing controller of FIG. 1 according to an embodiment of the invention.

2B is a timing diagram of the data enable signal DE, the clock signal CLK, the internal clock signals iCLK1, iCLK2, and the latch control signal LAT of FIG.

FIG. 3 is a circuit diagram of the reset unit of FIG. 1 according to an embodiment of the invention.

4 is a circuit diagram of the reset unit of FIG. 1 according to another embodiment of the present invention.

FIG. 5 is a circuit diagram of the reset unit of FIG. 1 according to still another embodiment of the present invention.

6 is a flow chart of a method of operating a display device in accordance with an embodiment of the present invention.

100. . . Display device

110. . . Reset unit

120. . . Timing controller

130. . . Source driver

140. . . Gate driver

150. . . Display panel

CLK. . . Clock signal

DE. . . Data enable signal

iCLK1, iCLK2. . . Internal clock signal

LAT. . . Latch control signal

RS. . . Reset signal

SC. . . Scanning signal

VP. . . Pixel voltage

Claims (13)

A display device includes: a display panel; a reset unit for receiving a data enable signal and a clock signal, counting according to the clock signal when the data enable signal is enabled, and counting up to one a reset signal is generated by a preset value; a timing controller is coupled to the reset unit to output at least one internal clock signal and at least one control signal, and the timing controller resets according to the reset signal to Resetting the internal clock signal and the control signal to a predetermined level before writing data during each picture; and a source driver coupled to the display panel and the timing controller to be based on the internal The clock signal and the control signal output a plurality of pixel voltages to the display panel. The display device of claim 1, wherein the resetting unit comprises: a detecting circuit for receiving the data enabling signal, and outputting a notification signal when the data enabling signal is enabled; a counting circuit for receiving the clock signal, and counting according to the clock signal to output a counting result; and a logic circuit coupled to the detecting circuit and the counting circuit for controlling the counting circuit according to the notification signal Counting is performed, and the reset signal is output when the counting result is the preset value. The display device of claim 1, wherein the reset unit comprises: a switching circuit for receiving the data enable signal and the clock signal, and outputting the clock signal when the data enable signal is enabled; a counting circuit coupled to the switch circuit to receive the switch circuit output The clock signal is outputted according to the clock signal outputted by the switch circuit, and a counting result is output; and a decision circuit is coupled to the counting circuit to output the weight when the counting result is the preset value Set the signal. The display device of claim 1, wherein the reset unit comprises: a switch circuit for receiving the data enable signal and the clock signal, and outputting the data enable signal when enabled a clock signal; and a control circuit coupled to the switch circuit to receive the clock signal output by the switch circuit, and counting according to the clock signal output by the switch circuit, and counting the preset value The reset signal is output. The display device of claim 1, wherein the timing controller receives the data enable signal and the clock signal to generate the internal clock signals according to the data enable signal and the clock signal. The control signal. The display device of claim 5, wherein the internal clock signals comprise a first internal clock signal and a second internal clock signal, the control signal comprising a latch control signal, the timing control The device includes: a frequency dividing circuit for receiving the data enabling signal and the clock signal, wherein the frequency dividing circuit performs frequency division on the clock signal to generate a reference clock signal And outputting the reference clock signal according to the data enable signal; a first phase delay circuit coupled to the frequency dividing circuit and the reset unit to generate the first internal clock signal according to the reference clock signal And outputting after phase delay, and resetting according to the reset signal; a second phase delay circuit coupled to the frequency dividing circuit and the reset unit to generate the second internal time according to the reference clock signal The pulse signal is output after the phase delay is performed, and reset according to the reset signal; and a third phase delay circuit coupled to the frequency dividing circuit and the reset unit to generate the plug according to the reference clock signal The lock control signal is output after the phase delay is performed, and is reset according to the reset signal; wherein delay phases of the first phase delay circuit, the second phase delay circuit, and the third phase delay circuit are different from each other. The display device of claim 6, wherein the relationship between the delay phases of the first phase delay circuit, the second phase delay circuit, and the third phase delay circuit is as follows: a delay of the first phase delay circuit Phase < Delay phase of the second phase delay circuit < Delay phase of the third phase delay circuit. The display device of claim 6, wherein the reference clock signal has a frequency that is one quarter of a frequency of the clock signal. The display device of claim 1, wherein the reset unit resets the count when the data enable signal is disabled. The display device of claim 1, wherein the preset value is 1. The display device is applicable to the display device having a timing controller, comprising: receiving a data enable signal and a clock signal; and when the data enable signal is enabled, counting according to the clock signal And generating a reset signal to reset the timing controller when counting up to a preset value to reset at least one internal clock signal output by the timing controller before data writing is performed during each picture And at least one control signal to a predetermined level. The method of operating the display device of claim 11, further comprising: resetting the count when the data enable signal is disabled. The method of operating a display device according to claim 11, wherein the preset value is 1.