TWI556223B - Liquid crystal display device and operating method thereof - Google Patents

Description

Liquid crystal display device and operating method thereof

The present invention relates to a display device, and more particularly to a structure of a liquid crystal display device and a method of operating the same.

The current liquid crystal display includes a plurality of columns of pixels, and each column of pixels receives a gate driving signal. When the pixels of the same column are turned on due to the gate driving signal, the turned-on pixels are displayed according to the received display data. . In order to reduce the flicker caused by the parasitic capacitance of the pixel, it is conventional to use a chamfer circuit to make the liquid crystal display have a chamfered gate driving signal to drive the above pixel. Moreover, in order to prevent the pixel from being turned on by the gate driving signal at the wrong time and displaying the wrong display material, that is, the pixel is mischarged, an additional design is required, thereby greatly increasing the internal wiring area of the liquid crystal display and using the component. Quantity, which in turn increases overall energy and cost.

In order to solve the above drawbacks, the present invention provides a liquid crystal display device including a display unit, a clock control unit, and a gate driving module, wherein the display unit has a plurality of pixel units, and the clock control unit is used to generate the time. The pulse signal, the gate drive module is electrically coupled to the clock control unit, and the gate drive module is configured to generate a chamfer gate drive signal according to the clock signal and transmit To the corresponding multiple pixel units, and the chamfered gate drive signal is chamfered according to the clock signal.

In a preferred embodiment of the present invention, the gate driving module further includes a gate driving unit and a chamfering circuit, and the gate driving unit is electrically coupled to the clock control unit to output the gate driving according to the clock signal. The signal, the chamfering circuit is electrically coupled to the plurality of pixel units, the gate driving unit and the clock control unit, and the chamfering circuit is configured to receive the gate driving signal and the clock signal and drive the gate according to the clock signal The signal is chamfered to generate a chamfered gate drive signal, and the chamfering circuit transmits the chamfered gate drive signal to the corresponding plurality of pixel units.

In a preferred embodiment of the present invention, the gate driving module further includes a gate driving unit and a chamfering circuit, and the chamfering circuit is electrically coupled to the clock control unit to receive the clock signal and the high Voltage level, and chamfering the high voltage level according to the clock signal to generate a chamfer high voltage level, the gate driving unit is electrically coupled with the chamfering circuit, the clock control unit and the plurality of pixel units, The gate driving unit is configured to receive the chamfer high voltage level and the clock signal, and generate the chamfering gate driving signal according to the chamfering high voltage level and the clock signal, and transmit the chamfering gate driving signal to the corresponding Multiple pixel units.

In a preferred embodiment of the present invention, the clock signal, the chamfered gate driving signal and the data driving signal have a first type trigger edge and a second type trigger edge, and the second data driving signal The type trigger edge is later than the first pulse trigger edge of the clock signal and the chamfered gate drive signal, and the second type trigger edge of the data drive signal is earlier than the clock signal and the second type of the chamfered gate drive signal State trigger edge.

The invention further provides a method for operating a liquid crystal display device. The liquid crystal display device comprises a plurality of pixel units, a clock control unit and a gate driving module. The clock control unit is configured to output a clock signal and a data driving signal, and the liquid crystal display The operation method of the device includes the following steps: connecting the gate driving module Receiving a clock signal and generating a chamfered gate driving signal; and causing the plurality of pixel units to receive the chamfering gate driving signal, wherein the chamfering gate driving signal is chamfered according to the clock signal.

In a preferred embodiment of the present invention, the gate driving module further includes a gate driving unit and a chamfering circuit. The operating method of the liquid crystal display device further includes: causing the gate driving unit to receive the clock signal and output the signal according to the output. a gate driving signal; the chamfering circuit receives the clock signal and the gate driving signal and chamfers the gate driving signal by the clock signal to output a chamfering gate driving signal.

In a preferred embodiment of the present invention, the gate driving module further includes a gate driving unit and a chamfering circuit. The operating method of the liquid crystal display device further includes: receiving the clock signal and the high voltage level by the chamfering circuit And chamfering the high voltage level according to the clock signal to generate a chamfered high voltage level; enabling the gate driving unit to receive the clock signal and the chamfering high voltage level, and according to the clock signal and the chamfer angle The voltage level produces a chamfered gate drive signal.

In a preferred embodiment of the present invention, the clock signal, the chamfered gate driving signal and the data driving signal have a first type trigger edge and a second type trigger edge, and the second data driving signal The type trigger edge is later than the first pulse trigger edge of the clock signal and the chamfered gate drive signal, and the second type trigger edge of the data drive signal is earlier than the clock signal and the second type of the chamfered gate drive signal State trigger edge.

The invention can effectively avoid the occurrence of mischarge, and therefore the invention can obviously reduce the component routing area and the number of components, and greatly reduce the overall energy and cost consumption.

The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims.

10‧‧‧Liquid crystal display device

11‧‧‧clock control unit

12‧‧‧Gate drive module

121‧‧‧Gate drive unit

122‧‧‧Chamfering circuit

13‧‧‧Data Drive Unit

14‧‧‧Display unit

141‧‧‧ pixel unit

CLK‧‧‧ clock signal

STB, STB1, STB2‧‧‧ data drive signals

G _OUT , G _OUT1 ... G _OUTn ‧‧‧Chamfering gate drive signal

G ₁ , G ₂ ... Gn‧‧‧ gate drive signal

V _GH ‧‧‧high voltage level

V _GHM ‧‧‧Chamfering high voltage level

T, T ₁ , T ₂ ‧ ‧ hours

1A is a schematic view showing a first embodiment of a liquid crystal display device of the present invention.

FIG. 1B is a timing diagram of Embodiment 1 of a liquid crystal display device of the present invention.

2A is a schematic view showing a second embodiment of a liquid crystal display device of the present invention.

2B is a timing diagram of a second embodiment of a liquid crystal display device of the present invention.

3A is a schematic view showing the steps of an operation method of the liquid crystal display device of the present invention.

FIG. 3B is a schematic diagram showing the steps of the second embodiment of the liquid crystal display device of the present invention.

Referring to FIG. 1A, FIG. 1A shows a first embodiment of a liquid crystal display device 10 of the present invention. The liquid crystal display device 10 includes a clock control unit 11, a gate driving module 12, a data driving unit 13, and a display unit 14. The clock control unit 11 is electrically coupled to the gate driving module 12 and the data driving unit 13. The clock control unit 11 is configured to generate the clock signal CLK and the data driving signal STB. The data driving unit 13 is electrically coupled to the clock control unit 11 for receiving the data driving signal STB and outputting the display data according to the data driving signal STB to the display unit 14 electrically coupled. The display unit 14 includes a plurality of pixel units 141. Each of the pixel units 141 is electrically coupled to the data driving unit 13 and the gate driving module 12, and each of the pixel units 141 is configured according to the gate driving module. The 12-output chamfered gate drive signal G _OUT determines whether or not the display material received by the data driving unit 13 is displayed. The gate driving unit 12 includes a gate driving unit 121 and a chamfering circuit 122. The gate driving unit 121 is electrically coupled to the clock control unit 11 and the chamfering circuit 122. The gate driving unit 121 is configured to receive the above. The clock signal CLK generates a gate driving signal corresponding to each column of pixels 141 according to the clock signal CLK, as shown in FIG. 1A, G ₁ , G ₁ ... Gn, the chamfering circuit 122 and the clock control unit 11 and a driving unit 121 is electrically gate coupled chamfered circuit 122 receives the above-described of the clock signal CLK and the gate drive signals G ₁ ... Gn, and for the gate drive signal G received ₁ ... Gn according to the clock signal CLK The chamfered corners generate corresponding chamfered gate drive signals G _OUT1 ... G _OUTn , as shown in FIG. 1A, the chamfering circuit 122 transmits the chamfered gate drive signals G _OUT1 ... G _OUTn to the corresponding columns. The pixel unit 141 enables the pixel unit 141 that receives the corresponding chamfered gate drive signals G _OUT1 ... G _OUTn to turn on and display the received display material.

Referring to FIG. 1B, FIG. 1B is a timing diagram of the clock signal CLK, the data driving signal STB, the gate driving signals G ₁ ... Gn, and the chamfered gate driving signals G _OUT1 ... G _OUTn . In this embodiment, The gate drive signals G ₁ ... Gn take the gate drive signal G ₁ and the gate drive signal G ₂ as an example. The chamfered gate drive signals G _OUT1 ... G _{OUTn are used} as the chamfered gate drive signal G _OUT1 and the chamfered gate The drive signal G _{OUT2 is taken} as an example. Hereinafter, the timing relationship between the signals will be described by taking the gate driving signal G ₁ and the chamfering gate driving signal G _OUT1 as an example. The clock signal CLK, the data driving signal STB, the gate driving signal G ₁ , and the chamfered gate driving signal G _{OUT both} have a first type trigger edge and a second type trigger edge, and the first type trigger edge It may be one of a rising edge or a falling edge, and the second type triggering edge may be the other of the rising edge or the falling edge, and the first type trigger of the gate driving signal G ₁ and the chamfering gate driving signal G _OUT1 The edge and the second type trigger edge have substantially the same enable time, the first type trigger edge of the clock signal CLK and the gate drive signal G ₁ and the first type trigger edge of the chamfer gate drive signal G _OUT1 Having substantially the same enable time, the second type trigger edge of the clock signal CLK is earlier than the gate drive signal G ₁ and the chamfered gate drive signal G _OUT1 , and the first type trigger edge of the data drive signal STB The first type triggering edge of the clock signal CLK, the gate driving signal G ₁ and the chamfering gate driving signal G _OUT1 have the same enabling time, and the enabling time of the second type triggering edge of the data driving signal STB is Earlier than the clock signal CLK, gate drive signal G ₁ And a second type of trigger edge of the chamfered gate drive signal G _OUT1 .

Next, a method of operating the first embodiment of the liquid crystal display device 10 of the present invention will be described below with reference to FIGS. 1A and 1B. First, in the time period T, the gate driving unit 121 receives the clock signal CLK and starts to output the gate driving signal G ₁ , and the second type triggering edge of the data driving signal STB1 corresponding to the gate driving signal G ₁ is late. The time of the first type trigger edge of the gate driving signal G ₁ is enabled, and the data driving unit 13 outputs the display data to the pixel unit 141 according to the second type trigger edge of the data driving signal STB1. In addition, the chamfering circuit 122 receives the clock signal CLK and the gate driving signal G ₁ . As can be seen in FIG. 1B, in the period T _1, the chamfered circuit 122 when the clock signal CLK (e.g., logic low) is a low voltage level, when using low voltage level of the gate clock signal CLK The pole drive signal G ₁ is chamfered to generate a chamfered gate drive signal G _OUT1 , and the chamfered gate drive signal G _{OUT1 is} transmitted to the corresponding pixel unit 141. Wherein chamfered to gate drive signal G _OUT2 as an example, when the chamfering patterns for a first gate drive signal G _OUT2 of the edge trigger is enabled, the corresponding chamfered gate drive signal G _OUT2 of the data driving signal STB2 The first type trigger edge is also enabled at the same time, but the second type trigger edge of the data driving signal STB2 has not been enabled, and the data driving unit 13 is activated according to the second type trigger edge of the data driving signal STB. The display data is transmitted to the electrically coupled pixel unit 141, that is, the interval in which the first type trigger edge of the data driving signal STB2 is enabled but the second type trigger edge is not enabled, that is, During the time period T _{2 of} FIG. 1B, the pixel unit 141 enabled by the chamfered gate drive signal G _OUT2 receives the display data received by the pixel unit 141 enabled by the chamfered gate drive signal G _OUT1 , that is, The display data received by the previous column of pixel units 141, although the pixel unit 141 enabled by the chamfered gate drive signal G _OUT2 in this interval receives the display data of the previous column of pixel units 141, but the data drive signal When the second type of trigger edge of STB2 is enabled, Immediately correct the display data of pixel units cover the display data 141 previously received, the thus chamfered gate drive enable signal G _OUT2 of the unit pixel 141 may still display the normal fast data to be displayed.

2A, FIG. 2A is a second embodiment of the liquid crystal display device 10 of the present invention. The difference between FIG. 2A and FIG. 1A is that the chamfering circuit 122 of FIG. 2A is configured to receive the clock signal CLK and the high voltage level V _{GH .} (for example, logic high), the chamfering circuit 122 chamfers the high voltage level according to the clock signal CLK to generate a chamfered high voltage level V _GHM , and the chamfering circuit 122 further chamfers the high voltage level V _{The GHM is} transmitted to the gate driving unit 121. The gate driving unit 121 of FIG. 2A is configured to receive the clock signal CLK and the chamfer high voltage level V _GHM , and generate the chamfered gate driving signal G _OUT1 according to the clock signal CLK and the chamfer high voltage level V _{GHM .} ...G _OUTn , the gate driving unit 121 transmits the chamfered gate driving signals G _OUT1 ... G _OUTn to the corresponding pixel units 141 as shown in FIG. 2A.

Please refer to FIG. 2B. FIG. 2B is a timing diagram of the clock signal CLK, the data driving signal STB, the high voltage level V _GH , the chamfer high voltage level V _{GHM ,} and the chamfered gate driving signals G _OUT1 ... G _OUTn . In this embodiment, the chamfered gate drive signals G _OUT1 ... G _{OUTn are exemplified} by the chamfered gate drive signal G _OUT1 and the chamfered gate drive signal G _OUT2 . The following uses the chamfered gate drive signal G _OUT1 as an example to illustrate the timing relationship between the signals. The clock signal CLK, the data driving signal STB, and the chamfered gate driving signal G _{OUT both} have a first type trigger edge and a second type trigger edge, and the first type trigger edge and chamfer of the clock signal CLK The first type trigger edge of the gate drive signal G _OUT1 has the same enable time, and the second type trigger edge of the clock signal CLK is earlier than the second type trigger edge of the chamfered gate drive signal G _OUT1 . The first type triggering edge of the data driving signal STB has the same enabling time as the first type triggering edge of the clock signal CLK and the chamfering gate driving signal G _OUT1 , and the second type triggering edge of the data driving signal STB The enable time is earlier than the second type trigger edge of the clock signal CLK and the chamfered gate drive signal G _OUT1 .

Next, a method of operating the second embodiment of the liquid crystal display device 10 of the present invention will be described below with reference to FIGS. 2A and 2B. First, in the period T, chamfering the circuit 122 receives the clock signal CLK and a high voltage level V _GH, chamfered circuit 122 and the clock signal CLK to a high voltage level V _GH for chamfering according to that in FIG. 2B period T _1, The high voltage level V _GH is chamfered by the low voltage level of the clock signal CLK to generate a chamfered high voltage level V _GHM , and the gate driving unit 121 receives the clock signal CLK and the chamfer high voltage level V _GHM time and outputting gate drive signals chamfered G _OUT1, with the gate drive signals G ₁ corresponding to the second data driving signals STB1 patterns of trigger edge triggered late in _a first edge of the gate drive signals G type When enabled, the data driving unit 13 outputs the display data to the pixel unit 141 according to the second type trigger edge of the data driving signal STB1. Wherein chamfered to gate drive signal G _OUT2 as an example, when the chamfering patterns for a first gate drive signal G _OUT2 of the edge trigger is enabled, the corresponding chamfered gate drive signal G _OUT2 of the data driving signal STB2 The first type trigger edge is also enabled at the same time, but the second type trigger edge of the data driving signal STB2 has not been enabled, and the data driving unit 13 is activated according to the second type trigger edge of the data driving signal STB. The display data is transmitted to the electrically coupled pixel unit 141, that is, the interval in which the first type trigger edge of the data driving signal STB2 is enabled but the second type trigger edge is not enabled, that is, In the period T _{2 of} FIG. 2B, the pixel unit 141 enabled by the chamfered gate driving signal G _OUT2 is the display data received by the pixel unit 141 enabled by the chamfered gate driving signal G _OUT1 , although The pixel unit 141 enabled by the chamfered gate drive signal G _OUT2 receives the display data of the previous column of pixel units 141 during this time, and is correct when the second type trigger edge of the data drive signal STB2 is enabled. The display data can immediately cover the previous element of the pixel unit 141 The received display information is thus chamfered gate drive enable signal G _OUT2 of the unit pixel 141 may still display the normal fast data to be displayed.

According to the above, the present invention can further integrate the operation method of the liquid crystal display device 10. Referring to FIG. 3A and FIG. 1A , FIG. 3A is an embodiment of an operation method of the first embodiment of the liquid crystal display device 10 . The following is an example of the gate driving signal G ₁ and the chamfered gate driving signal G _OUT1 . The steps include: The gate driving unit 121 receives the clock signal CLK and outputs the gate driving signal G ₁ according to the clock signal CLK (step 301); then, the chamfering circuit 122 receives the clock signal CLK and the gate driving signal G ₁ , and The gate driving signal G ₁ is chamfered by the clock signal CLK to output the chamfered gate driving signal G _OUT1 (step 302); and the data driving unit 13 outputs multiple signals according to the second type triggering edge of the data driving signal STB. The data is displayed to the plurality of pixel units 141 (step 303); the pixel unit 141 receives the display data and the chamfered gate driving signal G _OUT1 , and the pixel unit 141 is turned on because of the chamfered gate driving signal G _OUT1 , and displays The received display material (step 304). Referring to FIG. 3B and FIG. 1B, FIG. 3B is an embodiment of the operation method of the second embodiment of the liquid crystal display device 10. The step of the method includes: the chamfering circuit 122 receives the clock signal CLK and the high voltage level V _GH according to the clock. The signal CLK chamfers the high voltage level V _GH to generate the chamfered high voltage level V _GHM (step 311); the gate driving unit 121 receives the clock signal CLK and the chamfer high voltage level V _GHM , and according to The clock signal CLK and the chamfered high voltage level V _GHM generate a chamfered gate driving signal G _OUT1 (step 312); the data driving unit 13 outputs a plurality of display data according to the second type trigger edge of the data driving signal STB. The pixel unit 141 (step 313); the pixel unit 141 receives the display data and the chamfered gate driving signal G _OUT1 , the pixel unit 141 is turned on by the chamfering gate driving signal G _OUT1 , and displays the received display. Information (step 304).

In view of the above, the present invention can effectively avoid the occurrence of mis-charging by replacing the external chamfer signal with the clock signal CLK, so that the present invention can effectively reduce the component routing area and the number of components. In turn, the overall energy and cost consumption are greatly reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any one skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope is subject to the definition of the patent application scope.

CLK‧‧‧ clock signal

STB, STB1, STB2‧‧‧ data drive signals

G _OUT , G _OUT1 ‧‧‧ chamfered gate drive signal

G ₁ , G ₂ ‧‧ ‧ gate drive signal

T, T ₁ , T ₂ ‧ ‧ hours

Claims (6)

A liquid crystal display device includes: a display unit having a plurality of pixel units; a clock control unit for generating a clock signal; and a gate driving module electrically coupled to the clock control unit The gate driving module generates a chamfered gate driving signal according to the clock signal and transmits the signal to the corresponding pixel unit, wherein the chamfering gate driving signal is performed according to the clock signal The gate driving module further includes: a gate driving unit electrically coupled to the clock control unit, wherein the gate driving unit is configured to output a gate driving signal according to the clock signal And a chamfering circuit electrically coupled to the pixel unit, the gate driving unit, and the clock control unit, the chamfering circuit is configured to receive the gate driving signal and the clock signal according to The clock signal chamfers the gate drive signal to generate the chamfered gate drive signal, and the chamfer circuit transmits the chamfered gate drive signal to the corresponding pixel units. The liquid crystal display device of claim 1, wherein the liquid crystal display device further comprises a data driving unit, wherein the data driving unit is configured to receive a data driving signal (STB) generated by the clock control unit, and according to The data driving signal outputs a display data to the pixel units electrically coupled. The liquid crystal display device of claim 2, wherein the clock signal, the chamfered gate driving signal, and the data driving signal have a first type trigger edge and a second type trigger edge, the second type trigger edge of the data driving signal is later than the clock signal and the first type trigger edge of the chamfered gate driving signal The second type triggering edge of the data driving signal is earlier than the clock signal and the second type triggering edge of the chamfering gate driving signal. A method of operating a liquid crystal display device includes a plurality of pixel units, a clock control unit, and a gate driving module, wherein the clock control unit outputs a clock signal and a data driving signal, the gate The pole drive module further includes a gate drive unit and a chamfering circuit, wherein the gate drive module receives the clock signal and generates a chamfered gate drive signal, and the operation method of the liquid crystal display device includes the following Step: the gate driving unit receives the clock signal and outputs a gate driving signal; the cornering circuit receives the clock signal and the gate driving signal, and drives the gate with the clock signal The signal is chamfered to output the chamfered gate drive signal; and the pixel unit receives the chamfered gate drive signal; wherein the chamfered gate drive signal is chamfered according to the clock signal. The operating method of the liquid crystal display device of claim 4, further comprising a data driving unit, the operating method of the display panel further comprising the steps of: causing the data driving unit to output a plurality of signals according to the data driving signal Display data to the pixel units. The method of operating a liquid crystal display device according to claim 4, wherein The clock signal, the chamfered gate driving signal and the data driving signal both have a first type triggering edge and a second type triggering edge, and the second type triggering edge of the data driving signal is later than the The first signal triggering edge of the clock signal and the chamfered gate driving signal, the second type triggering edge of the data driving signal is earlier than the clock signal and the second of the chamfering gate driving signal Type trigger edge.