CN102034440B - Gate driver and operating method thereof - Google Patents
Gate driver and operating method thereof Download PDFInfo
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- CN102034440B CN102034440B CN 200910176184 CN200910176184A CN102034440B CN 102034440 B CN102034440 B CN 102034440B CN 200910176184 CN200910176184 CN 200910176184 CN 200910176184 A CN200910176184 A CN 200910176184A CN 102034440 B CN102034440 B CN 102034440B
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Abstract
The invention discloses a gate driver applied in a liquid crystal display device, comprising a plurality of groups of channels and an angle cutting control module, wherein each group of channels comprises a plurality of channels. The angle cutting control module comprises a plurality of angle cutting control units which are respectively and correspondingly connected with the plurality of groups of channels. If a shift registering signal received by the angle cutting control module corresponds to one channel which belongs to one group of channels, then the angle cutting control module starts one angle cutting control unit corresponding to the group of channels according to the shift registering signal, so that a high-potential power signal input to the channel starts to discharge and has a waveform for cutting angles.
Description
Technical field
The present invention relates to a kind of display device, especially, relate to gate drivers (gate driver) and the method for operating thereof of a kind of liquid crystal indicator (LCD display).
Background technology
In recent years, constantly develop because image shows relevant science and technology, the display device of the new kenel of all kinds that occurs on the market replaces traditional cathode ray tube (CRT) display gradually.Wherein, liquid crystal indicator (LCD) extensively receives liking of ordinary consumer owing to have power saving and advantage such as do not take up space, and has therefore become the main flow on the monitor market.
Please with reference to Fig. 1, Fig. 1 shows the synoptic diagram of operational scenario of power management chip and the gate drivers of traditional liquid crystal display device.As shown in Figure 1; The power management chip 1 that is used for liquid crystal indicator traditionally mainly comprises two parts: boost pressure controller (boostregulator) 10 and top rake baud generator (grid impulse modulating converter, gate pulsemodulation switch) 12.Wherein, boost pressure controller 10 boosts to the simulation primary power AVDD of higher pressure in order to the input power supply VIN with low pressure.Simulation primary power AVDD is in order to source electrode driver that liquid crystal indicator is provided, gamma (Gamma) reference voltage impact damper, first charge pump 2 and the required power supply of second charge pump 3.Will produce high levle out-put supply VGH and low level out-put supply VGL respectively as for first charge pump 2 and second charge pump 3, to offer each gate drivers 5.
Generally speaking; After the transmission of signal through the scanning linear of liquid crystal indicator; The waveform of signal will produce distortion because of the influence of dead resistance and stray capacitance delay; The signal that causes being positioned at front end and terminal gate drivers 5 has different waveforms, thereby causes the picture displayed flicker of liquid crystal indicator institute.In order to improve this phenomenon of picture flicker; The high levle out-put supply VGH that first charge pump 2 is exported can't directly offer gate drivers 5; But earlier the top rake baud generator 12 through power management chip 1 is that benchmark carries out top rake to high levle out-put supply VGH and handles with top rake control signal YVC; To produce top rake out-put supply signal VGHM, export top rake out-put supply signal VGHM to each gate drivers 5 again.
Please with reference to Fig. 2, Fig. 2 shows the instance of the top rake baud generator 12 of traditional power management chip 1.As shown in Figure 2, top rake baud generator 12 utilizes P1 and two PMOS of P2 to be external to discharge resistance R1 as switch and discharge node R E.When top rake control signal YVC was in high levle, the reverse signal YVC_N of top rake control signal YVC then was in low level, and at this moment, switch P 1 will be opened and switch P 2 will be closed, so top rake out-put supply signal VGHM will be recharged the VGH to the high-tension electricity position; When top rake control signal YVC is in low level; The reverse signal YVC_N of top rake control signal YVC then is in high levle; At this moment, switch P 1 will be closed and switch P 2 will be opened, so top rake out-put supply signal VGHM will utilize the discharge resistance R1 of ground connection to begin discharge from high-voltage VGH.
Though said method can improve the film flicker phenomenon that liquid crystal indicator runs into, yet, the problem that causes other to be difficult to overcome also.Please with reference to Fig. 3, Fig. 3 shows the sequential chart of traditional top rake baud generator 12 operations.As shown in Figure 3, suppose that high-voltage VGH is 30 volts (V), top rake bottom voltage is 10V.In very first time at interval during the t1, switch P 1 is closed and switch P 2 is opened, and top rake out-put supply signal VGHM will begin to discharge and forms the waveform of top rake discharge node R E.
Then; After the time gets into second time interval t2; Switch P 1 switches to opening and switch P 2 by originally closed condition and switches to closed condition by opening, because general switch P 1 and the resistance of P2 are about 15 ohm or littler, therefore; Will produce burst current in switch P 1 by closing the moment that switches to unlatching, its peak value is about (30 volts-10 volts)/15 ohm=1.3 amperes.
It should be noted that; Become big along with the panel size of liquid crystal indicator is continuous; The passage of gate drivers (channel) number also can become many, makes the load capacitance of top rake out-put supply signal VGHM become big, and the time that causes switch P formed burst current of 1 unlatching moment to be kept is also elongated.On the other hand, the high-voltage VGH of gate drivers also can become big and improves along with panel size, under the constant situation of top rake bottom voltage, also can cause the peak value of burst current to become big, thus cause gate drivers with and the damage on packaging line road.In addition, traditional power management chip 1 must the many design costs of ancillary cost, quite inconvenience in order will the boost pressure controller 10 and the top rake baud generator 12 of the processing with different voltages to be combined.
Therefore, the present invention proposes a kind of gate drivers and method of operating thereof that is applied to liquid crystal indicator, to address the above problem.
Summary of the invention
First specific embodiment according to the present invention is a kind of gate drivers.This gate drivers is applied to a kind of liquid crystal indicator, and this gate drivers comprises many group passages and top rake control module.Each the group passage that should organize in the passages comprises a plurality of passages more.This top rake control module comprises a plurality of top rake control modules, connects respectively and corresponding to these many group passages.If the received shift register signal of this top rake control module is corresponding to a passage; And this passage belongs to one group of passage in these many group passages; Promptly according to the top rake control module of this shift register signal enabling corresponding to this group passage, a high potential power signal that makes this top rake control module input to this passage thus begins to discharge and has the waveform of top rake this top rake control module.
In this specific embodiment, this gate drivers further comprises: the shift register module comprise this shift register signal at interior a plurality of shift register signals in order to generation, and these a plurality of shift register signals corresponds respectively to this a plurality of passages.
In this specific embodiment, this gate drivers further comprises: first charge pump, in order to receive low-tension supply and to produce this high potential power signal according to this low-tension supply; And second charge pump, in order to receive this low-tension supply and to produce the low potential power source signal according to this low-tension supply.
Preferably, in this gate drivers, this liquid crystal indicator comprises power management chip, is connected to this first charge pump and this second charge pump, in order to provide this low-tension supply to this first charge pump and this second charge pump.
In this specific embodiment; In gate drivers; This top rake control module further comprises: the top rake logic controller; In order to judging that pairing this passage of this shift register signal belongs to these group passages in this many group passages, and start this top rake control module of organizing passage corresponding to this according to above-mentioned judged result.
In this specific embodiment, in gate drivers, this active switch of this top rake control module is connected to corresponding to these a plurality of passages in this group passage of this top rake control module.
In this specific embodiment; In gate drivers; This top rake control module further comprises discharge node and the discharge path between this discharge node and ground connection, and when this active switch open, this high potential power signal begins to discharge through this discharge node and this discharge path.
Preferably, in this gate drivers, this top rake control module further comprises discharge resistance, and this discharge resistance is positioned at this discharge path, and this discharge resistance can be in order to the top rake degree of depth of the waveform of adjusting this high potential power signal.
In this specific embodiment, in gate drivers, this top rake control signal is a benchmark with the frequency of this liquid crystal indicator.
In this specific embodiment, this gate drivers is according to top rake function on signal enabling or close this top rake control module.
In this specific embodiment, this gate drivers utilizes this shift register signal to control its subregion top rake function.
According to second specific embodiment of the present invention also is a kind of gate drivers.Be with the gate drivers difference of first specific embodiment; The gate drivers of this embodiment is through the work frequency of the frequency signal of design system suitably; Make its work frequency consistent with the top rake control signal; So can directly replace the top rake control signal of script, with the design of further simplification panel system with the frequency signal of system.
The 3rd specific embodiment according to the present invention is a kind of gate drivers method of operating.This gate drivers is applied to liquid crystal indicator; This gate drivers comprises many group passages and top rake control module; Each the group passage that should organize in the passages comprises a plurality of passages more; This top rake control module comprises a plurality of top rake control modules, and these a plurality of top rake control modules correspond respectively to this many group passages.
This gate drivers method of operating comprises the following step: at first, this top rake control module receives a shift register signal.Then, judge that pairing this passage of this shift register signal belongs to one group of passage in these many group passages.Afterwards, start the top rake control module in these a plurality of top rake control modules according to above-mentioned judged result corresponding to this group passage.Then, this top rake control module is opened an active switch of this top rake control module according to a top rake control signal that receives.At last, this top rake control module high potential power signal of inputing to this passage begins to discharge and has the waveform of top rake.
In this method of operating; This gate drivers further comprises first charge pump and second charge pump; This first charge pump receives low-tension supply and produces this high potential power signal according to this low-tension supply, and this second charge pump receives this low-tension supply and produces the low potential power source signal according to this low-tension supply.
Preferably, this liquid crystal indicator comprises power management chip, in order to provide this low-tension supply to this first charge pump and this second charge pump.
In this method of operating; This top rake control module further comprises discharge node and the discharge path between this discharge node and ground connection; When this active switch open, this high potential power signal begins to discharge through this discharge node and this discharge path.
Preferably, this top rake control module further comprises discharge resistance, and this discharge resistance is positioned at this discharge path, and this discharge resistance can be in order to the top rake degree of depth of the waveform of adjusting this high potential power signal.
In this method of operating, this top rake control signal is a benchmark with the frequency of this liquid crystal indicator.
In this method of operating, this top rake control signal can use the frequency signal of this liquid crystal indicator to replace.
Preferably, this frequency signal has identical work frequency through suitably designing with this top rake control signal, so can be in order to replace this top rake control signal.
In this method of operating, utilize this shift register signal to control subregion top rake function.
Can further be understood through following detailed Description Of The Invention and accompanying drawing about advantage of the present invention and spirit.
Description of drawings
Fig. 1 shows the synoptic diagram of operational scenario of power management chip and the gate drivers of traditional liquid crystal display device.
Fig. 2 shows the instance of the top rake baud generator of traditional power management chip.
Fig. 3 shows the sequential chart of traditional top rake baud generator operation.
Fig. 4 shows the functional block diagram according to the gate drivers of first specific embodiment of the present invention.
Fig. 5 shows the sequential chart of the first top rake control module and the second top rake control module operation in the top rake control module among Fig. 4.
Fig. 6 A shows the synoptic diagram that the first top rake control module and the second top rake control module in the top rake control module among Fig. 4 correspond respectively to first group of passage and second group of passage; Fig. 6 B shows the operator scheme synoptic diagram corresponding to the second channel in first group of passage among Fig. 6 A.
Fig. 7 A shows the functional block diagram that discharge switch is changed into the gate drivers of NMOS; Fig. 7 B shows the operator scheme synoptic diagram corresponding to the second channel in first group of passage among Fig. 7 A.
Fig. 8 A shows the functional block diagram that gate drivers among Fig. 4 further comprises first charge pump and second charge pump; Fig. 8 B shows the functional block diagram that replaces the gate drivers of top rake control signal with frequency signal.
Fig. 9 shows the sequential chart of the first top rake control module and the second top rake control module operation in the top rake control module among Fig. 8 B.
Figure 10 shows the process flow diagram according to the gate drivers method of operating of the 3rd specific embodiment of the present invention.
Embodiment
First specific embodiment according to the present invention is a kind of gate drivers.In this embodiment, this gate drivers is applied to liquid crystal indicator, but not as limit.Identical with prior art is that this liquid crystal indicator also comprises power management chip and gate drivers.Yet; It should be noted that; Because the present invention is produced by gate drivers and exports the top rake out-put supply of each grid to, so when chip designer's designing power supply managing chip, only need consider to be applicable to that the processing (the for example processing of 20V voltage) of boost pressure controller gets final product; So significantly the flow process and the cost of facilitating chip design also can increase the elasticity on the processing selecting.
In addition; The more important thing is; The present invention is divided into a plurality of top rake control modules through the notion of subregion control with the top rake control module in the gate drivers, controls not passage on the same group respectively, to reduce the load capacitance of top rake control module; And, can effectively avoid in the traditional panel system because the shortcoming of lead load (wireloading) IR voltage drop that phenomenon caused owing to be built in gate drivers in the top rake control module.
Please with reference to Fig. 4, Fig. 4 shows the functional block diagram according to the gate drivers of first specific embodiment of the present invention.As shown in Figure 4, gate drivers 4 comprises the accurate offset module in shift register module 41, output enable (enable) control module 42, position 43, output buffer module 44, top rake control module 45.Wherein, shift register module 41 is connected to output enable control module 42; Output enable control module 42 is connected to the accurate offset module 43 in position; The accurate offset module 43 in position is connected to output buffer module 44.
In this embodiment, gate drivers 4 comprises n passage altogether, and this n passage is divided into m group passage in regular turn, and wherein each group passage all comprises r passage, and promptly first group of passage comprises first passage～r passage; Second group of passage comprises (r+1) passage～2r passage; The rest may be inferred for all the other.N, m and r are positive integer.For example, if n=400 and m=4, r=400/4=100 then, but not as limit.As shown in Figure 4, output buffer module 44 comprises the first output buffer cell, 441～the m output buffer cell 44m, corresponds respectively to first group of passage～m and organizes passage; Top rake control module 45 comprises the first top rake control module, 451～the m top rake control module 45m, organizes passage through the first output buffer cell, 441～the m output buffer cell 44m corresponding to first group of passage～m respectively thus.
As shown in Figure 4; The signal that the first top rake control module 451 receives comprises: correspond respectively to first shift register signal S (1)～r shift register signal S (r) of first passage～r passage, top rake function on signal GS_Ctrl, top rake control signal YVC and the high-voltage VGG whether the control first top rake control module 451 is opened, and the first top rake control module 451 will be through the first output buffer cell, 441 outputs, the first high-voltage VGH1 to its corresponding first group of passage.Then the rest may be inferred as for the second top rake control module, 452～the m top rake control module 45m, do not give unnecessary details separately at this.
Be noted that, because the output enable control module 42 that gate drivers 4 comprised, the accurate offset module 43 in position and output buffer module 44 are for known module, so do not add to give unnecessary details.Next, will be respectively describe in detail to module such as topmost shift register module 41 of the present invention and top rake control module 45 and function thereof.
Please be simultaneously with reference to Fig. 5, Fig. 6 A and Fig. 6 B, Fig. 5 shows the first top rake control module 451 and the sequential chart of the second top rake control module, 452 operations in the top rake control module 45; Fig. 6 A shows the synoptic diagram that the first top rake control module 451 and the second top rake control module 452 in the top rake control module 45 correspond respectively to first group of passage and second group of passage; Fig. 6 B shows the operator scheme synoptic diagram corresponding to the second channel in first group of passage among Fig. 6 A.
As shown in the figure; When time T 1; Top rake control module 45 becomes high levle from the shift register module 41 first received shift register signal S (1) by low level; Top rake control module 45 will judge that the pairing first passage of the first shift register signal S (1) belongs to first group of passage, and therefore, top rake control module 45 promptly can start the first top rake control module 451 corresponding to first group of passage.After the first top rake control module 451 is activated; The first top rake logic controller 4510 of the first top rake control module 451 promptly can be opened switch P S1 and off switch PR1 respectively, to export first high-voltage VGH1 to the first group passage through the first output buffer cell 441.
Then; Begin to get into the moment of the 3rd time interval t3 when the time; Because top rake control signal YVC just in time becomes low level by high levle, at this moment, the first top rake logic controller 4510 will and be opened switch P R1 according to top rake control signal YVC difference off switch PS1.
As shown in Figure 5; When switch P R1 opens; Corresponding first passage grid output G1 promptly can begin to discharge through discharge node R E and obtain having the first out-put supply signal G (1) of top rake waveform; When output enable signal OE became low level by high levle, the first out-put supply signal G (1) promptly can be initially located in low pressure current potential VGL.In fact, discharge node R E can be connected to the discharge path (discharging path) through discharge resistance ground connection, but not as limit.In like manner, next, second channel grid output G2～r pass gates output Gr also can be respectively discharge and obtain having second out-put supply signal G (2)～r out-put supply signal G (r) of top rake waveform during the 3rd time interval t3.
It should be noted that the time T 2 shown in Fig. 5 just in time is in the intersection of r out-put supply signal G (r) and (r+1) out-put supply signal G (r+1).Wherein the pairing r passage of r out-put supply signal G (r) belongs to first group of passage and by 451 controls of the first top rake control module; But (r+1) out-put supply signal G (r+1) pairing (r+1) passage belongs to second group of passage by 452 controls of the second top rake control module; Promptly the r passage belongs to different top rake control modules with (r+1) passage and controls; Therefore; Top rake control module 45 will be switched the top rake control module according to r shift register signal S (r) or (r+1) shift register signal S (r+1) corresponding to r passage and (r+1) passage, promptly closes the first top rake control module 451 and opens the second top rake control module 452 in time T 2.Operational scenario as for the second top rake control module 452 is also similar with the first top rake control module 451, so do not give unnecessary details separately.The present invention discloses to utilize the shift register signal to control the method for subregion top rake function, but not as limit.
Moreover though the shown switch P R1 of Fig. 6 A adopts the PMOS assembly, yet in practical application, this discharge switch also can change the NMOS assembly into, the switch NR1 shown in Fig. 7 A.Then show operator scheme synoptic diagram as for Fig. 7 B corresponding to the second channel G2 in first group of passage among Fig. 7 A.
In addition; Can know by Fig. 8 A; Gate drivers 4 only needs the outside to give a low-tension supply VDD, can boost voluntarily through its first inner charge pump 46 and second charge pump 47 and form the high-voltage VGG and the low pressure current potential VGL of output, so can reach the have single power supply chip design of (single supply); For the panel system design, quite convenient and saving design cost.
According to second specific embodiment of the present invention also is a kind of gate drivers.Please with reference to Fig. 8 B, Fig. 8 B shows the functional block diagram of this gate drivers.Comparison diagram 8B and gate drivers shown in Figure 4 can know that both differences are that for the design that can further simplify panel system and the kind that reduces signal, Fig. 8 B replaces the top rake control signal YVC among Fig. 4 with the frequency signal CLK of system.In fact, as long as the work frequency of the frequency signal CLK of design system (duty cycle) suitably makes its work frequency with top rake control signal YVC consistent, get final product the usefulness of direct frequency signal CLK with system as the top rake control signal.Then show the sequential chart of top rake control module 45 operations among Fig. 8 B as for Fig. 9.Comparison diagram 9 can know that with Fig. 5 both difference only are that also Fig. 9 replaces the top rake control signal YVC among Fig. 5 with the frequency signal CLK of system, so do not give unnecessary details separately.
In sum; The gate drivers of present embodiment is except having the advantages such as chip design of avoiding damage that burst current causes and single power supply; Can also replace top rake control signal YVC with the frequency signal CLK that system just has originally; So can further simplify the design of panel system, to promote the market competitiveness of the liquid crystal indicator of using gate drivers.
The 3rd specific embodiment according to the present invention is a gate drivers method of operating.In this embodiment; This gate drivers is arranged in the liquid crystal indicator; This gate drivers comprises many group passages and top rake control module; Each the group passage that should organize in the passages comprises a plurality of passages more, and this top rake control module comprises a plurality of top rake control modules, and these a plurality of top rake control modules correspond respectively to this many group passages.
Please with reference to Figure 10, Figure 10 shows the process flow diagram according to the gate drivers method of operating of the 3rd specific embodiment of the present invention.Shown in figure 10, at first, this method execution in step S10, this top rake control module receives a shift register signal.Then, this method execution in step S12 judges that pairing this passage of this shift register signal belongs to one group of passage in these many group passages.
In practical application, need only the suitably work frequency of the frequency signal of design system, make its work frequency consistent with the top rake control signal, can directly replace the top rake control signal of script with the frequency signal of system.Then, this method execution in step S14 starts the top rake control module corresponding to this group passage in these a plurality of top rake control modules according to above-mentioned judged result.Then, in step S16, this top rake control module is opened the active switch of this top rake control module according to a top rake control signal that receives.In fact, this active switch can be PMOS assembly or NMOS assembly.At last, in step S18, the high potential power signal that this top rake control module inputs to this passage begins to discharge and has the waveform of top rake.Can not give unnecessary details separately at this with reference to the explanation of above-mentioned first specific embodiment and correlative type thereof as for detailed gate drivers operator scheme.
Than prior art; When producing the top rake ripple except can effectively avoiding traditional power management chip, gate drivers according to the present invention the damage of formed burst current for gate drivers, also has the advantages such as complexity that adopt single power supply, reduce signal kinds and simplify power management chip design originally.The more important thing is; The present invention is divided into a plurality of top rake control modules through the notion of subregion control with the top rake control module in the gate drivers; To reduce the load capacitance of top rake control module; And, can effectively avoid in the traditional panel system because the shortcoming of the lead load IR voltage drop that phenomenon caused owing to be built in gate drivers in the top rake control module.Therefore, gate drivers of the present invention can significantly be simplified the design cycle and the cost of integral panels display system, to promote the competitive power of panel display on market of using this gate drivers.
Through the detailed description of above preferred specific embodiment, hope can be known description characteristic of the present invention and spirit more, and is not to come protection scope of the present invention is limited with the above-mentioned preferred specific embodiment that is disclosed.On the contrary, its objective is hope the present invention can contain the arrangement of various changes and tool equality in the protection domain of the patent that will apply for.
The primary clustering symbol description
S10～S18: process step G1～Gn: pass gates
1: power supply control chip 10: boost pressure controller
12: top rake baud generator 2,46: the first charge pumps
4: gate drivers 3,47: the second charge pumps
PR1, PS1, NR1: switch R1, R: resistance
RE: discharge node t1: the very first time at interval
T2: second time interval T1, T2: time
T3: the 3rd time interval 41: shift register module
43: the accurate offset module 42 in position: output enable control module
44: output buffer module 45: top rake control module
441～44m: output buffer cell 451～45m: top rake control module
DIO: input signal DOI: output signal
452: active switch CLK: frequency signal
OE: output enable signal YVC: top rake control signal
VGG, VGH1～VGHm: high-voltage
VGL: low pressure current potential
VDD: low-tension supply
G (1)～G (n): out-put supply signal
S (1)～S (n): shift register signal
4510,4520: the top rake logic controller.
Claims (22)
1. a gate drivers is arranged in the liquid crystal indicator, and said gate drivers comprises:
Many group passages, and each the group passage in said many group passages comprises a plurality of passages; And
The top rake control module comprises:
A plurality of top rake control modules; Connect respectively and corresponding to said many group passages; If the received shift register signal of said top rake control module is corresponding to a passage; And said passage belongs to one group of passage in said many group passages; Said top rake control module is promptly according to the top rake control module corresponding to said group of passage in the said a plurality of top rake control modules of said shift register signal enabling, and said top rake control module is opened the active switch of said top rake control module according to the top rake control signal that receives, and the high potential power signal that makes said top rake control module input to said passage thus begins to discharge and has the waveform of top rake.
2. gate drivers according to claim 1 further comprises:
The shift register module comprise said shift register signal at interior a plurality of shift register signals in order to generation, and said a plurality of shift register signal corresponds respectively to said a plurality of passage.
3. gate drivers according to claim 1 further comprises:
First charge pump is in order to receive low-tension supply and to produce said high potential power signal according to said low-tension supply; And
Second charge pump is in order to receive said low-tension supply and to produce the low potential power source signal according to said low-tension supply.
4. gate drivers according to claim 3; Wherein said liquid crystal indicator comprises power management chip; Be connected to said first charge pump and said second charge pump, in order to provide said low-tension supply to said first charge pump and said second charge pump.
5. gate drivers according to claim 1, wherein said top rake control module further comprises:
The top rake logic controller belongs to said group of passage in said many group passages in order to judge the pairing said passage of said shift register signal, and starts the said top rake control module corresponding to said group of passage according to above-mentioned judged result.
6. gate drivers according to claim 1, the said active switch of wherein said top rake control module is connected to corresponding to the said a plurality of passages in the said group of passage of said top rake control module.
7. gate drivers according to claim 1; Wherein said top rake control module further comprises discharge node and the discharge path between said discharge node and ground connection; When said active switch open, said high potential power signal begins to discharge through said discharge node and said discharge path.
8. gate drivers according to claim 7; Wherein said top rake control module further comprises discharge resistance; Said discharge resistance is positioned at said discharge path, and said discharge resistance can be in order to the top rake degree of depth of the waveform of adjusting said high potential power signal.
9. gate drivers according to claim 1, wherein said top rake control signal is a benchmark with the frequency of said liquid crystal indicator.
10. gate drivers according to claim 1, wherein said top rake control signal can use the frequency signal of said liquid crystal indicator to replace.
11. gate drivers according to claim 10, wherein said frequency signal is through fitting
Has identical work frequency (dutycycle) when design with said top rake control signal, so can be in order to replace said top rake control signal.
12. gate drivers according to claim 1 is according to top rake function on signal enabling or close said top rake control module.
13. gate drivers according to claim 1 utilizes said shift register signal to control its subregion top rake function.
14. the method for an operation gate driver; Said gate drivers is arranged in the liquid crystal indicator; Said gate drivers comprises many group passages and top rake control module, and each the group passage in said many group passages comprises a plurality of passages, and said top rake control module comprises a plurality of top rake control modules; Said a plurality of top rake control module corresponds respectively to said many group passages, and said method comprises the following step:
Said top rake control module receives the shift register signal;
Judge that the pairing said passage of said shift register signal belongs to one group of passage in said many group passages;
Start the top rake control module in said a plurality of top rake control module according to above-mentioned judged result corresponding to said group of passage; And
Said top rake control module is opened the active switch of said top rake control module according to the top rake control signal that receives, and the high potential power signal that makes said top rake control module input to said passage thus begins to discharge and has the waveform of top rake.
15. method according to claim 14; Wherein said gate drivers further comprises first charge pump and second charge pump; Said first charge pump receives low-tension supply and produces said high potential power signal according to said low-tension supply, and said second charge pump receives said low-tension supply and produces the low potential power source signal according to said low-tension supply.
16. method according to claim 15, wherein said liquid crystal indicator comprises power management chip, in order to provide said low-tension supply to said first charge pump and said second charge pump.
17. method according to claim 14; Wherein said top rake control module further comprises discharge node and the discharge path between said discharge node and ground connection; When said active switch open, said high potential power signal begins to discharge through said discharge node and said discharge path.
18. method according to claim 17, wherein said top rake control module further comprises discharge resistance, and said discharge resistance is positioned at said discharge path, and said discharge resistance can be in order to the top rake degree of depth of the waveform of adjusting said high potential power signal.
19. method according to claim 14, wherein said top rake control signal is a benchmark with the frequency of said liquid crystal indicator.
20. method according to claim 14, wherein said top rake control signal can use the frequency signal of said liquid crystal indicator to replace.
21. method according to claim 20, wherein said frequency signal have identical work frequency through suitably designing with said top rake control signal, so can be in order to replace said top rake control signal.
22. method according to claim 14 utilizes said shift register signal to control subregion top rake function.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910176184 CN102034440B (en) | 2009-09-24 | 2009-09-24 | Gate driver and operating method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910176184 CN102034440B (en) | 2009-09-24 | 2009-09-24 | Gate driver and operating method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN102034440A CN102034440A (en) | 2011-04-27 |
| CN102034440B true CN102034440B (en) | 2012-12-19 |
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| TWI440011B (en) * | 2011-10-05 | 2014-06-01 | Au Optronics Corp | Liquid crystal display having adaptive pulse shaping control mechanism |
| TW201340069A (en) * | 2012-03-16 | 2013-10-01 | Au Optronics Corp | Display device and method for generating scanning signal thereof |
| CN104575410B (en) * | 2013-10-18 | 2018-12-28 | 联咏科技股份有限公司 | Electricity saving method and its related liquid crystal display |
| CN104332145B (en) | 2014-11-07 | 2017-03-01 | 深圳市华星光电技术有限公司 | Liquid crystal panel and its driving method, liquid crystal display |
| CN105206248B (en) | 2015-11-09 | 2019-07-05 | 重庆京东方光电科技有限公司 | Display driver circuit, display device and display driving method |
| TWI556223B (en) * | 2015-11-17 | 2016-11-01 | 友達光電股份有限公司 | Liquid crystal display device and operating method thereof |
| CN105489151B (en) * | 2015-11-30 | 2019-07-23 | 深圳市华星光电技术有限公司 | Top rake route and display panel |
| CN105590610B (en) * | 2016-03-18 | 2019-04-05 | 深圳市华星光电技术有限公司 | Corner cutting circuit in liquid crystal display panel drive system |
| CN113689818B (en) * | 2021-10-25 | 2022-02-11 | 常州欣盛半导体技术股份有限公司 | Gate driving circuit and driving chip comprising same |
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| CN101029984A (en) * | 2007-04-11 | 2007-09-05 | 友达光电股份有限公司 | Crystal-liquid display device and its pulse-wave adjusting circuit |
| CN101226714A (en) * | 2008-02-02 | 2008-07-23 | 友达光电股份有限公司 | Flat display device as well as control circuit and control method thereof |
| TW200939190A (en) * | 2008-03-06 | 2009-09-16 | Novatek Microelectronics Corp | Driving device and related transformation device of output enable signals in an LCD device |
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| CN101029984A (en) * | 2007-04-11 | 2007-09-05 | 友达光电股份有限公司 | Crystal-liquid display device and its pulse-wave adjusting circuit |
| CN101226714A (en) * | 2008-02-02 | 2008-07-23 | 友达光电股份有限公司 | Flat display device as well as control circuit and control method thereof |
| TW200939190A (en) * | 2008-03-06 | 2009-09-16 | Novatek Microelectronics Corp | Driving device and related transformation device of output enable signals in an LCD device |
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