CN104575410B - Electricity saving method and its related liquid crystal display - Google Patents
Electricity saving method and its related liquid crystal display Download PDFInfo
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- CN104575410B CN104575410B CN201310493478.8A CN201310493478A CN104575410B CN 104575410 B CN104575410 B CN 104575410B CN 201310493478 A CN201310493478 A CN 201310493478A CN 104575410 B CN104575410 B CN 104575410B
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Abstract
The invention discloses a kind of electricity saving methods and its related liquid crystal display in a liquid crystal display.The liquid crystal display includes multi-strip scanning line.The electricity saving method includes that the multi-strip scanning line is divided into multiple scan line groups；And in multiple different time points, a top rake function is started to every scan line group in multiple scan line group respectively.
Description
Technical field
The present invention relates to a kind of electricity saving method and its related liquid crystal displays, more particularly to can timesharing one top rake function of execution
Electricity saving method and its related liquid crystal display.
Background technique
Liquid crystal display (Liquid Crystal Display；LCD) have frivolous external form, power saving and Low emissivity etc. excellent
Point, therefore it has been widely used in calculator screen, mobile phone, PDA(Personal Digital Assistant), flat-surface television and other
On the electronic products such as communication/amusement equipment.The working principle of liquid crystal display be using change liquid crystal layer both ends voltage difference come
Change the ordered state of the liquid crystal molecule in liquid crystal layer, change the translucency of liquid crystal layer accordingly, then backlight module is cooperated to be provided
Light source to show image.
Referring to FIG. 1, Fig. 1 is a thin film transistor (TFT) (Thin Film Transistor, TFT) liquid crystal of the prior art
Show the schematic diagram of device 10.Thin Film Transistor-LCD 10 includes a liquid crystal display panel (LCD Panel) 122, one timing
Controller (timing controller) 102, one source driver 104(source driver) and a gate drivers
(gate driver) 106.Liquid crystal display panel 122 is to be made of two substrates (Substrate), and be filled between two substrates
Liquid crystal material (LCD layer).Multiple data lines (Data Line) 110, a plurality of perpendicular to data line are provided on one substrate
110 scan line (Scan Line or grid line, Gate Line) 112 and multiple thin film transistor (TFT)s 114, and in another base
A shared electrode (Common Electrode) is provided on plate to be used to provide a share voltage.For purposes of illustration only, Fig. 1 is only shown
Four thin film transistor (TFT)s 114, in fact, in liquid crystal display panel 122 each data line 110 and scan line 112 junction
(Intersection) it is respectively connected with a thin film transistor (TFT) 114, that is, thin film transistor (TFT) 114 is that liquid is distributed in a manner of matrix
On LCD panel 122, each data line 110 corresponds to a line (Column) of Thin Film Transistor-LCD 10, and sweeps
A column (Row) of the line 112 corresponding to Thin Film Transistor-LCD 10 are retouched, and each thin film transistor (TFT) 114 corresponds to one
Pixel (Pixel).In addition, the circuit characteristic that the two substrates of liquid crystal display panel 122 are constituted can be considered an equivalent capacity 116.
Details are as follows for the driving principle of existing Thin Film Transistor-LCD 10.Firstly, sequence controller 102 generates phase
Control signal and clock signal needed for data-signal and driving liquid crystal display panel 122 about display image.Source drive
Device 104 and gate drivers 106 are according to the signal that sequence controller 102 transmits and to different data line 110 and scan line 112
Driving signal is generated, thus controls the potential difference at 116 both ends of conducting and equivalent capacity of thin film transistor (TFT) 114, and further
Change the arrangement and corresponding light penetration of liquid crystal molecule.For example, gate drivers 106 are defeated to scan line 112
Entering a pulse wave is connected thin film transistor (TFT) 114, therefore the signal of 104 input data lines 110 of source electrode driver can be via film
Transistor 114 and input equivalent capacity 116, therefore reach grayscale (Gray Level) state for controlling corresponding pixel.In addition,
The signal magnitude for being input to data line 110 by controlling source electrode driver 104, can produce different grayscale sizes.
When the thin film transistor (TFT) 114 of Thin Film Transistor-LCD 10 charges, the gate driving of gate drivers 106
Signal will cause penetrating (Feed-through) effect from the voltage change that the quasi- Wei ﹙ Vgh ﹚ of Gao falls on the quasi- Wei ﹙ Vgl ﹚ of Di and occur,
So that the target level that pixel builtin voltage level is charged to than expection originally is low.If because of electricity inside pixel caused by penetrating effect
Press level gap excessive, when display will generate flashing (Flicker) phenomenon.And it to solve because of sudden strain of a muscle caused by penetrating effect
Bright, one of mode is exactly the generation top rake wave mode on gate drive signal.The advantages of top rake wave mode, is: as the quasi- Wei ﹙ of Gao
The moment pressure difference of the quasi- Wei ﹙ Vgl ﹚ of Vgh ﹚ and Di becomes smaller, and penetrating effect can reduce.
However, top rake circuit used in existing gate drivers 106 (Wave-Shaping Circuit) is to its electricity
Source power supply unit executes the movement of charge and discharge, further to electric capacity of voltage regulation charge and discharge, therefore very power consumption.Another practice is to utilize
One power management chip switches the high levle of the gate drive signal of gate drivers 106, but still needs to drive all grids
Dynamic 106 charge and discharge of device, still very power consumption.
Summary of the invention
Therefore, the present invention provides a kind of electricity saving method in a liquid crystal display, starts a top rake function to reduce
Caused power consumption.
The present invention discloses a kind of electricity saving method in a liquid crystal display.Wherein, the liquid crystal display includes more
Scan line.The electricity saving method includes that the multi-strip scanning line is divided into multiple scan line groups；And when multiple different
Between point, respectively in the multiple scan line group every scan line group start a top rake function.
Invention additionally discloses a kind of liquid crystal displays.The liquid crystal display includes multiple scan line groups and multiple points
When top rake circuit.Every scan line group of the multiple scan line group includes multi-strip scanning line.The multiple timesharing top rake
Circuit is used to that a top rake is respectively started to every scan line group in the multiple scan line group in multiple different time points
Function, wherein each timesharing top rake circuit of the multiple timesharing top rake circuit is coupled to sweeping for the multiple scan line group
Retouch line-group group.Each timesharing top rake circuit includes a top rake unit and a control logic unit.The top rake unit is used
To execute a top rake function.The control logic unit is coupled to the top rake unit, for controlling the top rake unit starting
The top rake function.
Detailed description of the invention
Fig. 1 is the schematic diagram of a Thin Film Transistor-LCD of the prior art.
Fig. 2 is schematic diagram of the embodiment of the present invention for a power saving process 20 of a liquid crystal display.
Fig. 3 is a timing diagram of the embodiment of the present invention.
Fig. 4~5 are the schematic diagram of timesharing of embodiment of the present invention top rake circuit.
Fig. 6~8 are the schematic diagram of the realization circuit of power saving of embodiment of the present invention process 20.
Fig. 9 A is the schematic diagram of a realization circuit of power saving of embodiment of the present invention process 20.
Fig. 9 B is a signal waveforms of Fig. 9 A.
Figure 10 A is the schematic diagram of a realization circuit of power saving of embodiment of the present invention process 20.
Figure 10 B is a signal waveforms of Figure 10 A.
Figure 11 A is the schematic diagram of a realization circuit of power saving of embodiment of the present invention process 20.
Figure 11 B is a signal waveforms of Figure 11 A.
Wherein, the reference numerals are as follows:
Specific embodiment
Referring to FIG. 2, Fig. 2 is schematic diagram of the embodiment of the present invention for a power saving process 20 of a liquid crystal display.Institute
Stating liquid crystal display includes multi-strip scanning line.Power saving process 20 can reduce the penetrating effect of the liquid crystal display and save electricity
Source consumption, it includes following steps:
Step 200: starting；
Step 202: the multi-strip scanning line is divided into multiple scan line groups；
Step 204: in multiple different time points, every scan line group in the multiple scan line group being opened respectively
A dynamic top rake function；
Step 206: terminating.
It is opened respectively according in power saving process 20, every scan line group of multiple scan line groups puts in different times
Dynamic top rake (wave-shaping) function.That is, only a scan line group will start top rake function in same time point
Energy.Wherein, top rake function can be used in LCD Panel, so that a gate drive signal of liquid crystal display generates a top rake
Waveform, to reduce flashing (Flicker) phenomenon caused by penetrating (Feed-through) effect.Since power saving process 20 is staggered
The starting time of every scan line group top rake function, therefore need when can avoid multiple scan line groups while starting top rake function
Want the load of charge and discharge, further economization power supply.Therefore, power saving process 20 of the invention can save the liquid crystal display and execute
Electrical source consumption when top rake function.
Top rake function can start according to an incoming initial pulse STI, an an outflow initial pulse STO and clock signal CK
Or it closes.Referring to FIG. 3, Fig. 3 is that the embodiment of the present invention starts and close a timing diagram of top rake function.As shown in figure 3, working as
When incoming initial pulse STI comes, top rake function starts in the drop edge of clock signal CK, gate drive signal V_gpulse's
Wave edges generate top rake.When outflow initial pulse STO comes, top rake function is closed.On the other hand, believed by different clocks
It number can be achieved to start a top rake function to every scan line group in multiple scan line groups respectively in different time point.Citing
For, according to an incoming initial pulse STI and clock signal CKD(1), top rake function is started to scan line group G_1, and
According to an incoming initial pulse STI and clock signal CKD(2), then it can start the top rake function to scan line group G_2
Energy.In other words, by different clock signals, top rake function can be started to each scan line group respectively in different time points
Energy.In embodiments of the present invention, clock signal CKD(1) and clock signal CKD(2) can be by by clock signal CK frequency elimination institute
It generates.
In addition, it may include according to multiple gate drivers by multi-strip scanning that multi-strip scanning line, which is divided into multiple scan line groups,
Line is divided into multiple scan line groups, and multi-strip scanning line is divided into multiple sweep according to scan line sequence or scan line quantity
Retouch the wherein at least one mode of line-group group.For example, liquid crystal display includes multi-strip scanning line.Multi-strip scanning line can basis
Multiple gate drivers are divided into multiple scan line groups, and every scan line group corresponds to a gate drivers group grid therein
Driver.That is, only starting the top rake function of single gate drivers on same time point, not starting other grid
The top rake function of driver avoids whole gate drivings with the time for each gate drivers starting top rake function that is staggered
Device starts top rake function simultaneously, to achieve the purpose that power saving.In other embodiments of the present invention, process 20 is not limited applied to more
A gate drivers can also be applied to the multi-strip scanning line in single gate drivers.In the case, in a gate drivers
Multi-strip scanning line can according to a particular scan sequence or a certain amount of adjacent scanning lines be divided into multiple scan line groups.
For example, a gate drivers include n scan line g(1), g(2), g(3) ..., g(n), and per k adjacent scan line
Can be divided into a group, therefore multi-strip scanning line g(1), g(2), g(3) ..., g(n) can be divided into n/k groups in total (that is, scan line group
G_1, G_2 ..., G_n/k), include scan line g(1 in scan line group G_1), g(2), g(3) ..., g(k)；Scan line-group
Group G_2 include g(k+1), g(k+2), g(k+3) ..., g(2k), and so on.In another embodiment of the present invention, multi-strip scanning line
G(1), g(2), g(3) ..., g(n) a group can be divided into every p scan line.That is, scan line group G_1 includes to sweep
Retouch line g(1), g(1+p), g(1+2p) ...；Scan line group G_2 includes scan line g(2), g(2+p), g(2+2p) ..., according to
This analogizes.As p=2, then the scan line for representing odd number is divided into a group, and the scan line of even number is divided into another group.In addition, above-mentioned
Two methods can also arrange in pairs or groups mutually, and after multi-strip scanning line is divided into m groups, odd number group and even number are subdivided in each group
Group；Or multi-strip scanning line first divides odd number group and even number group, and m1 groups are subdivided in odd number group, subdivides m2 in even number group
Group.
Referring to FIG. 4, Fig. 4 is the schematic diagram of one timesharing top rake circuit 40 of the embodiment of the present invention.Timesharing top rake circuit 40 can
For in a liquid crystal display, being used in one top rake function time saving power consumption of execution.Timesharing top rake circuit 40 is cut comprising one
Angle unit 400 and a control logic unit 420.Top rake unit 400, for executing top rake function.Control logic unit 420,
It is coupled to top rake unit 400, starts top rake function for controlling top rake unit 400.About control logic unit 420 and top rake
The implementation of unit 400 can refer to Fig. 5.Fig. 5 is the schematic diagram of one timesharing top rake circuit 50 of the embodiment of the present invention.Timesharing top rake
Circuit 50 can be used to realize timesharing top rake circuit 40.Top rake circuit 50 includes a top rake unit 500 and a control logic unit
520.Control logic unit 520 includes a flip-flop 521, one and door 522 and a NAND gate 523.Flip-flop 521 has one the
One input terminal, for receiving an incoming initial pulse STI, one second input terminal, for receive an outflow initial pulse STO and
One output end, for exporting an enable signal EN.Wherein, it is passed to initial pulse STI and outflow initial pulse STO is used to start
And close top rake function.With door 522 there is a first input end to be used to for receiving enable signal EN, one second input terminal
A clock signal CK and an output end are received, for exporting a switch-over control signal C1.NAND gate 523 has one first input
End, for receiving enable signal EN, one second input terminal, for receiving clock signal CK and an output end, for exporting one
Switch-over control signal C2.Wherein, switch-over control signal C1 and switch-over control signal C2 can be used to control the starting of top rake unit 500
Top rake function.Top rake unit 500 includes switch SW1, SW2 and an impedance component RE.Switch SW1, SW2 basis can be cut respectively
It changes control signal C1, C2 execution to open or close, and then starts top rake function.Switch SW1, SW2 can switch for two transistor, resistance
Anti- component RE can be a resistance.In addition, one current source may replace impedance component RE in other embodiments of the present invention, cut with realizing
Angle unit 500.
Referring to FIG. 6, Fig. 6 is the schematic diagram of a realization circuit 60 of power saving of embodiment of the present invention process 20.For the sake of clarity,
Realize that circuit 60 only draws members.Realize that circuit 60 includes multiple top rake units 600 and multiple control logic units
620.Each top rake unit of multiple top rake units 600 includes switch SW1, SW2, and shares an impedance component RE.Realize circuit
60 according to gate drivers Gate(1), Gate(2) ..., Gate(m) multi-strip scanning line (in being not shown in figure 6) is divided into scanning
Line-group group G_1, G_2 ..., G_m.Every scan line group is coupled to a control logic unit 620 and a top rake unit 600.
Each control logic unit tool is respectively intended to receive an incoming initial pulse STI, an outflow initial pulse there are three input terminal
A STO and clock signal CK, and opened according to incoming initial pulse STI, outflow initial pulse STO and clock signal CK control
Close SW1, SW2.Multiple top rake units 600 are coupled to an a voltage source VGG and target potential VGPM, and are respectively coupled to each
The scan line of scan line group, to provide the one high levle voltage VGH(x of gate drive signal of every scan line group) and one
Low level voltage VEE, wherein x=1,2 ..., m.When incoming initial pulse STI comes, multiple control logic units 620 are according to biography
Enter initial pulse STI and clock signal CK, sequential start gate drivers Gate(1), Gate(2) ..., Gate(m) cut
Angle function avoids whole gate drivers so that only having a gate drivers on same time point will start top rake function
Start top rake function simultaneously, to achieve the purpose that power saving.
Referring to FIG. 7, Fig. 7 is the schematic diagram of another realization circuit 70 of power saving of embodiment of the present invention process 20.To ask letter
It is clean, realize that circuit 70 only draws members.Realize that circuit 70 can be used in single gate drivers, it includes multiple top rake lists
Member 700 and multiple control logic units 720.Each top rake unit of multiple top rake units 700 includes switch SW1, SW2, and
A shared impedance component RE.Realize circuit 70 according to certain amount of adjacent scanning lines (such as: k adjacent scanning lines divide a group)
By multi-strip scanning line (being not illustrated in Fig. 7) be divided into m scan line group (that is, scan line group G_1, G_2 ..., G_m), it is each
Scanning line-group is coupled to a control logic unit 720 and a top rake unit 700.There are three inputs for each control logic unit tool
End is respectively intended to receive an incoming initial pulse STI, an an outflow initial pulse STO and clock signal CK, and according to incoming
Initial pulse STI, outflow initial pulse STO and clock signal CK control switch SW1, SW2.Multiple top rake units 700 couple
To an a voltage source VGG and target potential VGPM, and it is respectively coupled to the scan line of every scan line group, it is each to provide
One high levle voltage VGH(x of the gate drive signal of scan line group) an and low level voltage VEE, wherein x=1,2 ...,
m.When incoming initial pulse STI comes, multiple control logic units 720 according to incoming initial pulse STI and clock signal CK,
Sequential start scan line group G_1, G_2 ..., the top rake function of G_m so that only having a scan line group on same time point
It will start top rake function, avoid whole scan line groups while starting top rake function, to achieve the purpose that power saving.
Referring to FIG. 8, Fig. 8 is the schematic diagram of a realization circuit 80 of power saving of embodiment of the present invention process 20.For the sake of clarity,
Fig. 8 only draws members.Realize that circuit 80 can be used in single gate drivers, it includes multiple top rake units 800 and
Multiple control logic units 820.Each top rake unit of multiple top rake units 800 includes switch SW1, SW2, and shares an impedance
Component RE.Realize circuit 80 according to particular scan sequence (such as: dividing a group every k scan line) by multi-strip scanning line (not
It is shown in Figure 8) be divided into m scan line group (that is, scan line group G_1, G_2 ..., G_m), every scan line group is coupled to one
Control logic unit 820 and a top rake unit 800.There are four input terminals for each control logic unit tool, are respectively intended to receive
One incoming initial pulse STI, an outflow initial pulse STO, a clock signal CK and a clock signal CKD(x), wherein x=1,
2,…,m.Multiple top rake units 800 are coupled to an a voltage source VGG and target potential VGPM, and are respectively coupled to often sweep
The scan line of line-group group is retouched, to provide a high levle voltage VGH(x of the gate drive signal of every scan line group) and one
Low level voltage VEE, wherein x=1,2 ..., m.Pass through different clock signal CKD(x), multiple control logic units 820 can be wrong
Open multiple scan line group G_1, G_2 ..., G_m starting top rake function time point, avoid whole scan line groups while opening
Dynamic top rake function, to achieve the purpose that power saving.
It please also refer to showing for the realization circuit 90 that Fig. 9 A and Fig. 9 B, Fig. 9 A are power saving of embodiment of the present invention process 20
It is intended to, Fig. 9 B is a signal waveforms of Fig. 9 A.Realize that circuit 90 can be used for a liquid crystal display, for the odd scan that is staggered
The time of line-group group G_odd and even-line interlace line-group group G_even starting top rake function.Realize that circuit 90 includes one the
One top rake unit 900, one first control logic unit 920, one second top rake unit 940 and one second control logic unit
960.First top rake circuit 900 is coupled to a voltage source VGG, a target potential VGPM and an even-line interlace line-group group G_
Even, to provide a high levle voltage VGH_even of even-line interlace line-group group G_even.First top rake circuit 900 includes out
SW1, SW2 are closed, and shares an impedance component RE with the second top rake circuit 940.First control logic unit 920 includes one positive and negative
Device 921, one and door 922 and a NAND gate 923.Flip-flop 921 has a first input end, for receiving an incoming starting arteries and veins
STI, one second input terminal are rushed, for receiving an outflow initial pulse STO and an output end, for exporting an enable signal
EN1.There is a first input end with door 922, for receiving enable signal EN1, one second input terminal, when for receiving one first
Clock signal CK, a third input terminal are used to control switch SW1 and open for receiving a second clock signal and an output end
Or it closes.NAND gate 923 has a first input end, for receiving enable signal EN1, one second input terminal, for receiving the
One clock signal CK, a third input terminal are opened for receiving second clock signal and an output end for control switch SW2
It opens or closes.Wherein, produced by second clock signal is reversed after the first clock signal CK frequency elimination.Second top rake circuit, 940 coupling
It is connected to the scan line of a voltage source VGG, a target potential VGPM and an odd-numbered scan lines group G_odd, is swept with providing odd number
Retouch a high levle voltage VGH_odd of line-group group G_odd.Second top rake unit 940 includes switch SW3, SW4, and with first
Top rake circuit 900 shares an impedance component RE.Second control logic unit 960 include a flip-flop 961, one with door 962 with
An and NAND gate 963.Flip-flop 961 has a first input end, for receiving incoming initial pulse STI, one second input terminal,
For receiving outflow initial pulse STO and an output end, for exporting an enable signal EN2.It is defeated with one first with door 962
Enter end, for receiving enable signal EN2, one second input terminal, for receiving the first clock signal CK, a third input terminal, uses
It receives a third clock signal CK/2 and an output end, is opened or closed for control switch SW3.NAND gate 963 has
One first input end, for receiving enable signal EN2, one second input terminal, for receiving clock signal CK, third input
End, for receiving third clock signal CK/2 and an output end, opens or closes for control switch SW4.Wherein, when third
Clock signal CK/2 is produced after clock signal CK frequency elimination.When incoming initial pulse STI comes, top rake unit 900 and top rake
Unit 940 is according to second clock signal and third clock signal CK/2 difference dual numbers scan line group G_even and odd number
Scan line group G_odd starts top rake function.
It on the other hand, can non-sequential start multi-strip scanning line using control second clock signal and third clock signal
Top rake function.Please also refer to Figure 10 A and Figure 10 B, Figure 10 A is the schematic diagram that the embodiment of the present invention one realizes circuit 100,
Figure 10 B is a signal waveforms of Figure 10 A.Realize that circuit 100 is the variation for realizing circuit 90, basic framework and work are former
Reason is identical as circuit 90 is realized, therefore same components are indicated with identical label, and detailed mode of operation is repeated no more in this.Uniquely
The difference is that the timing of a clock signal CKD of timesharing top rake circuit 100.By controlling the timing of clock signal CKD, can control
Start the sequence of even-line interlace line-group group G_even and odd-numbered scan lines group G_odd starting top rake function.For example, when
The boot sequence of scan line group is odd-numbered scan lines group G_odd, even-line interlace line-group group G_even, even-line interlace line-group group
, it can be achieved that scan line g(1 when G_even, odd-numbered scan lines group G_odd, odd-numbered scan lines group G_odd), scan line g(2),
Scan line g(4), scan line g(3), scan line g(5), scan line g(6), scan line g(8), scan line g(7) sequential start top rake
Function.
Please also refer to Figure 11 A and Figure 11 B, Figure 11 A is another schematic diagram for realizing circuit 110 of the embodiment of the present invention,
Figure 11 B is a signal waveforms of Figure 11 A.Realize that circuit 110 includes: a flip-flop 1100；NAND gate 1120,1140 and
1160；Switch SW1, SW2, SW3, SW4, SW5 and SW6；An and impedance component RE.It realizes in circuit 110, multi-strip scanning line
(being not illustrated in Figure 11 A) is divided into a group every three scan lines, therefore can be divided into three group scan line-group groups G_1, G_2 and G_
3.Wherein, scan line group G_1 includes scan line g(1), scan line g(4), scan line g(7) ...；Scan line group G_2 packet
Contain scan line g(2), scan line g(5), scan line g(8) ...；Scan line group G_3 includes scan line g(3), scan line g
(6), scan line g(9) ....Flip-flop 1100 has a first input end, for receiving an incoming initial pulse STI, one second
Input terminal, for receiving an outflow initial pulse STO and an output end, for exporting an enable signal EN.NAND gate 1120
With a first input end, for receiving enable signal EN, one second input terminal, for receiving one first clock signal CK, one
Third input terminal, for receiving a second clock signal CKD(1) and an output end, it is opened for control switch SW1 and SW2
It opens or closes.NAND gate 1140 has a first input end, for receiving enable signal EN, one second input terminal, for receiving
First clock signal CK, a third input terminal, for receiving a third clock signal CKD(2) and an output end, for controlling
Switch SW3 and SW4 are opened or closed.NAND gate 1160 has a first input end, for receiving enable signal EN, one second
Input terminal, for receiving the first clock signal CK, a third input terminal, for receiving one the 4th clock signal CKD(3) and one
Output end opens or closes for control switch SW5 and SW6.Switch SW1, SW2, switch SW3, SW4 and switch SW5 with
And SW6 is respectively coupled to scan line group G_1, scan line group G_2 and scan line group G_3.As incoming initial pulse STI
When coming, utilize different clock signal CKD(1), CKD(2) and CKD(3), respectively to scan line group G_1, G_2 and G_3
Start top rake function.
In conclusion a liquid crystal display multi-strip scanning line can be divided into multiple scannings by the power saving process of the embodiment of the present invention
Line-group group, and top rake function is started to every scan line group respectively in different time point.In this way, which liquid crystal display can divide
Shi Zhihang top rake function, so that scan line group that will not be whole on same time point starts top rake function simultaneously, to reach
The purpose of power saving.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of electricity saving method in a liquid crystal display, the liquid crystal display includes multi-strip scanning line, the power saving
Method includes:
The multi-strip scanning line is divided into multiple scan line groups, wherein at interval of N scan line as a scan line group,
N is greater than or equal to 2；And
In multiple different time points, a top rake function is started to every scan line group in the multiple scan line group respectively
Can, wherein one first scan line group in the multiple scan line group is according to one first timing control signal, one first
Clock signal and a third clock signal start the top rake function and one the by the result that one first logical operation generates
Two scan line groups are according to first timing control signal, a second clock signal and the third clock signal by one
The result that second logical operation generates starts the top rake function.
2. electricity saving method as described in claim 1 also includes to carry out frequency elimination to the third clock signal, described in generating
First clock signal and the second clock signal.
3. electricity saving method as described in claim 1, also comprising closing the top rake function according to one second timing control signal
Energy.
4. a kind of liquid crystal display, includes:
Multiple scan line groups, wherein every scan line group of the multiple scan line group includes multi-strip scanning line,
In at interval of N scan line as a scan line group, N is greater than or equal to 2；And
Multiple timesharing top rake circuits, in multiple different time points to every scan line group in the multiple scan line group
A top rake function is respectively started in group, wherein each timesharing top rake circuit of the multiple timesharing top rake circuit be coupled to it is the multiple
The scan line group of scan line group, each timesharing top rake circuit includes:
One top rake unit, for executing a top rake function；And
One control logic unit is coupled to the top rake unit, for controlling top rake function described in the top rake unit starting, institute
State one first timesharing top rake circuit of multiple timesharing top rake circuits according to one first timing control signal, one first clock signal and
The result that one third clock signal is generated by one first logical operation is to one first scanning in the multiple scan line group
Line-group group starts one second timesharing top rake circuit of the top rake function and the multiple timesharing top rake circuit according to described the
One timing control signal, a second clock signal and the third clock signal by one second logical operation generate as a result,
The top rake function is started to one second scan line group in the multiple scan line group.
5. liquid crystal display as claimed in claim 4, it is characterised in that the control logic unit includes:
One flip-flop includes:
One first input end, for receiving first timing control signal；
One second input terminal, for receiving one second timing control signal；And
One output end, for exporting an enable signal；
One first logic gate includes:
One first input end, for receiving the enable signal；
One second input terminal, for receiving first clock signal；
One third input terminal, for receiving the third clock signal；And
One output end, for exporting one first switch-over control signal；And
One second logic gate includes:
One first input end, for receiving the enable signal；
One second input terminal, for receiving the second clock signal；
One third input terminal, for receiving the third clock signal；And
One output end, for exporting one second switch-over control signal；
Wherein, first switch-over control signal and second switch-over control signal control described in the top rake unit starting
Top rake function.
6. liquid crystal display as claimed in claim 5, it is characterised in that the top rake unit includes:
One first switch, for being opened or closed according to first switch-over control signal；
One second switch, for being opened or closed according to second switch-over control signal；And
One impedance component.
7. liquid crystal display as claimed in claim 5, it is characterised in that the top rake unit includes:
One first switch, for being opened or closed according to first switch-over control signal；
One second switch, for being opened or closed according to second switch-over control signal；And
One current source.
8. liquid crystal display as claimed in claim 5, it is characterised in that the flip-flop be a D-type flip-flop, described first
Logic gate is one and door, and second logic gate is a NAND gate.
9. liquid crystal display as claimed in claim 4, it is characterised in that frequency elimination is carried out to the third clock signal, to generate
First clock signal and the second clock signal.
10. liquid crystal display as claimed in claim 5, it is characterised in that the multiple timesharing top rake circuit is also according to described
Two timing control signals close the top rake function.
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| CN105590610B (en) * | 2016-03-18 | 2019-04-05 | 深圳市华星光电技术有限公司 | Corner cutting circuit in liquid crystal display panel drive system |
| CN109272958A (en) * | 2018-11-09 | 2019-01-25 | 重庆先进光电显示技术研究院 | The driving circuit and its method and display device of display panel |
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