CN101520998A - Picture flicker improvable liquid crystal display device and relevant driving method thereof - Google Patents

Picture flicker improvable liquid crystal display device and relevant driving method thereof Download PDF

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CN101520998A
CN101520998A CN200910132562A CN200910132562A CN101520998A CN 101520998 A CN101520998 A CN 101520998A CN 200910132562 A CN200910132562 A CN 200910132562A CN 200910132562 A CN200910132562 A CN 200910132562A CN 101520998 A CN101520998 A CN 101520998A
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pixel
drive signal
grid
parasitic capacitance
capacitance value
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CN101520998B (en
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徐兆庆
董穆林
陈仁杰
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AU Optronics Corp
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AU Optronics Corp
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Abstract

The invention provides a picture flicker improvable liquid crystal display device and a relevant driving method thereof. The method adjusts the chamfering amplitude of a grid driving signal to reduce the picture flicker and comprises the steps of respectively providing a first grid driving signal and a second grid driving signal according to parasitic capacitance values of a first pixel and a second pixel. The first grid driving signal comprises a waveform descending edge descending from a high potential to a first potential, and the second grid driving signal comprises a waveform descending edge descending from a high potential to a second potential; when the parasitic capacitance value of the first pixel is larger than that of the second pixel, the first potential is lower than the second potential; when the parasitic capacitance value is substantially equal to that of the second pixel, the first potential is substantially equal to the second potential; and when the parasitic capacitance value of the first pixel is less than that of the second pixel, the first potential is higher than the second potential. The invention can effectively eliminate the picture flicker to improve the display quality through adjusting the common voltage.

Description

Can improve the LCD and the drive method thereof of film flicker
Technical field
The present invention relates to a kind of LCD and drive method thereof, relate in particular to a kind of LCD and drive method thereof that improves film flicker.
Background technology
LCD (liquid crystal display, LCD) have low radiation, volume is little and advantage such as low power consuming, replace traditional cathode-ray tube display (cathode ray tube display gradually, CRT), thereby be widely used in notebook computer, personal digital assistant (personal digital assistant, PDA), flat-surface television, or on the information products such as mobile phone.The type of drive of conventional liquid crystal is to utilize source electrode drive circuit (source driver) and gate driver circuit (gate driver) to drive pixel on the panel with display image, because the cost of source electrode drive circuit is than the gate driver circuit height, in order to reduce the use amount of source electrode drive circuit, thereby derive half source electrode drive circuit (half source driver, the HSD) type of drive of pixel shared data line structure.In other words,, the data line of source electrode drive circuit is reduced by half, and the gate line of gate driver circuit is doubled, so can reduce production cost at the pixel of similar number.
Please refer to Fig. 1, Fig. 1 is the synoptic diagram of the liquid crystal indicator 100 of an employing HSD drives structure in the prior art.Liquid crystal indicator 100 comprises a sequential control circuit 130, one source pole driving circuit 110, a gate driver circuit 120, many data line DL 1～DL m, many gate lines G L 1～GL n, and a picture element matrix.Picture element matrix comprises a plurality of pixel cell PX LAnd PX R, each pixel cell comprises a thin film transistor (TFT) (thin film transistor, TFT) switching TFT, a liquid crystal capacitance C LCWith a memory capacitance C ST, be respectively coupled to corresponding data line, corresponding gate line, and a common voltage.Sequential control circuit 130 can produce source electrode drive circuit 110 and required control signal YOE, YV1C, input clock pulse signals CK, CKB or the output enable signal OE etc. of gate driver circuit 120 operations.Source electrode drive circuit 110 can produce the data drive signal SD corresponding to display image 1～SD mIf gate driver circuit 120 is an external drive circuit, then can produce the required gate drive signal SG of turn-on transistor switch according to control signal YOE and YV1C 1～SG n(gate on array, technology GOA) is made, and then can produce the required gate drive signal SG of turn-on transistor switch according to input clock pulse signals CK, CKB and output enable signal OE if gate driver circuit 120 utilizations are integrated in liquid crystal panel 1～SG n
When thin film transistor (TFT) TFT closes, pixel electrode is not connected to any voltage source, but be in unsteady (floating) state, this moment pixel electrode around if any variation in voltage arranged, will be coupled to pixel electrode by its stray capacitance, and change its voltage, so can allow be applied to liquid crystal capacitance C LCWith memory capacitance C STOn the original setting value of voltage deviation.The variation in voltage amount that this kind causes because of stray capacitance is called feed-trough voltage (feed-through voltage), and it is worth V FDCan be expressed as:
V FD＝[C GD/(C LC+C ST+C GD)]*ΔV G
＝K*ΔV G
Wherein, C GDRepresent the grid of thin film transistor switch TFT and the stray capacitance between the drain electrode, K represents C GDAccount for the ratio of all electric capacity sum totals, and Δ V GThen represent gate drive signal when closing thin film transistor switch TFT at pressure reduction that its grid caused.Feed-trough voltage V FDCan cause the situation of film flicker (image flicker), because thin film transistor switch TFT can't exist stray capacitance with avoiding, general type of drive can manage to reduce Δ V GValue, compensate by the common voltage Vcom that adjusts common ends more simultaneously, so could reduce film flicker effectively.
Please refer to Fig. 2 and Fig. 3, Fig. 2 and Fig. 3 are the synoptic diagram of the driving method of prior art liquid crystal indicator 100.Fig. 2 has shown when gate driver circuit 120 is external drive circuit, control signal YOE and gate drive signal SG 1～SG 4Waveform; Fig. 3 has shown when gate driver circuit 120 is made with the GOA technology, clock pulse signal CK, CKB, CK and CKB, output enable signal OE, and gate drive signal SG 1～SG 4Waveform.
In driving method shown in Figure 2, gate drive signal SG 1～SG 4In enable the cycle length decide and gate drive signal SG by the pulse width of control signal YOE 1～SG 4Time span when waveform descends is then decided by the start time point that control signal YOE and YV1C waveform descend.Control signal YOE has the time span of noble potential in each cycle fixes, and control signal YV1C is identical at the waveform decline start time point in each cycle.Therefore, when closing corresponding thin film transistor switch TFT, gate drive signal SG 1～SG 4Be all Δ V at the pressure reduction that its grid caused G'.As previously mentioned, the value of feed-trough voltage is proportional to grid pressure reduction, owing to carry out the Δ V behind the voltage top rake G' Δ V when not carrying out the voltage top rake GTherefore, can reduce the effect of feed-trough voltage.
In driving method shown in Figure 3, clock pulse signal CK and CKB have opposite phase, switch between high electronegative potential with a predetermined period, and this predetermined period then determines gate drive signal SG 1～SG 4In enable the length in cycle.When output enable signal OE had noble potential, gate driver circuit 120 meeting output clock pulse signal CK and CKB were to provide corresponding clock pulse signal O_CK and O_CKB; When output enable signal OE has electronegative potential, gate driver circuit 120 stops output, can carry out electric charge between clock pulse signal O_CK and the O_CKB this moment shares, and then reach the effect of top rake in the waveform drop edge, then provide gate drive signal SG according to clock pulse signal O_CK and O_CKB again 1～SG 4Because having the time span of electronegative potential in each cycle, output enable signal OE is all T, can be to gate drive signal SG 1～SG 4Cause identical top rake amplitude.Therefore, when closing corresponding thin film transistor switch TFT, gate drive signal SG 1～SG 4Be all Δ V at the pressure reduction that its grid caused G'.As previously mentioned, the value of feed-trough voltage is proportional to grid pressure reduction, owing to carry out the Δ V behind the voltage top rake G' Δ V when not carrying out the voltage top rake GTherefore, can reduce the effect of feed-trough voltage.
In the liquid crystal indicator 100 of prior art, the both sides of each bar data line all are provided with pixel, wherein pixel cell PX LThe gate drive signal SG that is located at the data line left side and transmits by odd number bar gate line 1, SG 3..., SG N-1Control, and pixel cell PX RThe gate drive signal SG that is located at the data line right side and transmits by even number bar gate line 2, SG 4..., SG nControl.Two types pixel cell PX LAnd PX RUsually has different designs, its C LC, C ST, C GSOr C GDAlso difference to some extent of value, therefore can produce the feed-trough voltage V of different sizes FDEven two types pixel cell PX LAnd PX RHave same design, also (for example the skew of the first metal layer Metal 1 and the second metal level Metal 2 can cause pixel cell PX because process shifts causes different manifestations easily LAnd PX RDifferent C is arranged GD), still can produce different big or small feed-trough voltage V FD
Reduce the grid cross-pressure at Fig. 2 and prior art driving method shown in Figure 3 with same magnitude, though can reduce the effect of feed-trough voltage, but the feed-trough voltage of each pixel cell is difference to some extent still, therefore can't be effectively by adjusting the situation that common voltage Vcom eliminate film flicker.
Summary of the invention
The object of the present invention is to provide a kind of LCD and drive method thereof that improves film flicker, to overcome the defective of prior art.
The invention provides a kind of LCD of improving film flicker, comprise a first grid polar curve, be used for transmitting a first grid drive signal; One second grid line, adjacent and be parallel to this first grid polar curve, be used for transmitting a second grid drive signal; One data line perpendicular to described first and second gate lines, is used for transmitting data drive signal; One first pixel is located at the confluce of this data line and this first grid polar curve and is positioned at first side of this data line, is used for according to this first grid drive signal and received data drive signal with display frame; One second pixel is located at the confluce of this data line and this second grid line and is positioned at second side of this data line, is used for according to this second grid drive signal and received data drive signal with display frame; One top rake circuit is used for producing a top rake signal according to the parasitic capacitance value of described first and second pixels; An and grid circuit, be used for according to this top rake signal adjust a grid impulse signal in the characteristic of waveform drop edge to produce described first and second gate drive signals, wherein this first grid drive signal comprises the waveform drop edge of reducing to one first current potential from a noble potential, and this second grid drive signal comprises the waveform drop edge of reducing to one second current potential from this noble potential.
The present invention also provides a kind of method that drives LCD, this LCD comprises first pixel that a data line, two adjacent first and second gate lines, are located at the confluce of this data line and this first grid polar curve and are positioned at first side of this data line, and one be located at the confluce of this data line and this second grid line and be positioned at second pixel of second side of this data line, and this method comprises provides a grid impulse signal; Adjust this grid impulse signal to produce a first grid drive signal according to the parasitic capacitance value of this first pixel, wherein this first grid drive signal comprises the waveform drop edge of reducing to one first current potential from a noble potential; Adjust this grid impulse signal to produce a second grid drive signal according to the parasitic capacitance value of this second pixel, wherein this second grid drive signal comprises the waveform drop edge of reducing to one second current potential from this noble potential; And export respectively described first and second gate drive signals to described first and second gate lines to drive described first and second pixels.
The present invention is according to the electric capacity ratio value K of pixel cell 1～K nBut elasticity is adjusted gate drive signal G 1～G nTime span when waveform descends or waveform descending slope.By different pressure differential deltap V G1～Δ V GnCompensate different parasitic capacitance values, make the feed-trough voltage of each type pixel cell have identical value, therefore can improve display quality effectively by adjusting the situation that common voltage Vcom eliminates film flicker.
Description of drawings
Fig. 1 is the synoptic diagram of the liquid crystal indicator of an employing HSD drives structure in the prior art.
Fig. 2 and Fig. 3 are the synoptic diagram of the driving method of prior art liquid crystal indicator.
Fig. 4 and Fig. 5 are for adopting the synoptic diagram of the liquid crystal indicator of HSD drives structure among the present invention.
Fig. 6 is the synoptic diagram of a kind of liquid crystal display apparatus driving circuit in the first embodiment of the invention.
Fig. 7 is the synoptic diagram that can realize the top rake circuit of first embodiment of the invention driving method.
Fig. 8 is the synoptic diagram of a kind of liquid crystal display apparatus driving circuit in the second embodiment of the invention.
Fig. 9 is the synoptic diagram that can realize the top rake circuit of second embodiment of the invention driving method.
Figure 10 is the synoptic diagram that can realize the top rake circuit of third embodiment of the invention driving method.
Wherein, description of reference numerals is as follows:
R1 resistance 74,94 slew rate adjustment circuits
R2 variable resistor 110,210 source electrode drive circuits
C LCLiquid crystal capacitance 130,230 sequential control circuits
C STMemory capacitance QP, QN transistor switch
70 transformer S1, S2 switch
72 electric potential transducer DL 1～D LmData line
240 top rake circuit GL 1～G LnGate line
TFT thin film transistor switch 120,220 gate driver circuits
100,200,300 liquid crystal indicators
PX L, PX R, PX LU, PX LB, PX RU, PX RBPixel cell
YOE、YV1C、CK、CKB、O_CK、
O_CKB、OE、OE TRIM、V TRIM、
SD 1～SD m, SG 1～SG nSignal
Embodiment
Please refer to Fig. 4 and Fig. 5, Fig. 4 and Fig. 5 are respectively the liquid crystal indicator 200 of employing HSD drives structure among the present invention and 300 synoptic diagram. Liquid crystal indicator 200 and 300 respectively comprises one source pole driving circuit 210, a gate driver circuit 220, a sequential control circuit 230, a top rake circuit 240, many data line DL 1～DL m, many gate lines G L 1～GL n, and a picture element matrix.The picture element matrix of liquid crystal indicator 200 comprises a plurality of pixel cell PX LAnd PX R, the picture element matrix of liquid crystal indicator 300 comprises a plurality of pixel cell PX LU, PX LB, PX RUAnd PX RB, and each pixel cell comprises a thin film transistor switch TFT, a liquid crystal capacitance C LCWith a memory capacitance C ST, be respectively coupled to corresponding data line, corresponding gate line, and a common ends.Sequential control circuit 230 can produce source electrode drive circuit 210 and required control signal YOE, YV1C, clock pulse signal CK, CKB or the output enable signal OE etc. of gate driver circuit 220 operations.Source electrode drive circuit 210 can produce the data drive signal SD corresponding to display image 1～SD mIf gate driver circuit 220 is an external drive circuit, top rake circuit 240 can produce a top rake signal V according to the parasitic capacitance value of control signal YV1C and pixel cell TRIM, gate driver circuit 220 is again according to control signal YOE and top rake signal V TRIMProduce the required gate drive signal SG of turn-on transistor switch 1～SG nIf gate driver circuit 220 utilizes the technology of GOA to make, top rake circuit 240 can produce a top rake signal OE according to the parasitic capacitance value of output enable signal OE and pixel cell TRIM, gate driver circuit 220 is again according to clock pulse signal CK, CKB and top rake signal OE TRIMProduce the required gate drive signal SG of turn-on transistor switch 1～SG n
In liquid crystal indicator 200 of the present invention, the both sides of each bar data line are respectively equipped with dissimilar pixel cells, wherein the pixel cell PXL of the first kind gate drive signal SG that is located at data line left side and transmitted by odd number bar gate line 1, SG 3..., SG N-1Control, and the pixel cell PX of second type RThe gate drive signal SG that is located at the data line right side and transmits by even number bar gate line 2, SG 4..., SG nControl (supposing that n is an even number).This pixel cell PX of two types LAnd PX RUsually has different designs, C LC, C ST, C GSOr C GDAlso difference to some extent of value, therefore can produce the feed-trough voltage V of different sizes FDEven two types pixel cell PX LAnd PX RHave same design, also cause the feed-trough voltage V of different sizes easily because of process shifts FD
In liquid crystal indicator 300 of the present invention, the both sides of each bar data line are respectively equipped with dissimilar pixel cells, wherein the pixel cell PX of the first kind LUBe located on the left of the data line and by gate lines G L 1, GL 5..., GL N-3The gate drive signal SG that transmits 1, SG 5..., SG N-3Control the pixel cell PX of second type RBBe located at the data line right side and by gate lines G L 2, GL 6..., GL N-2The gate drive signal SG that transmits 2, SG 6..., SG N-2Control the pixel cell PX of the 3rd type RUBe located at the data line right side and by gate lines G L 3, GL 7..., GL N-1The gate drive signal SG that transmits 3, SG 7..., SG N-1Control, and the pixel cell PX of the 4th type LBBe located on the left of the data line and by gate lines G L 4, GL 8..., G LnThe gate drive signal SG that transmits 4, SG 8..., SG nControl (supposing that n is 4 multiple).This pixel cell PX of four types LU, PX LB, PX RUAnd PX RBUsually has different designs, C LC, C ST, C GSOr C GDAlso difference to some extent of value, therefore can produce the feed-trough voltage V of different sizes FDEven four types pixel cell PX LU, PX LB, PX RUAnd PX RBHas same design, also easily because process shifts causes the feed-trough voltage V of different sizes FD
The present invention uses the gate drive signal SG with top rake waveform drop edge 1～SG nReduce grid pressure reduction, the parasitic capacitance value according to dissimilar pixel cells changes gate drive signal SG simultaneously 1～SG nTop rake amplitude in its waveform drop edge, so when closing corresponding thin film transistor switch TFT, gate drive signal SG 1～SG nCan cause different pressure differential deltap VG at its grid 1～Δ VG nWith liquid crystal indicator 300 is example, and the present invention uses at the different gate drive signal SG of waveform drop edge top rake amplitude 1～SG 4Drive four types pixel cell, therefore when closing corresponding transistor switch, can cause the grid pressure differential deltap VG of different sizes 1～Δ VG 4, to compensate the different electric capacity ratio value K of four types of pixel cells 1～K 4To the influence that feed-trough voltage caused, make the feed-trough voltage V of four types of pixel cells FD1～V FD4Probably identical, so can reduce film flicker effectively by adjusting common voltage Vcom.
Please refer to Fig. 6, Fig. 6 is the driving method of a kind of liquid crystal indicator in the first embodiment of the invention, the liquid crystal indicator 200 or 300 when can be used to drive source electrode drive circuit 310 for external drive circuit.Fig. 4 has shown control signal YOE, YV1C, top rake signal V TRIMAnd gate drive signal SG 1～SG 4Waveform.In driving method shown in Figure 6, control signal YOE has the time span of noble potential in each cycle fixes, its pulse width decision gate drive signal SG 1～SG 4In enable the length in cycle.The control signal YV1C start time point that its waveform descends in each cycle is then different according to the parasitic capacitance value of pixel cell, and gate drive signal SG 1～SG 4The waveform T.T. length T 1～T4 that descends then decide with the YV1C start time point that its waveform descends in the corresponding cycle by control signal YOE.Top rake circuit 340 is at first according to control signal YV1C and electric capacity ratio value K 1～K 4Be created in the different top rake signal V of waveform fall time point in the corresponding cycle TRIMGate driver circuit 320 is again according to control signal YOE and top rake signal V TRIMProduce gate drive signal SG with different top rake amplitudes 1～SG 4, it causes grid pressure differential deltap V respectively when control signal YOE switches to electronegative potential by noble potential G1～Δ V G4The magnitude relationship of supposing the stray capacitance ratio value is K 1＜K 2＜K 3＜K 4, then the waveform of gate drive signal decline T.T. its magnitude relationship of length is T1＜T2＜T3＜T4, so the magnitude relationship of grid pressure reduction is Δ V G1Δ V G2Δ V G3Δ V G4As previously mentioned, the value of feed-trough voltage is proportional to the electric capacity ratio value of pixel cell and the product of grid pressure reduction, at K 1＜K 2＜K 3＜K 4Situation under, the gate drive signal SG of first embodiment of the invention 1～SG 4Provide and have Δ V G1Δ V G2Δ V G3Δ V G4The pressure reduction of magnitude relationship allows the feed-trough voltage of each type pixel cell have identical value, therefore can be effectively by adjusting the situation that common voltage Vcom eliminates film flicker.
Please refer to Fig. 7, the schematic view illustrating of Fig. 7 can realize the top rake circuit 340 of the driving method of first embodiment of the invention.The top rake circuit 340 of Fig. 7 comprises a transformer (inverter) 70, an electric potential transducer (level shifter) 72, one slew rate adjustment circuit 74, and transistor switch QP and QN, can produce top rake signal V according to control signal YV1C TRIMWhen control signal YV1C had noble potential, transistor switch QP was conducting and transistor switch QN is and closes, this moment top rake signal V TRIMHas noble potential VGH; When control signal YV1C had electronegative potential, transistor switch QP was and closes and transistor switch QN is conducting, this moment top rake signal V TRIMCurrent potential can be pulled to electronegative potential by the resistance R in the slew rate adjustment circuit 74 1.Therefore, in the embodiment of Fig. 6 and Fig. 7, the control signal YV1C with different waveform decline start time point, the top rake signal V that provides the waveform drop edge to have a slope by slew rate adjustment circuit 74 again are provided top rake circuit 340 TRIM, wherein slew rate adjustment circuit 74 can be impedor, for example resistance or variable resistor.
Please refer to Fig. 8, Fig. 8 is the driving method of a kind of liquid crystal indicator in the second embodiment of the invention, the liquid crystal indicator 200 or 300 when can be used to drive source electrode drive circuit 310 for external drive circuit.Fig. 6 has shown control signal YOE, YV1C, top rake signal V TRIMWith gate drive signal SG 1～SG 4Waveform.In driving method shown in Figure 8, control signal YOE has the time span of noble potential in each cycle fixes, its pulse width decision gate drive signal SG 1～SG 4In enable the length in cycle.The waveform decline start time point of control signal YV1C is identical, so gate drive signal SG 1～SG 4Waveform fall time length be all T, and gate drive signal SG 1～SG 4Waveform descending slope m 1～m 4Then control by top rake circuit 340.Top rake circuit 340 is at first according to control signal YV1C and electric capacity ratio value K 1～K 4Produce the different top rake signal V of waveform descending slope TRIMGate driver circuit 320 is again according to control signal YOE and top rake signal V TRIMProduce gate drive signal SG with different top rake amplitudes 1～SG 4, it causes grid pressure differential deltap V respectively when control signal YOE switches to electronegative potential by noble potential G1～Δ V G4The magnitude relationship of supposing parasitic capacitance value is K 1＜K 2＜K 3＜K 4, then the magnitude relationship of gate drive signal waveform descending slope is m 1＜m 2＜m 3＜m 4, so the magnitude relationship of grid pressure reduction is Δ V G1Δ V G2Δ V G3Δ V G4As previously mentioned, the value of feed-trough voltage is proportional to the stray capacitance of pixel cell and the product of grid pressure reduction, at K 1＜K 2＜K 3＜K 4Situation under, the gate drive signal SG of second embodiment of the invention 1～SG 4Provide and have Δ V G1Δ V G2Δ V G3Δ V G4The pressure reduction of magnitude relationship allows the feed-trough voltage of each type pixel cell have identical value, therefore can be effectively by adjusting the situation that common voltage Vcom eliminates film flicker.
Please refer to Fig. 9, the schematic view illustrating of Fig. 9 can realize the top rake circuit 340 of the driving method of second embodiment of the invention.The top rake circuit 340 of Fig. 9 comprises transformer 70, electric potential transducer 72, a slew rate adjustment circuit 94, and transistor switch QP and QN, can produce top rake signal V according to control signal YV1C TRIMWhen control signal YV1C had noble potential, transistor switch QP was conducting and transistor switch QN is and closes, this moment top rake signal V TRIMHas noble potential VGH; When control signal YV1C had electronegative potential, transistor switch QP was and closes and transistor switch QN is conducting, this moment top rake signal V TRIMCurrent potential can be pulled to electronegative potential by slew rate adjustment circuit 94.Slew rate adjustment circuit 94 comprises a resistance R 1, a variable resistor R2, and switch S 1 and S2, therefore can be according to parasitic capacitance value K 1～K 4Different equivalent resistance is provided, makes slew rate adjustment circuit 94 can drag down the top rake signal with suitable slope VTRIMCurrent potential.Therefore, in the embodiment of Fig. 8 and Fig. 9, the control signal YV1C with same waveform as decline start time point, the top rake signal V that provides the waveform drop edge to have Different Slope by slew rate adjustment circuit 94 again are provided top rake circuit 340 TRIM
Please refer to Figure 10, Figure 10 is the driving method of a kind of liquid crystal indicator in the third embodiment of the invention, the liquid crystal indicator 200 or 300 when can be used to drive source electrode drive circuit 310 and adopting the GOA technology to make.Figure 10 has shown clock pulse signal CK, CKB, O_CK and O_CKB, output enable signal OE, and gate drive signal SG 1～SG 4Waveform.In driving method shown in Figure 8, the clock pulse signal CK and the CKB that are produced by sequential control circuit 230 have opposite phase, and switch between high electronegative potential with a predetermined period, and this predetermined period decision gate drive signal SG 1～SG 4In enable the length in cycle.Top rake circuit 340 is at first according to output enable signal OE and parasitic capacitance value K 1～K 4Produce the decapacitation time the different top rake signal OE of (having electronegative potential) length T 1～T4 TRIMAs top rake signal OE TRIMWhen having noble potential, gate driver circuit 220 meeting output clock pulse signal CK and CKB are to provide corresponding clock pulse signal O_CK and O_CKB; As top rake signal OE TRIMWhen having electronegative potential, gate driver circuit 220 stops output, can carry out electric charge between clock pulse signal O_CK and the O_CKB this moment and share, and then reach the effect of top rake in the waveform drop edge.Gate driver circuit 320 produces the gate drive signal SG with different top rake amplitudes according to clock pulse signal O_CK and O_CKB again 1～SG 4, cause grid pressure differential deltap V when between high electronegative potential, switching respectively at corresponding clock pulse signal CK and CKB G1～Δ V G4Suppose stray capacitance C GDThe magnitude relationship that accounts for the total capacitance value ratio is K 1＜K 2＜K 3＜K 4, top rake signal OE then TRIMThe magnitude relationship of decapacitation time span is T1＜T2＜T3＜T4, so grid pressure differential deltap V G1Δ V G2Δ V G3Δ V G4As previously mentioned, the value of feed-trough voltage is proportional to the stray capacitance of pixel cell and the product of grid pressure reduction, at K 1＜K 2＜K 3＜K 4Situation under, the gate drive signal SG of third embodiment of the invention 1～SG 4Provide and have Δ V G1Δ V G2Δ V G3Δ V G4The pressure reduction of magnitude relationship allows the feed-trough voltage of each type pixel cell have identical value, therefore can be effectively by adjusting the situation that common voltage Vcom eliminates film flicker.
Electric capacity ratio value K according to pixel cell 1～K nBut the present invention's elasticity is adjusted gate drive signal G 1～G nTime span when waveform descends or waveform descending slope.By different pressure differential deltap V G1～Δ V GnCompensate different parasitic capacitance values, make the feed-trough voltage of each type pixel cell have identical value, therefore can improve display quality effectively by adjusting the situation that common voltage Vcom eliminates film flicker.
The above only is the preferred embodiments of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong in protection scope of the present invention.

Claims (25)

1. the LCD that can improve film flicker comprises:
One first grid polar curve is used for transmitting a first grid drive signal;
One second grid line, adjacent and be parallel to this first grid polar curve, be used for transmitting a second grid drive signal;
One data line perpendicular to described first and second gate lines, is used for transmitting data drive signal;
One first pixel is located at the confluce of this data line and this first grid polar curve and is positioned at first side of this data line, is used for according to this first grid drive signal and received data drive signal with display frame;
One second pixel is located at the confluce of this data line and this second grid line and is positioned at second side of this data line, is used for according to this second grid drive signal and received data drive signal with display frame;
One top rake circuit is used for producing a top rake signal according to the parasitic capacitance value of described first and second pixels; And
One grid circuit, be used for according to this top rake signal adjust a grid impulse signal in the characteristic of waveform drop edge to produce described first and second gate drive signals, wherein this first grid drive signal comprises the waveform drop edge of reducing to one first current potential from a noble potential, and this second grid drive signal comprises the waveform drop edge of reducing to one second current potential from this noble potential.
2. LCD as claimed in claim 1, wherein:
This first pixel comprises:
One first switch comprises:
One first end is coupled to this data line;
One second end; And
One control end is coupled to this first grid polar curve;
One first liquid crystal capacitance is coupled between second end and a common ends of this first switch; And
One first memory capacitance is parallel to this first liquid crystal capacitance; And
This second pixel comprises:
One second switch comprises:
One first end is coupled to this data line;
One second end; And
One control end is coupled to this second grid line;
One second liquid crystal capacitance is coupled between second end and this common ends of this second switch; And
One second memory capacitance is parallel to this second liquid crystal capacitance.
3. LCD as claimed in claim 2, wherein said first and second switches comprise thin film transistor (TFT), and the parasitic capacitance value of described a plurality of pixels is the gate-to-drain electric capacity of described a plurality of thin film transistor (TFT)s.
4. LCD as claimed in claim 1, wherein this first current potential is greater than this second current potential.
5. LCD as claimed in claim 1 also comprises:
One the 3rd gate line, adjacent and be parallel to this second grid line, be used for transmitting one the 3rd gate drive signal;
One the 4th gate line, adjacent and be parallel to the 3rd gate line, be used for transmitting one the 4th gate drive signal;
One the 3rd pixel is located at the confluce of this data line and the 3rd gate line and is positioned at first side of this data line, is used for according to the 3rd gate drive signal and received data drive signal with display frame; And
One the 4th pixel is located at the confluce of this data line and the 4th gate line and is positioned at second side of this data line, is used for according to the 4th gate drive signal and received data drive signal with display frame;
Wherein this top rake circuit also produces this top rake signal according to the parasitic capacitance value of described third and fourth pixel, and this grid circuit also according to this top rake signal adjust this grid impulse signal in the characteristic of waveform drop edge to produce described third and fourth gate drive signal, wherein the 3rd gate drive signal comprises the waveform drop edge of reducing to one the 3rd current potential from this noble potential, and the 4th gate drive signal comprises the waveform drop edge of reducing to one the 4th current potential from this noble potential.
6. LCD as claimed in claim 5, wherein:
The 3rd pixel comprises:
One the 3rd switch comprises:
One first end is coupled to this data line;
One second end; And
One control end is coupled to the 3rd gate line;
One the 3rd liquid crystal capacitance is coupled between second end and a common ends of the 3rd switch; And
One the 3rd memory capacitance is parallel to the 3rd liquid crystal capacitance; And
The 4th pixel comprises:
One the 4th switch comprises:
One first end is coupled to this data line;
One second end; And
One control end is coupled to the 4th gate line;
One the 4th liquid crystal capacitance is coupled between second end and this common ends of the 4th switch; And
One the 4th memory capacitance is parallel to the 4th liquid crystal capacitance.
7. LCD as claimed in claim 6, wherein said third and fourth switch comprises thin film transistor (TFT), and the parasitic capacitance value of described a plurality of pixels is the gate-to-drain electric capacity of described a plurality of thin film transistor (TFT)s.
8. LCD as claimed in claim 7, wherein the 3rd current potential is greater than the 4th current potential.
9. LCD as claimed in claim 5, the wherein said first and the 3rd current potential is equal in fact, and the described second and the 4th current potential is equal in fact.
10. LCD as claimed in claim 1 also comprises:
One the 3rd gate line, adjacent and be parallel to this second grid line, be used for transmitting one the 3rd gate drive signal;
One the 4th gate line, adjacent and be parallel to the 3rd gate line, be used for transmitting one the 4th gate drive signal;
One the 3rd pixel is located at the confluce of this data line and the 3rd gate line and is positioned at second side of this data line, is used for according to the 3rd gate drive signal and received data drive signal with display frame; And
One the 4th pixel is located at the confluce of this data line and the 4th gate line and is positioned at first side of this data line, is used for according to the 4th gate drive signal and received data drive signal with display frame;
Wherein this top rake circuit also produces this top rake signal according to the parasitic capacitance value of described third and fourth pixel, and this grid circuit also according to this top rake signal adjust this grid impulse signal in the characteristic of waveform drop edge to produce described third and fourth gate drive signal, wherein the 3rd gate drive signal comprises the waveform drop edge of reducing to one the 3rd current potential from this noble potential, and the 4th gate drive signal comprises the waveform drop edge of reducing to one the 4th current potential from this noble potential.
11. LCD as claimed in claim 10, wherein:
The 3rd pixel comprises:
One the 3rd switch comprises:
One first end is coupled to this data line;
One second end; And
One control end is coupled to the 3rd gate line;
One the 3rd liquid crystal capacitance is coupled between second end and a common ends of the 3rd switch; And
One the 3rd memory capacitance is parallel to the 3rd liquid crystal capacitance; And
The 4th pixel comprises:
One the 4th switch comprises:
One first end is coupled to this data line;
One second end; And
One control end is coupled to the 4th gate line;
One the 4th liquid crystal capacitance is coupled between second end and this common ends of the 4th switch; And
One the 4th memory capacitance is parallel to the 4th liquid crystal capacitance.
12. LCD as claimed in claim 11, wherein said third and fourth switch comprises thin film transistor (TFT), and the parasitic capacitance value of described a plurality of pixels is the gate-to-drain electric capacity of described a plurality of thin film transistor (TFT)s.
13. LCD as claimed in claim 10, wherein this first to the 4th current potential is different each other.
14. LCD as claimed in claim 1, wherein this top rake circuit comprises:
One switch is used for controlling the start time point of this top rake signal its waveform drop edge in different cycles.
15. LCD as claimed in claim 1, wherein this top rake circuit comprises:
One resistance, the slope when being used for controlling this top rake signal its waveform descending in different cycles.
16. LCD as claimed in claim 1, wherein this top rake circuit and this grid circuit are made with the integrated circuit technique that is integrated in panel.
17. LCD as claimed in claim 1 also comprises:
One sequential control circuit is used to provide this grid impulse signal.
18. method that drives LCD, this LCD comprises first pixel that a data line, two adjacent first and second gate lines, are located at the confluce of this data line and this first grid polar curve and are positioned at first side of this data line, and one be located at the confluce of this data line and this second grid line and be positioned at second pixel of second side of this data line, and this method comprises:
One grid impulse signal is provided;
Adjust this grid impulse signal to produce a first grid drive signal according to the parasitic capacitance value of this first pixel, wherein this first grid drive signal comprises the waveform drop edge of reducing to one first current potential from a noble potential;
Adjust this grid impulse signal to produce a second grid drive signal according to the parasitic capacitance value of this second pixel, wherein this second grid drive signal comprises the waveform drop edge of reducing to one second current potential from this noble potential; And
Export respectively described first and second gate drive signals to described first and second gate lines to drive described first and second pixels.
19. method as claimed in claim 18, wherein:
When the parasitic capacitance value of this first pixel during greater than the parasitic capacitance value of this second pixel, this first current potential is lower than this second current potential;
When the parasitic capacitance value of this first pixel equaled the parasitic capacitance value of this second pixel in fact, this first current potential equaled this second current potential in fact; And
When the parasitic capacitance value of this first pixel during less than the parasitic capacitance value of this second pixel, this first current potential is higher than this second current potential.
20. method as claimed in claim 18, wherein:
Producing this first grid drive signal comprises this first grid drive signal is descended a very first time length to reach this first current potential from this noble potential; And
Producing this second grid drive signal comprises this second grid drive signal is descended one second time span to reach this second current potential from this noble potential.
21. method as claimed in claim 20, wherein:
When the parasitic capacitance value of this first pixel during greater than the parasitic capacitance value of this second pixel, this very first time length is greater than this second time span;
When the parasitic capacitance value of this first pixel equaled the parasitic capacitance value of this second pixel in fact, this very first time length equaled this second time span in fact; And
When the parasitic capacitance value of this first pixel during less than the parasitic capacitance value of this second pixel, this very first time length is less than this second time span.
22. method as claimed in claim 18, wherein:
Producing this first grid drive signal comprises this first grid drive signal is descended to reach this first current potential with one first slope from this noble potential; And
Producing this second grid drive signal comprises this second grid drive signal is descended to reach this second current potential with one second slope from this noble potential.
23. method as claimed in claim 22, wherein:
When the parasitic capacitance value of this first pixel during greater than the parasitic capacitance value of this second pixel, this first slope is greater than this second slope;
When the parasitic capacitance value of this first pixel equaled the parasitic capacitance value of this second pixel in fact, this first slope equaled this second slope in fact; And
When the parasitic capacitance value of this first pixel during less than the parasitic capacitance value of this second pixel this first slope less than this second slope.
24. method as claimed in claim 18 also comprises:
One first clock pulse signal and a second clock pulse signal are provided, and the polarity of wherein said first and second clock pulse signals is reversed with a predetermined period, and described at one time first and second clock pulse signals have opposite polarity;
Parasitic capacitance value according to this first pixel decides a very first time length;
Parasitic capacitance value according to this second pixel decides one second time span;
In cycle, in this very first time length, described first and second clock pulse signals are carried out electric charge and share corresponding to this first pixel;
In cycle, in this second time span, described first and second clock pulse signals are carried out electric charge and share corresponding to this second pixel; And
According to carry out described first or second clock pulse signal after electric charge is shared adjust this grid impulse signal with produce this first or this second grid drive signal.
25. method as claimed in claim 24, wherein:
When the parasitic capacitance value of this first pixel during greater than the parasitic capacitance value of this second pixel, this very first time length is greater than this second time span;
When the parasitic capacitance value of this first pixel equaled the parasitic capacitance value of this second pixel in fact, this very first time length equaled this second time span in fact; And
When the parasitic capacitance value of this first pixel during less than the parasitic capacitance value of this second pixel, this very first time length is less than this second time span.
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CN110992906A (en) * 2019-11-18 2020-04-10 福建华佳彩有限公司 Drive method of Demux circuit
CN111681582A (en) * 2020-06-02 2020-09-18 Tcl华星光电技术有限公司 Scanning driving method, scanning driving device, electronic apparatus, and storage medium
US11705033B2 (en) 2020-06-02 2023-07-18 Tcl China Star Optoelectronics Technology Co., Ltd. Scanning driving method, scanning driving device, electronic equipment, and storage medium
CN113870806A (en) * 2020-06-30 2021-12-31 晶门科技（中国）有限公司 Compensation system and method for dual gate display
CN113870806B (en) * 2020-06-30 2023-10-10 晶门科技（中国）有限公司 Compensation system and method for dual gate display

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