CN113870806A

CN113870806A - Compensation system and method for dual gate display

Info

Publication number: CN113870806A
Application number: CN202010618439.6A
Authority: CN
Inventors: 庄振荣; 梁佑玮; 黄伟特; 赵崇劭
Original assignee: Solomon Systech Shenzhen Ltd
Current assignee: Solomon Systech Shenzhen Ltd
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2021-12-31
Anticipated expiration: 2040-06-30
Also published as: TWI799858B; CN113870806B; TW202203195A

Abstract

A driving system and method for a dual gate display includes a source driver and two array substrate gate drivers (GOAs) configured to drive odd and even gate lines, respectively. One of the odd-numbered gate lines and an adjacent one of the even-numbered gate lines are connected to gate electrodes of thin film transistors of the same row of pixel cells from different directions, so that adjacent pixel cells have different feed-through voltages. At least one of the two array substrate gate drivers includes a gate driving circuit configured to generate a plurality of gate control signals to the gate lines, each of the gate control signals having an alternating waveform of alternating high and low levels, and a compensation system. The compensation system adjusts the VGH voltage level, thereby adjusting the high level of the gate control signal to compensate for the different feed-through voltages driving the neighboring pixel cells.

Description

Compensation system and method for dual gate display

Technical Field

The present invention relates generally to compensation systems and methods for dual gate displays, and more particularly to methods and systems for applying VGH voltage compensation or gamma (gamma) curve compensation in integrated circuits to improve or resolve vertical line symptoms common in dual gate displays.

Background

In a conventional active matrix liquid crystal display, the display is driven by a single gate driver and a source driver. In the single gate circuit architecture, a gate driver controls a plurality of gate lines (also referred to as scan lines), each pixel has a thin film transistor whose gate electrode is connected to the gate line in the horizontal direction, whose source electrode is connected to the source line in the vertical direction, whose drain electrode is connected to one end of a liquid crystal capacitor (Clc) and a storage capacitor (Cs) of each pixel, and whose other end is connected to a common electrode (VCOM).

In the horizontal direction, the gate electrodes of all the tfts are connected together, and when the gate driver outputs a high voltage signal to one of the gate lines, all the tfts on the gate line are turned on, so that the pixels on the gate line receive display signals from the source lines in each vertical direction in time sequence.

In order to reduce the production cost of the liquid crystal display, the pixel structure of the liquid crystal display adopts a dual-gate structure. In the dual-gate structure, the signals output from the same source line can drive the odd and even two adjacent pixels in the same row, so that half of the number of sources can be saved but the number of gates must be doubled, and the effect of reducing the cost can be achieved for the traditional liquid crystal display with the number of sources larger than the number of gates.

Since the liquid crystal should balance the positive voltage and the negative voltage alternately, ideally, the VCOM electrode should be the GND level to balance the display voltages of the positive gamma and the negative gamma. In practice, however, the gate drive voltage causes a feedthrough voltage when turned off. Therefore, voltage offsets exist for the VCOM electrode, the positive gamma and the negative gamma, which is called feed-through voltage. The transistors on the tft panel are made of amorphous silicon or metal oxide, which is relatively coarse, and the position of the tft in the display also affects the feedthrough effect. In the dual gate display, two adjacent pixels are driven by the same source line and two different gate lines, and the feed-through voltages of the two gate lines are different, so that the odd and even pixels need two different VCOMs for compensation. If there is only one VCOM, vertical line symptoms are often seen in the display.

Accordingly, there is a need in the art for a compensation method and system that improves or addresses the vertical line symptoms common in dual gate displays by employing voltage compensation or gamma curve compensation in the integrated circuit. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.

Disclosure of Invention

Compensation systems and methods for dual gate displays are provided. The present invention is directed to a compensation method and system capable of improving or solving the vertical line symptoms commonly seen in a dual gate display by voltage compensation or gamma curve compensation.

According to some embodiments of the present invention, a driving system for a dual gate display is disclosed. The dual gate display includes a plurality of pixel cells arranged in rows and columns, each pixel cell including a display electrode capacitance and a thin film transistor. The display electrode capacitor includes a first terminal coupled to the drain electrode of the thin film transistor and a second terminal coupled to the common electrode. The driving system comprises a source driver, a first array substrate gate driver and a second array substrate gate driver. The first array substrate gate driver is configured to drive odd-numbered gate lines, and the second array substrate gate driver is configured to drive even-numbered gate lines. Wherein one odd-numbered gate line and an adjacent even-numbered gate line are connected to gate electrodes of thin film transistors of the same row of pixel cells from different directions, so that the adjacent pixel cells have different feed-through voltages. The first array substrate gate driver and the second array substrate gate driver each include a gate driving circuit configured to generate a plurality of gate control signals to the gate lines, each gate control signal having an alternating waveform of alternating high and low levels, wherein at least one of the first array substrate gate driver and the second array substrate gate driver further includes a compensation system that generates a compensation voltage for adjusting a voltage level of the high level of the gate control signal to compensate for different feedthrough voltages driving adjacent pixel cells.

Preferably, the compensation system further includes a smoothing capacitor connected from the VGH voltage to the compensation voltage, which may be selected between Δ V1 and the ground voltage, so that the high level is VGH or VGH + Δv 1. Wherein the compensation voltage can be connected to Δ V1 through a first switch or to a ground voltage through a second switch.

Preferably, the capacitance range of the smoothing capacitor is between 0.1uF and 10 uF.

Preferably, the compensation system further includes another smoothing capacitor connected from the VGL voltage to the compensation voltage, which may be selected between Δ V2 and the ground voltage, so that the low level is VGL or VGL + Δ V2. Wherein the compensation voltage can be connected to Δ V2 through a first switch or to a ground voltage through a second switch.

Preferably, the capacitance of the further smoothing capacitor ranges between 0.1uF and 10 uF.

According to some embodiments of the present invention, a driving system for a dual gate display is disclosed, the dual gate display comprising a plurality of pixel cells arranged in rows and columns, each pixel cell comprising a display electrode capacitance and a thin film transistor. The display electrode capacitor includes a first terminal coupled to the drain electrode of the thin film transistor and a second terminal coupled to the common electrode. The driving system comprises a source driver, a first array substrate gate driver and a second array substrate gate driver. The source driver includes a gamma generator and a source driving circuit. The source driving circuit is configured to generate a plurality of source control signals to source lines, each of the source lines being connected to source electrodes of thin film transistors of a same column of pixel cells, each of the source control signals having an alternating waveform in which a VCOMH level, a VCOML level, and a common electrode alternate. The first array substrate gate driver and the second array substrate gate driver are configured to drive odd-numbered and even-numbered gate lines, respectively. The gamma generator is configured to drive a positive gamma curve, a negative gamma curve, a positive gamma curve with compensation, and a negative gamma curve with compensation. The positive gamma curve and the negative gamma curve drive a column of pixel units, and the positive gamma curve with compensation and the negative gamma curve with compensation drive a column of pixel units adjacent to the column of pixel units.

Preferably, the gamma generator further comprises four sets of gamma register settings respectively defining a positive gamma curve, a negative gamma curve, a positive gamma curve with compensation and a negative gamma curve with compensation.

Preferably, four sets of gamma register settings are independently set based on the characteristics of the display to compensate for color and brightness deviations of the pixel cells of the column and the adjacent column.

Preferably, the positive gamma curve with compensation is a voltage offset for each gray level of the positive gamma curve.

Preferably, the negative gamma curve with compensation is a voltage offset for each gray level of the negative gamma curve.

Preferably, the source driver further comprises a VCOM generator, wherein the common electrode driven by the VCOM generator is static.

According to some embodiments of the present invention, a method is disclosed for a dual gate display comprising a plurality of pixel cells arranged in rows and columns, each pixel cell comprising a display electrode capacitance and a thin film transistor. The display electrode capacitor includes a first terminal coupled to the drain electrode of the thin film transistor and a second terminal coupled to the common electrode. The driving system comprises a source driver, a first array substrate gate driver and a second array substrate gate driver. The method comprises the following steps: the source driver generates a gate driving control signal, a VGH voltage and a VGL voltage which are coupled to the two array substrate gate drivers; adjusting the VGH voltage level received by at least one array substrate gate driver; driving odd-numbered gate lines by a first array substrate gate driver of the two array substrate gate drivers; and driving even number of gate lines by a second array substrate gate driver of the two array substrate gate drivers. The high level of the grid control signal generated by the grid driver of the array substrate is adjusted to compensate for different feed-through voltages for driving adjacent pixel units by adjusting the received VGH voltage level.

Preferably, adjusting the VGH voltage level received by at least one of the array substrate gate drivers includes connecting the received VGH voltage to a compensation voltage through a smoothing capacitor, and the compensation voltage may be selected between Δ V1 and a ground voltage, so that the high level is VGH or VGH +. Δ V1.

Preferably, the compensation voltage may be connected to Δ V1 through a first switch or to a ground voltage through a second switch.

Preferably, the method further includes adjusting a VGL voltage level received by at least one of the array substrate gate drivers, and adjusting a low level of a gate control signal generated by the array substrate gate driver to compensate for a different feedthrough voltage driving an adjacent pixel cell by adjusting the received VGL voltage level.

Preferably, the adjusting the VGL voltage level received by the gate driver of at least one of the array substrates further comprises connecting the received VGL voltage to a compensation voltage through a smoothing capacitor, and the compensation voltage can be selected between Δ V2 and a ground voltage, so that the low level is VGL or VGL + Δ V2.

Preferably, the compensation voltage may be connected to Δ V2 through a first switch or to a ground voltage through a second switch.

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. Other aspects and advantages of the invention are disclosed as shown in the examples below.

Drawings

The accompanying drawings contain drawings that further illustrate and explain the above and other aspects, advantages, and features of the present invention. It is appreciated that these drawings depict only certain embodiments of the invention and are not intended to limit its scope. It will be further appreciated that the drawings are for simplicity and clarity and have not necessarily been drawn to scale. The invention will now be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

FIG. 1 depicts a schematic diagram of a dual gate display and corresponding drive circuitry;

FIG. 2 depicts signal diagrams of source line and gate line signals and VGH related voltage compensation in accordance with a first embodiment of the present invention;

FIG. 3 depicts a schematic diagram of an array substrate gate driver circuit according to a first embodiment of the invention;

fig. 4 depicts a block diagram of the structure of a source driver according to a second embodiment of the present invention;

FIG. 5A is a positive gamma curve according to a second embodiment of the present invention;

FIG. 5B is a positive gamma curve with compensation according to a second embodiment of the present invention;

FIG. 6A is a negative gamma curve according to a second embodiment of the present invention; and

fig. 6B is a negative gamma curve with compensation according to a second embodiment of the present invention.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

Detailed Description

The present invention generally relates to compensation systems and methods for dual gate displays. More particularly, but not by way of limitation, the present invention provides a compensation method and system in an integrated circuit that can ameliorate or solve vertical line symptoms common in dual gate displays through voltage compensation or gamma curve compensation.

The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and/or uses of the invention. It will be appreciated that a vast number of variations exist. The detailed description will enable those skilled in the art to practice exemplary embodiments of the invention without undue experimentation, and it should be understood that various changes or modifications in the function and arrangement described in the exemplary embodiments may be made without departing from the scope of the invention as set forth in the appended claims.

The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.

Unless otherwise defined, all terms (including technical and scientific terms) used in the examples of the present invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. As used herein, the terms "gate electrode", "source electrode" and "drain electrode" collectively define three terminals of a Thin Film Transistor (TFT) in each pixel cell, the TFT having an active channel region that can be controlled by a gate electrode for electrically connecting the source and drain electrodes.

As used herein, "GND" refers to the ground voltage to which other voltage levels are referenced, which is assigned to a voltage of 0V in many circuit designs. "VCOM" refers to the common electrode of a liquid crystal display, and is usually adjusted according to the panel characteristics for the purpose of eliminating flicker from the liquid crystal display panel. The "VGH" voltage refers to a voltage that turns on the thin film transistors of the liquid crystal display panel, and the "VGL" voltage refers to another voltage that turns off the thin film transistors of the liquid crystal display panel.

The present invention relates to driving a dual gate display comprising a plurality of pixel cells 30 arranged in rows and columns, each pixel cell 30 comprising a display electrode capacitance 33 and a Thin Film Transistor (TFT)31, as shown in figure 1. The display electrode capacitance 33 comprises a first terminal and a second terminal, the first terminal of the display electrode capacitance 33 is coupled to the drain electrode of the thin film transistor 31, the second terminal of the display electrode capacitance 33 is coupled to the common electrode (VCOM)32, wherein the display electrode capacitance 33 comprises a liquid crystal capacitance (Clc), a parasitic capacitor (Cgd) and a storage capacitance (Cs). As shown in FIG. 1, the odd and even pixel cells 30 in the same row of the dual gate display are driven by

different gate lines

21, 22 although they are at the same level, the source driver 10 is configured to drive a plurality of source lines 11 (S1-S M), each source line 11 is connected to the source electrode of the thin film transistor 31 of the same column of pixel cells 30 for providing data to the pixel cells 30. The Gate lines 21, 22 (G1 to G N) are driven by two Array substrate Gate drivers 20(Gate On Array, GOA) for driving the Gate electrodes of the TFTs 31 of the 30 units, and all the Gate lines 21, 22 are scanned in one frame. The term "array substrate gate driver" is a technology: the circuit of the gate switch is integrated on the array substrate to replace the part of the gate drive integrated circuit. The two array substrate gate drivers 20 are respectively located at two sides of the liquid crystal display. The first array substrate gate driver 20 is configured to drive odd-numbered gate lines 21 (G1, G3 … G N-1). The second array substrate gate driver 20 is configured to drive even-numbered gate lines 22 (G2, G4 … G N), wherein one odd-numbered gate line (e.g., G1) and an adjacent even-numbered gate line (e.g., G2) are connected to different gate electrodes of the thin film transistors 31 of the same row of pixel cells 30.

The source driver 10 is connected to the first array substrate gate driver 20 and the second array substrate gate driver 20, wherein the source driver 10 is configured to generate gate driving control signals (GOUT _ L, GOUT _ R)12, 13, a VGH voltage 110, and a VGL voltage 140, so as to synchronize the source driver 10 and the array substrate gate driver 20 and provide gate high and low level inputs. The source driver 10 may also include other circuit blocks for receiving and processing image or video data for display purposes, and in one embodiment, the source driver 10 or any portion thereof may be contained in a Microcontroller (MCU), a custom integrated circuit, a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), other semiconductor device, or a combination of any of the foregoing. Those skilled in the art will readily appreciate that the circuitry of the source driver 10 may be formed, at least in part, by logic gates, analog circuit blocks, transistors, semiconductor devices, discrete components, other electronic devices, or a combination of any of the foregoing circuit configurations. Other circuit blocks or touch sensing systems for driving and updating the liquid crystal display may also be included in the source driver 10 (not shown in fig. 1).

The first group of gate driving control signals (GOUT _ L)12 is connected to the first array substrate gate driver 20, and generates pulse signals to the odd-numbered gate lines 21 in time sequence. The second group of gate driving control signals (GOUT _ R)13 is connected to the second array substrate gate driver 20, and generates pulse signals to the even-numbered gate lines 22 at a timing.

In a dual gate display, the pixel cells 30 in the same row are driven by two

gate lines

21, 22. in the illustrated embodiment, the source line S1 … … SM is coupled to the source electrodes of the first and second TFTs 31, the gate electrode of the first TFT 31 is driven by the odd-numbered gate lines G1, G3 … …, and the gate electrode of the second TFT 31 is driven by the even-numbered gate lines G2, G4 … …, wherein the odd-numbered gate lines G1, G3 … … and the even-numbered gate lines G2, G4 … … are driven by two different array substrate gate drivers 20, respectively, the odd-numbered gate lines G1, G3 … … are above the pixel cells 30, and the even-numbered gate lines G2, G4 … … are below the pixel cells 30, therefore, the physical directions of the odd and even pixel cells 30 in the same row are reversed.

It can be known from the prior art that the tft on the tft panel is relatively coarse, and the position and physical direction of the tft will affect the feed-through effect in the dual gate driving mode. Among them, the most influential is the feedthrough voltage generated via the parasitic capacitor (Cgd). Since the common electrode (VCOM) is driven by a dc voltage, the feed-through voltage across Cgd is:

VGH and VGL are voltages at the time of turning on and off when the gate lines are driven, Cgd is a parasitic capacitance of the thin film transistor, Clc is a liquid crystal capacitance of the thin film transistor, and Cs is a storage capacitance of the thin film transistor, respectively.

Accordingly, in the dual gate display, since the two array substrate gate drivers 20 drive two adjacent pixel units 30 from different directions through two

different gate lines

21 and 22, even if the two pixel units 30 are adjacent, the silicon device parameters inevitably vary, so that the feed-through voltages of the odd and even pixel units 30 in the same row are different, or the odd and even pixel units 30 respectively need two different common electrodes 32 for compensation. If there is only one common electrode 32 without compensation, vertical line symptoms are often seen in the display.

Fig. 2 is a signal diagram showing signals of the source line 11 and the gate lines 21 and 22 and a VGH-dependent compensation voltage (Vcompensated)121 according to the first embodiment of the present invention. Fig. 3 shows a schematic diagram of a corresponding array substrate gate driver 20 circuit.

At least one of the first array substrate gate driver 20 and the second array substrate gate driver 20 includes a gate driving circuit 150 and a compensation system 120, and the gate driving circuit 150 may be configured to generate a plurality of gate control signals to the gate lines 21, 22, each gate control signal having an alternating waveform of alternating high and low levels. The high-level pulse of the gate control signal is turned on and off in sequence, and when the thin film transistor 31 of the pixel unit 30 connected to the gate lines 21 and 22 is turned on by the high-level pulse, a display signal is input from the source line 11. The time length for scanning all the gate lines G1 to G N is one frame, and the time length is also the period of the gate control signal on each

gate line

21, 22.

As described above, since the common electrode VCOM 32 is a static dc voltage without voltage adjustment, the feed-through voltage is not compensated, and the vertical line symptoms are shown, the present invention provides a method involving the use of voltage compensation in an integrated circuit. The method adjusts the VGH voltage level using the compensation system 120 in the array substrate gate driver 20, thereby adjusting the high level of the gate control signal to compensate for the different feedthrough voltages driving the odd and even pixel cells 30.

The voltage compensation method includes coupling a pulse of VGH1 level to each odd gate line 21 (G1, G3 … G N-1) and coupling a pulse of VGH2 level to each even gate line 22 (G2, G4 … G N), or in other words, the first array substrate gate driver 20 drives the odd gate lines 21 at VGH1 level and the second array substrate gate driver 20 drives the even gate lines 22 at VGH2 level. The voltage difference between the VGH1 level and the VGH2 level is Δ V1130, which can be adjusted by the compensation system 120 of the array substrate gate driver 20. In particular, as shown in fig. 3, the compensation system 120 may adjust the feed-through voltage by adjusting the compensation voltage 121 to achieve different VGH1 and VGH2 voltages.

In more detail, the source driver 10 generates the VGH voltage 110 and the VGL voltage 140, and is electrically connected to the array substrate gate driver 20 to provide high and low levels of the gate. The first embodiment of the present invention provides a smoothing capacitor 111 connected from the VGH voltage 110 to the compensation voltage 121, wherein the capacitance of the smoothing capacitor 111 ranges between 0.1uF and 10 uF. The compensation voltage 121 may be selected between Δ V1(VGH offset) 130 and the ground voltage (GND), and in one embodiment, the compensation voltage 121 may be connected to Δ V1130 through a first switch 131 or to the ground voltage through a second switch 132. Therein, reference numeral 130 may be denoted as Δ V1 or Δ V2 according to the connected voltage (VGH or VGL). When the VGH voltage 110 needs to be compensated, the first switch 131 is switched off, so that the compensation voltage 121 is coupled to Δ V1130. When the VGH voltage 110 does not need to be compensated, the second switch 132 is turned off, so that the compensation voltage 121 is coupled to the ground voltage. Accordingly, the high level of the gate control signal is VGH or VGH +. DELTA.V 1.

For low levels of the gate, the compensation system 120 of the present invention can also adjust VGL to achieve feed-through voltage adjustment, and the compensation voltage 121 can also be selected to compensate the VGL voltage 140. In this alternative embodiment, another smoothing capacitor may be connected from the VGL voltage 140 to the compensation voltage 121. Since the offset voltage 121 can be selected between Δ V2(VGL offset value) 130 and the ground voltage, the low level of the gate control signal is VGL or VGL + Δ V2. The compensation voltage 121 may be connected to Δ V2 through a first switch 131, or connected to a ground voltage through a second switch 132. Wherein the capacitance of the other smoothing capacitor ranges between 0.1uF and 10 uF.

As described above, the first embodiment of the present invention provides a method for driving a dual gate display, which includes the following steps. First, the source driver 10 generates a gate driving control signal 12/13, a VGH voltage 110, and a VGL voltage 140 coupled to the two array substrate gate drivers 20; secondly, adjusting the VGH voltage 110 level received by at least one of the array substrate gate drivers 20; finally, the odd-numbered gate lines 21 are driven by the first array substrate gate driver of the two array substrate gate drivers 20; and driving the even number of gate lines 22 by a second array substrate gate driver of the two array substrate gate drivers 20. Wherein, the high level of the gate control signal generated by the array substrate gate driver 20 is adjusted to compensate for the different feedthrough voltages driving the neighboring pixel units 30 by adjusting the received VGH voltage 110 level. In addition, the method further includes adjusting the VGL voltage 140 level received by at least one of the array substrate gate drivers 20.

Fig. 4 is a block diagram showing the structure of the source driver 10 according to the second embodiment of the present invention. As described above, since the position and physical orientation of the tft affects the feedthrough voltage, the odd and even pixel cells 30 require two different common electrodes 32 for compensation, but the capacitance of the common electrode 32 is large, the voltage cannot be stabilized in a short time, and it is substantially impossible to adjust the refresh rate of the odd and even pixel cells 30 at a high frequency. However, the source line 11 voltage is relatively easier to adjust at the refresh rate of the pixel cells 30, and the array substrate gate driver 20 does not need to adjust the high and low levels of the gate control signals.

According to the second embodiment of the present invention, the source driver 10 includes a gamma generator 210, a VCOM generator 220, and a source driving circuit 230, wherein the source driver 10 is configured to drive a plurality of source lines 11(S [1] to S [ M ]), each of which is connected to the source electrodes of the thin film transistors 31 of the same column of pixel units 30. Other circuit blocks for driving, synchronizing and updating the array substrate gate driver 20 may be included in the source driver 10, but are not shown in fig. 1. The source driving circuit 230 may be configured to generate a plurality of source control signals to the source lines 11, each source control signal having an alternating waveform in which a VCOMH level, a VCOML level, and the common electrode 32 alternate. Each source line 11 outputs a display signal to the source electrode of TFT 31 of each pixel unit 30 in time sequence, wherein the display signal is outputted between VCOMH and VCOML in time sequence by source driving circuit 230 according to the gamma curve in accordance with the image brightness.

As known in the art, the gamma curve includes a positive gamma curve 211 and a negative gamma curve 212, which represent the relationship between the output brightness (horizontal axis) of the display and the output voltage (vertical axis) of the source driving circuit 230. Fig. 5A and 6A respectively show a typical positive gamma curve 211 and a typical negative gamma curve 212, which are the positive gamma curve 211 and the negative gamma curve 212 driven by the gamma generator 210 in the second embodiment of the present invention. The positive gamma curve 211 and the negative gamma curve 212 are set by a register according to the characteristics of the liquid crystal of the display, and the polarity is inverted every predetermined period, so that the two curves are not necessarily symmetrical. The positive gamma voltages are all higher than the common electrode 32 while all negative gamma voltages are lower than the common electrode 32. The source driving circuit 230 divides the generated and outputted voltage into several voltage levels each corresponding to one gray level (V0 to V255) of the brightness of the displayed image according to the displayed image data and the positive and negative gamma curves 211, 212. Accordingly, the positive gamma curve 211 and the negative gamma curve 212 drive one column of the pixel units 30, and the positive gamma curve 213 with compensation and the negative gamma curve 214 with compensation drive one column of the pixel units 30 adjacent to the one column of the pixel units 30.

Since the common electrode 32 driven by the VCOM generator 220 of the present invention is static, the feedthrough voltage causes the odd and even pixel cells 30 to display different colors even when driven at the same voltage level, so that vertical line symptoms are often seen in the display. In order to compensate for the display brightness difference between the odd and even pixel units 30, the gamma generator 210 of the present invention is also configured to drive a positive gamma curve 213 with compensation and a negative gamma curve 214 with compensation, wherein the positive gamma curve 213 with compensation is voltage-shifted for each gray level of the positive gamma curve 211 as shown in fig. 5B, and similarly, the negative gamma curve 214 with compensation is voltage-shifted for each gray level of the negative gamma curve 212 as shown in fig. 6B.

More specifically, the gamma generator 210 of the present invention has four sets of gamma register settings respectively defining a positive gamma curve 211, a negative gamma curve 212, a positive gamma curve 213 with compensation, and a negative gamma curve 214 with compensation. The second embodiment of the present invention is to adjust four sets of gamma register settings in advance during the development of the display, wherein two sets of gamma register settings are compensated and used for the pixel units of two adjacent columns respectively to compensate the vertical line symptoms caused by the feed-through voltage.

This shows a dual gate display compensation method and system according to the present invention, which has the effect of improving or solving the vertical line symptoms commonly seen in dual gate displays. It will be apparent that variations of the above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different methods or apparatuses. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims

1. A drive system for a dual gate display comprising a plurality of pixel cells arranged in rows and columns, each pixel cell comprising a display electrode capacitance and a thin film transistor; the display electrode capacitor includes a first terminal coupled to the drain electrode of the thin film transistor and a second terminal coupled to a common electrode, the driving system includes:

a source driver;

a first array substrate gate driver configured to drive odd-numbered gate lines; and

a second array substrate gate driver configured to drive even-numbered gate lines,

wherein one of the odd-numbered gate lines and an adjacent one of the even-numbered gate lines are connected to gate electrodes of thin film transistors of pixel cells of the same row from different directions, so that the adjacent pixel cells have different feed-through voltages;

the first array substrate gate driver and the second array substrate gate driver each include a gate driving circuit configured to generate a plurality of gate control signals to the gate lines, each gate control signal having an alternating waveform of alternating high and low levels,

wherein at least one of the first array substrate gate driver and the second array substrate gate driver further comprises a compensation system generating a compensation voltage for adjusting a voltage level of a high level of the gate control signal to compensate for different feedthrough voltages driving adjacent pixel cells.

2. The drive system of claim 1, wherein the compensation system further comprises a smoothing capacitor connected from a VGH voltage to the compensation voltage, wherein the compensation voltage is selectable between Δ V1 and ground voltage, whereby the high level is VGH or VGH + Δ V1.

3. The drive system of claim 2, wherein the compensation voltage is connectable to Δ V1 through a first switch or to a ground voltage through a second switch.

4. The drive system of claim 2, wherein the smoothing capacitor has a capacitance ranging between 0.1uF and 10 uF.

5. The drive system of claim 1, wherein the compensation system further comprises another smoothing capacitor connected from a VGL voltage to the compensation voltage, wherein the compensation voltage is selectable between Δ V2 and ground voltage, whereby the low level is VGL or VGL + Δ V2.

6. The drive system of claim 5, wherein the compensation voltage is connectable to Δ V2 through a first switch or to a ground voltage through a second switch.

7. The drive system of claim 5, wherein the capacitance of the further smoothing capacitor ranges between 0.1uF and 10 uF.

8. A drive system for a dual gate display comprising a plurality of pixel cells arranged in rows and columns, each pixel cell comprising a display electrode capacitance and a thin film transistor; the display electrode capacitor includes a first terminal coupled to the drain electrode of the thin film transistor and a second terminal coupled to a common electrode, the driving system includes:

a source driver including a gamma generator and a source driving circuit, wherein the source driving circuit is configured to generate a plurality of source control signals to source lines, each of the source lines being connected to source electrodes of thin film transistors of a same column of pixel cells, each of the source control signals having alternating waveforms of a VCOMH level, a VCOML level, and a common electrode; and

a first array substrate gate driver and a second array substrate gate driver configured to drive odd-numbered and even-numbered gate lines, respectively,

wherein the gamma generator is configured to drive a positive gamma curve, a negative gamma curve, a positive gamma curve with compensation, and a negative gamma curve with compensation, wherein the positive gamma curve and the negative gamma curve drive a column of pixel units, and the positive gamma curve with compensation and the negative gamma curve with compensation drive a column of pixel units adjacent to the column of pixel units.

9. The drive system of claim 8, wherein the gamma generator further comprises four sets of gamma register settings respectively defining the positive gamma curve, the negative gamma curve, the positive gamma curve with compensation, and the negative gamma curve with compensation.

10. The driving system of claim 9, wherein the four sets of gamma register settings are independently set to compensate for color and brightness deviations of the pixel cells of the column and the adjacent column based on the display characteristics.

11. The driving system of claim 8, wherein the positive gamma curve with compensation is voltage-shifted for each gray level of the positive gamma curve.

12. The driving system of claim 8, wherein the negative gamma curve with compensation is voltage-shifted for each gray level of the negative gamma curve.

13. The drive system of claim 8, wherein the source driver further comprises a VCOM generator, wherein the common electrode driven by the VCOM generator is static.

14. A method for driving a dual gate display comprising a plurality of pixel cells arranged in rows and columns, each pixel cell comprising a display electrode capacitance and a thin film transistor; the display electrode capacitor comprises a first end and a second end, the first end is coupled to the drain electrode of the thin film transistor, the second end is coupled to the common electrode, the driving system comprises a source driver and two array substrate gate drivers, and the method comprises the following steps:

the source driver generates a gate driving control signal, a VGH voltage and a VGL voltage which are coupled to the two array substrate gate drivers;

adjusting the VGH voltage level received by at least one array substrate gate driver;

driving odd-numbered gate lines by a first array substrate gate driver of the two array substrate gate drivers; and

driving an even number of gate lines by a second array substrate gate driver of the two array substrate gate drivers,

and adjusting the high level of the gate control signal generated by the gate driver of the array substrate to compensate for different feed-through voltages for driving adjacent pixel units by adjusting the received VGH voltage level.

15. The method of claim 14, wherein adjusting the VGH voltage level received by at least one of the array substrate gate drivers comprises:

the compensation voltage is connected to the received VGH voltage through a smoothing capacitor, wherein the compensation voltage can be selected between Δ V1 and a ground voltage, and thus, the high level is VGH or VGH + Δ V1.

16. The method of claim 15, wherein the compensation voltage is connectable to av 1 through a first switch or to a ground voltage through a second switch.

17. The method of claim 14, further comprising the steps of:

and adjusting the VGL voltage level received by at least one array substrate gate driver, wherein the low level of the gate control signal generated by the array substrate gate driver is adjusted to compensate for different feed-through voltages for driving adjacent pixel units by adjusting the received VGL voltage level.

18. The method of claim 17, wherein adjusting the VGL voltage level received by at least one of the array substrate gate drivers comprises:

the compensation voltage is connected to the received VGL voltage through a smoothing capacitor, wherein the compensation voltage can be selected between Δ V2 and a ground voltage, and thus, the low level is VGL or VGL + Δ V2.

19. The method of claim 18, wherein the compensation voltage is connectable to av 2 through a first switch or to a ground voltage through a second switch.