CN109949756B - Feed-through voltage compensation circuit unit, feed-through voltage compensation circuit and liquid crystal display device - Google Patents
Feed-through voltage compensation circuit unit, feed-through voltage compensation circuit and liquid crystal display device Download PDFInfo
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Abstract
The invention relates to a feed-through voltage compensation circuit unit, a feed-through voltage compensation circuit and a liquid crystal display device. The compensation circuit unit includes: a first input end VghA, a second input end VglA, a third input end g (n), a first switch tube T1, a second switch tube T2, a third switch tube T3, a fourth switch tube T4 and an output end gc (n); the first switch tube T1 and the third switch tube T3 are sequentially connected in series between the first input end VghA and the second input end VglA; the second switch tube T2 and the fourth switch tube T4 are sequentially connected in series between the first input end VghA and the second input end VglA; the output terminal gc (n) is electrically connected to a node formed by the second switch transistor T2 and the fourth switch transistor T4 connected in series. The invention reduces the influence of the Feedthrough voltage on the pixel voltage of the panel by providing the compensation circuit unit, has simple and easily realized circuit, reduces the design cost and improves the production efficiency.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a feed-through voltage compensation circuit unit, a feed-through voltage compensation circuit and a liquid crystal display device.
Background
A Liquid Crystal Display (LCD) is one of flat panel displays, and is widely used in products such as televisions, computers, smart phones, mobile phones, car navigation devices, electronic books, and the like. Liquid crystal display devices have the advantages of low power consumption, small size, and low radiation, and are gradually replacing Cathode Ray Tube (CRT) display devices.
In the driving process of the liquid crystal display device, scanning voltage is loaded to pixels of each row by scanning lines, the pixels are influenced by the voltage change of scanning signals when charging is completed, when the scanning voltage is changed from a high level to a low level, the pixel voltage is coupled downwards due to the existence of feed through voltage, so that the original balanced common electrode voltage is deviated, and if the adjustment is not carried out in time, the display screen flickers. The larger the pixel voltage variation, the greater the likelihood of the panel developing frame sticking and reliability problems. As shown in fig. 1, the equation of the Feedthrough voltage is:
Disclosure of Invention
Therefore, in order to solve the technical defects and shortcomings of the prior art, the invention provides a feed-through voltage compensation circuit unit, a feed-through voltage compensation circuit and a liquid crystal display device, which can compensate the display flicker phenomenon caused by feed-through voltage on the premise of not changing a scanning line integrated IC.
Specifically, one embodiment of the present invention provides a feedthrough voltage compensation circuit unit including: a first input end VghA, a second input end VglA, a third input end g (n), a first switch tube T1, a second switch tube T2, a third switch tube T3, a fourth switch tube T4 and an output end gc (n); wherein the content of the first and second substances,
the first switch tube T1 and the third switch tube T3 are sequentially connected in series between the first input end VghA and the second input end VglA, and the control end of the first switch tube T1 is electrically connected to the first input end VghA, and the control end of the third switch tube T3 is electrically connected to the third input end g (n);
the second switch tube T2 and the fourth switch tube T4 are sequentially connected in series between the first input end VghA and the second input end VglA, a control end of the second switch tube T2 is electrically connected to a node formed by the first switch tube T1 and the third switch tube T3 connected in series, and a control end of the fourth switch tube T4 is electrically connected to the third input end g (n);
the output terminal gc (n) is electrically connected to a node formed by the second switch transistor T2 and the fourth switch transistor T4 connected in series.
In an embodiment of the present invention, the first switch transistor T1, the second switch transistor T2, the third switch transistor T3, and the fourth switch transistor T4 are all TFT transistors.
In an embodiment of the present invention, the first switch transistor T1, the second switch transistor T2, the third switch transistor T3, and the fourth switch transistor T4 are all MOS transistors.
In an embodiment of the present invention, the channel width ratio of the first switching tube T1, the second switching tube T2, the third switching tube T3 and the fourth switching tube T4 is 1: n: n: 2N, and (3).
In an embodiment of the invention, the circuit unit is disposed in the Gate region and the output end gc (N) of the circuit unit forms a coupling capacitor with the pixel electrode in the nth row.
In one embodiment of the present invention, the compensation line formed by the output terminal gc (n) is located in a region parallel to the scan line.
In one embodiment of the present invention, the compensation line formed by the output terminal gc (n) is located in the middle region of the sub-pixel.
In one embodiment of the present invention, the first input terminal VghA and the second input terminal VglA input the turn-on voltage Vgh and the turn-off voltage Vgl of the TFT transistor, respectively, and the third input terminal g (N) inputs the scan voltage of the nth row of scan lines.
Another embodiment of the present invention provides a feedthrough voltage compensation circuit, including the feedthrough voltage compensation circuit unit described in any of the above embodiments; each feed-through voltage compensation circuit unit corresponds to one path of scanning driving circuit unit.
The invention further provides a liquid crystal display device, which comprises a time schedule controller, a scanning driving circuit, a data driving circuit and a pixel matrix, and further comprises the feed-through voltage compensation circuit in the embodiment.
Compared with the prior art, the invention has the following beneficial effects:
1) the circuit unit provided by the invention does not need to create a compensation signal from the inside of a scanning line integrated IC, but generates the compensation signal in a scanning signal area of the array side (namely a TFT side) of the liquid crystal display panel through a circuit, so that the display problem caused by the fed through voltage is improved under the condition of not changing the IC, and the design cost is not increased;
2) the circuit unit provided by the invention can be directly used in a GOA circuit, so that the display problem caused by the feed through voltage can be solved while the narrow frame of the product is realized.
Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Drawings
The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.
FIG. 1 is a waveform diagram of charging of a liquid crystal display panel;
FIG. 2 is a schematic diagram of a prior art panel circuit design for reducing the Feedthrough voltage;
fig. 3 is a schematic diagram of a Feedthrough voltage compensation circuit unit according to an embodiment of the present invention;
fig. 4 is a waveform diagram of an output of the Feedthrough voltage compensation circuit unit according to the embodiment of the present invention;
fig. 5 is an equivalent circuit diagram of a Feedthrough voltage compensation pixel according to an embodiment of the present invention;
fig. 6 is a schematic diagram of layout arrangement of a pixel unit under 4Domain VA Mode according to an embodiment of the present invention;
fig. 7 is a schematic diagram of layout arrangement of a pixel unit under 4Domain VA Mode according to another embodiment of the present invention;
fig. 8 is an equivalent circuit diagram of a pixel under 4Domain VA Mode according to an embodiment of the present invention;
fig. 9 is a schematic diagram of layout arrangement of a pixel unit under 8Domain VA Mode according to an embodiment of the present invention;
fig. 10 is an equivalent circuit diagram of a pixel under 8Domain VA Mode according to an embodiment of the present invention;
fig. 11 is a schematic diagram illustrating a nine-point distribution of a panel according to an embodiment of the present invention;
fig. 12 is a diagram of simulation comparison data for 11-point pixel feed through voltage compensation of a panel according to an embodiment of the present invention;
fig. 13 is a diagram of simulation comparison data for 33-point pixel feed through voltage compensation of a panel according to an embodiment of the present invention;
fig. 14 is a schematic diagram of a Feedthrough voltage compensation circuit module according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Example one
Referring to fig. 3, fig. 3 is a schematic diagram of a Feedthrough voltage compensation circuit unit according to an embodiment of the present invention. Specifically, the Feedthrough voltage compensation circuit unit may include: a first input end VghA, a second input end VglA, a third input end g (n), a first switch tube T1, a second switch tube T2, a third switch tube T3, a fourth switch tube T4 and an output end gc (n); wherein the content of the first and second substances,
the first switch tube T1 and the third switch tube T3 are sequentially connected in series between the first input end VghA and the second input end VglA, and the control end of the first switch tube T1 is electrically connected to the first input end VghA, and the control end of the third switch tube T3 is electrically connected to the third input end g (n);
the second switch tube T2 and the fourth switch tube T4 are sequentially connected in series between the first input end VghA and the second input end VglA, a control end of the second switch tube T2 is electrically connected to a node formed by the first switch tube T1 and the third switch tube T3 connected in series, and a control end of the fourth switch tube T4 is electrically connected to the third input end g (n);
the output terminal gc (n) is electrically connected to a node formed by the second switch transistor T2 and the fourth switch transistor T4 connected in series.
The first switch tube T1, the second switch tube T2, the third switch tube T3 and the fourth switch tube T4 are all TFT transistors. Optionally, the first switch transistor T1, the second switch transistor T2, the third switch transistor T3, and the fourth switch transistor T4 may all be MOS transistors.
The channel width ratio of the first switching tube T1, the second switching tube T2, the third switching tube T3 and the fourth switching tube T4 is 1: n: n: 2N, N is greater than 1.
Preferably, the channel width ratio of the first switching tube T1, the second switching tube T2, the third switching tube T3 and the fourth switching tube T4 is 1: 7: 7: 14. the benefits of this are: the switching tube is provided with different channel width ratios, so that the switching sequence of the switching tube can be controlled.
This embodiment is through designing the simple structure feed through voltage compensation circuit unit that easily realizes, and output feed through voltage compensation voltage for the pixel voltage who solves liquid crystal display device changes along with scanning line signal voltage and causes the problem of display screen scintillation, when having avoided among the prior art to handle the solution this problem through carrying out the chamfer to the scanning line signal, the influence that pixel charging voltage received.
Example two
Referring to fig. 4 to fig. 13 and fig. 3 again, fig. 4 is a waveform diagram of an output waveform of a Feedthrough voltage compensation circuit unit according to an embodiment of the present invention; fig. 5 is an equivalent circuit diagram of a Feedthrough compensation pixel according to an embodiment of the present invention; fig. 6 is a schematic diagram of layout arrangement of a pixel unit under 4Domain VA Mode according to an embodiment of the present invention; fig. 7 is a schematic diagram of layout arrangement of a pixel unit under 4Domain VA Mode according to another embodiment of the present invention; fig. 8 is an equivalent circuit diagram of a pixel under 4Domain VA Mode according to an embodiment of the present invention; fig. 9 is a schematic diagram of layout arrangement of a pixel unit under 8Domain VA Mode according to an embodiment of the present invention; fig. 10 is an equivalent circuit diagram of a pixel under 8Domain VA Mode according to an embodiment of the present invention; fig. 11 is a schematic diagram illustrating a nine-point distribution of a panel according to an embodiment of the present invention; fig. 12 is a diagram of comparative simulation data of 11-point pixel Feedthrough compensation of a panel according to an embodiment of the present invention; fig. 13 is a diagram of simulation comparison data of panel 33-point pixel Feedthrough compensation according to an embodiment of the present invention. In this embodiment, on the basis of the above embodiments, the Feedthrough compensation circuit unit provided by the present invention is described in detail.
Specifically, the input voltage of the first input terminal VghA of the Feedthrough voltage compensation circuit unit is the turn-on voltage Vgh of the TFT transistor, the input voltage of the second input terminal VglA is the turn-off voltage Vgl of the TFT transistor, and the input voltage of the third input terminal g (N) is the scanning voltage of the nth row scanning line. When the third input end g (N) is Vgl, that is, the nth row scanning line voltage is Vgl, the first switching tube T1 and the second switching tube T2 are turned on, and at this time, the output end gc (N) outputs a voltage of Vgh-Vth, where Vth is the threshold voltage of the TFT transistor, and when the third input end g (N) voltage is Vgh, the third switching tube T3 and the fourth switching tube T4 are turned on, and the ratio of the channel widths (W) of the first switching tube T1, the second switching tube T2, the third switching tube T3, and the fourth switching tube T4 is W1: w2: w3: w4 ═ 1: n: n: 2N, preferably, W1: w2: w3: w4 ═ 1: 7: 7: 14, since the width-to-length ratio of the first switch tube T1 is smaller than that of the third switch tube T3, the third switch tube T3 and the fourth switch tube T4 play a dominant role, the second input terminal VglA closes the second switch tube T2 through the third switch tube T3, and simultaneously the second input terminal VglA pulls the voltage of the output terminal gc (n) back to the low voltage Vgl through the fourth switch tube T4, during which the third input terminal g (n) and the output terminal gc (n) output two waveforms with substantially the same differential pressure change and opposite change trends, as shown in fig. 4. When the output voltage gc (N) is input to the lcd device for the feed through compensation, the pixel equivalent circuit diagram is as shown in fig. 5, a coupling capacitor Cgc is formed between the compensation line connected to the output terminal gc (N) and the pixel electrode PE, a parasitic capacitor Cgs is formed between the nth row scanning line g (N) connected to the third input terminal and the pixel electrode PE, and the transistor T connects the data line to the liquid crystal capacitor Clc and the storage capacitor Cs. When the scan line is applied with the transistor turn-on voltage Vgh, the transistor T is turned on. The turned-on transistor T transmits the data voltage on the data line to the liquid crystal capacitor Clc and the storage capacitor Cs. The liquid crystal capacitor Clc and the storage capacitor Cs are charged by the data voltage, and a corresponding pixel voltage is generated on the pixel electrode PE. The pixel voltage is affected by the coupling capacitance Cgs between the scan line and the pixel electrode PE, and when the voltage inputted by the scan line changes, for example, from a high voltage to a low voltage, the feed through voltage generated by the scan line via the coupling capacitance Cgs affects the magnitude of the pixel voltage. The pixel voltage is also affected by a coupling capacitance Cgc between the compensation line and the pixel electrode PE. At this time, the differential pressure Δ Vp1 generated by the voltage change of the scanning line is as shown in formula 1, and the differential pressure Δ Vp2 generated by the voltage change of the compensation line is as shown in formula 2, and when the values of Δ Vp1 and Δ Vp2 are substantially equal and opposite, they can be cancelled out, so that the Cgs compensation effect is achieved.
Where Vth is the TFT threshold voltage, Cgs is Cgc, and hence Δ Vp1 +/Δ Vp2 is 0.
Further, under 4Domain VA Mode, a pixel unit layout is arranged as shown in fig. 6, and the compensation line is parallel to the scan line and arranged in the region adjacent to the scan line.
Further, under 4Domain VA Mode, another pixel unit layout arrangement is shown in fig. 7, where the compensation line is parallel to the scan line and the compensation line is disposed in the middle region of the pixel.
Fig. 8 shows equivalent circuit diagrams of the layout of fig. 6 and the layout of fig. 7, a coupling capacitor Cgc is formed between the compensation line connected to the output terminal gc (n) and the pixel electrode PE, the scan line connected to the third input terminal g (n) is connected to the pixel electrode PE through a parasitic capacitor Cgs, and the transistor TM connects the data line to a capacitor Ccst, where the capacitor Ccst is an equivalent capacitor of the pixel electrode PE.
Further, under 8Domain VA Mode, a pixel unit layout is arranged as shown in fig. 9, two sub-pixel units share one scan line, the compensation line is parallel to the scan line, and the compensation line is arranged in the middle region of the pixel. As shown in fig. 10, the TFT transistor TM in the a pixel unit region and the TFT transistor TS in the B pixel unit region share a scan voltage and a compensation voltage, coupling capacitors CAgc and CBgc are respectively formed between the compensation line connected to the output terminal gc (n) and the pixel electrodes PE in the a region and the B region, coupling capacitors CAgs and CBgs are respectively formed between the scan line connected to the third input terminal g (n) and the pixel electrodes PE in the a region and the B region, and the transistor TM in the a region and the transistor TS in the B region respectively connect the data line to the equivalent capacitor CAcst and the equivalent capacitor CBcst. The Low Color Shift Resistance Type (LCR for short) TFT is a pixel design, and the purpose of Low Color Shift of the pixel is achieved by adjusting the voltage difference between an A area and a B area by designing the width-length ratio of the LCR TFT channel; TFTVom is the common electrode on the TFT side.
A simulation data table of compensation effects of Cgs and Cgc capacitors is shown in the following table, and suppose that Vgh is 28V, Vgl is-8V and a panel is 9-point distribution, as shown in FIG. 11, wherein 11 represents a first pixel point in a first row, 12 represents a second pixel point in the first row, and 13-33 are analogized in sequence. Table 1 shows Δ Vp values of each pixel of the panel at a certain time without the Feedthrough voltage compensation. As shown in table 1, when there is no Feedthrough voltage compensation, the Δ Vp value of each pixel of the panel is more than 2V, and the value is large, which seriously affects the pixel charging voltage, wherein the Δ Vp value can reach 2.58V at most, and the influence thereof cannot be ignored. Table 2 shows Δ Vp values at a certain time of each pixel of the panel when the voltage compensation is provided and Cgc is Cgsoff (Cgsoff is a capacitance formed by the scanning line and the pixel electrode or the TFT source when the scanning line is at a low voltage). Compared with table 1, after the Feedthrough voltage compensation is added, the Δ Vp value of each pixel point in table 2 is obviously reduced to below 1V, and the maximum Δ Vp value is 0.74V. Table 3 shows Δ Vp values of each pixel of the panel at a certain time with Feedthrough voltage compensation and Cgc 1.3 × Cgsoff. Compared with the table 2, the Δ Vp value of each pixel point in the table 3 is further reduced to be below 0.4V, and the maximum Δ Vp value is 0.22V. Therefore, as can be seen from the table, the coupling capacitance Cgc has a significant compensation effect on the Feedthrough voltage.
TABLE 1
| |
11 | 12 | 13 |
| △Vp(V) | 2.56 | 2.31 | 2.27 |
| |
21 | 22 | 23 |
| △Vp(V) | 2.58 | 2.31 | 2.26 |
| |
31 | 32 | 33 |
| △Vp(V) | 2.58 | 2.32 | 2.26 |
TABLE 2
| |
11 | 12 | 13 |
| △Vp(V) | 0.74 | 0.50 | 0.45 |
| |
21 | 22 | 23 |
| △Vp(V) | 0.74 | 0.49 | 0.44 |
| |
31 | 32 | 33 |
| △Vp(V) | 0.68 | 0.50 | 0.45 |
TABLE 3
Simulation data plots of the effects of Cgs and Cgc capacitance on compensation are shown in fig. 12 and 13. It can be seen from the figure that after the Cgc compensation capacitance is added, the pixel voltage is substantially constant when the positive and negative polarities of the scan line voltage are changed. Specifically, as shown in fig. 12, the abscissa of the graph represents time, the ordinate represents voltage value, when the gate voltage is not compensated by the feedthru voltage, the pixel voltage is decreased from 16.28V at the time point of 27.53 μ 7 to 13.72V at the time point of 30.04Vr when the gate voltage is changed, the voltage difference Δ Vp of the pixel voltage is 2.56V, and when the gate voltage is changed after the feedthru voltage compensation is added, the pixel voltage is decreased from 16.20V at the time point of 27.44 to 16.16V at the time point of 34.43 μ 4 when the gate voltage is changed, the voltage difference Δ Vp of the pixel voltage is only 0.04V. As shown in fig. 13, the abscissa of the graph represents time, the ordinate represents voltage value, when the gate voltage is changed without the feedthru voltage compensation, the pixel voltage is decreased from 15.89V at the time point of 27.81 μ 1 to 33.09V, when the gate voltage is changed to 13.42V at the time point of s, the voltage difference Δ Vp of the pixel voltage is 2.47V, when the gate voltage is changed after the feedthru voltage compensation is added, the pixel voltage is increased from 27.77V at the time point of 15.81V to 36.85V at the time point of 15.89V at the time point, and the voltage difference Δ Vp of the pixel voltage is only-0.08V.
In the embodiment, the compensation signal is generated by scanning the signal area design circuit on the array side of the liquid crystal display panel, and is input to the pixel electrode through the coupling capacitor, so that the problem of display screen flicker caused by the feed through voltage can be solved without changing the IC, and the additional design cost is not increased.
EXAMPLE III
Referring to fig. 14 and 15, fig. 14 is a schematic diagram of a Feedthrough voltage compensation circuit according to an embodiment of the present invention, and fig. 15 is a schematic diagram of a structure of a liquid crystal display device according to an embodiment of the present invention. The present embodiment describes in detail the Feedthrough voltage compensation circuit and the liquid crystal display device using the Feedthrough voltage compensation circuit provided by the present invention on the basis of the above embodiments.
Specifically, the feedthru voltage compensation circuit includes N feedthru voltage compensation circuit units, and each feedthru voltage compensation circuit unit corresponds to one path of the scan driving circuit unit. The first input end of each of the feedthru voltage compensation circuit units is connected to form a first input end VghB of the feedthru voltage compensation circuit, that is, the first input end Vgh1A of the first feedthru voltage compensation circuit unit, the first input end Vgh2A of the second feedthru voltage compensation circuit unit to the first input end VghnA of the nth feedthru voltage compensation circuit unit are connected to form the first input end VghB of the feedthru voltage compensation circuit; the second input terminals of the respective feedthru voltage compensation circuit units are connected to form a second input terminal VglB of the feedthru voltage compensation circuit, that is, the second input terminals Vgl1A of the first feedthru voltage compensation circuit unit, the second input terminals Vgl2A of the second feedthru voltage compensation circuit unit to the second input terminal VglnA of the nth feedthru voltage compensation circuit unit are connected to form a second input terminal VglB of the feedthru voltage compensation circuit. The input voltage of the first input terminal VghB of the feedthrogh voltage compensation circuit is the turn-on voltage (Vgh) of the TFT transistor, the input voltage of the second input terminal VglB of the feedthrogh voltage compensation circuit is the turn-off voltage (Vgl) of the TFT transistor, and the input voltage of the third input terminal G (N) of each feedthrogh voltage compensation circuit unit is the scan voltage of one scan driving circuit unit, that is, the third input terminal of each feedthrogh voltage compensation circuit unit can be electrically connected to the scan signal output terminal of a certain row scan line of the corresponding scan driving circuit, for example, the third input terminal G (1N) of the first feedthrogh voltage compensation circuit unit is electrically connected to the scan signal output terminal of the first row scan line, the third input terminal G (2N) of the second feedthrogh voltage compensation circuit unit is electrically connected to the scan signal output terminal of the second row scan line, and so on, the third input terminal G (N) of the nth feedthrogh voltage compensation circuit unit is electrically connected to the scan signal output terminal of the scan line N scan line And (4) an output end.
Because the third input terminal g (n) and the output terminal gc (n) of the Feedthrough voltage compensation circuit unit output two waveforms with basically the same voltage difference change and opposite change trends. Therefore, when the N output voltages of the feedthrogh voltage compensation circuit are input to the liquid crystal display device for feedthrogh voltage compensation, the values of Δ Vp1 generated by the voltage change of the third input terminal of each feedthrogh voltage compensation circuit unit and Δ Vp2 generated by the compensation voltage change of the output terminal are substantially equal, and the positive and negative are opposite, and can be cancelled out, thereby achieving the Cgs compensation effect.
Further, the embodiment also provides a liquid crystal display device. The liquid crystal display device comprises a time sequence controller, a scanning driving circuit, a data driving circuit, a pixel matrix and a feed voltage compensation circuit, wherein the feed voltage compensation circuit comprises a plurality of feed voltage compensation circuit units. Each feedthru voltage compensation circuit unit can be arranged in the array side scanning signal area, so that a compensation signal does not need to be created from a scanning line driving circuit part, and the compensation signal is generated on a panel through a circuit, so that the display problem caused by the feedthru voltage is improved under the condition of not changing the driving circuit, the design cost is not increased, and the design of a narrow frame can be realized.
In summary, the principle and implementation of the feed-through compensation circuit unit, the circuit module and the liquid crystal display device provided by the embodiments of the present invention are described herein by applying specific examples, and the above description of the embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention, and the scope of the present invention should be subject to the appended claims.
Claims (10)
1. A feedthrough voltage compensation circuit cell, comprising: a first input end (Vgha), a second input end (Vgla), a third input end (G (n)), a first switch tube (T1), a second switch tube (T2), a third switch tube (T3), a fourth switch tube (T4) and an output end (Gc (n)); wherein the content of the first and second substances,
the first switching tube (T1) and the third switching tube (T3) are connected in series between the first input end (VghA) and the second input end (VglA) in sequence, and a control end of the first switching tube (T1) is electrically connected to the first input end (VghA), and a control end of the third switching tube (T3) is electrically connected to the third input end (g (n));
the second switching tube (T2) and the fourth switching tube (T4) are sequentially connected in series between the first input end (VghA) and the second input end (VglA), a control end of the second switching tube (T2) is electrically connected to a node formed by the first switching tube (T1) and the third switching tube (T3) which are connected in series, and a control end of the fourth switching tube (T4) is electrically connected to the third input end (g (n));
the output terminal (gc (n)) is electrically connected to a node formed by the second switching tube (T2) and the fourth switching tube (T4) connected in series.
2. The circuit unit of claim 1, wherein the first switch transistor (T1), the second switch transistor (T2), the third switch transistor (T3), and the fourth switch transistor (T4) are all TFT transistors.
3. The circuit unit of claim 1, wherein the first switch transistor (T1), the second switch transistor (T2), the third switch transistor (T3), and the fourth switch transistor (T4) are all MOS transistors.
4. The circuit unit of claim 1, wherein the channel width ratio of the first switching tube (T1), the second switching tube (T2), the third switching tube (T3) and the fourth switching tube (T4) is 1: n: n: 2N, and (3).
5. The circuit unit of claim 1, wherein the circuit unit is disposed in the Gate region, and the compensation line connected to the output terminal (gc (N)) of the circuit unit forms a coupling capacitor with the pixel electrode in the nth row.
6. A circuit cell according to claim 5, wherein the output terminal (Gc (n)) forms a compensation line in a region parallel to the scanning line.
7. A circuit unit according to claim 5, wherein the output terminal (Gc (n)) forms a compensation line in the middle area of a sub-pixel.
8. The circuit unit according to claim 1, wherein the first input terminal (VghA) and the second input terminal (VglA) input an on voltage (Vgh) and an off voltage (Vgl) of the TFT transistor, respectively, and the third input terminal g (N) inputs a scanning voltage of the scanning line of the nth row.
9. A feed-through voltage compensation circuit comprising a plurality of feed-through voltage compensation circuit units according to any one of claims 1 to 8; each feed-through voltage compensation circuit unit corresponds to one path of scanning driving circuit unit.
10. A liquid crystal display device comprising a timing controller, a scan driving circuit, a data driving circuit, and a pixel matrix, further comprising the feedthrough voltage compensating circuit of claim 9.
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| CN104317086A (en) * | 2014-11-14 | 2015-01-28 | 深圳市华星光电技术有限公司 | Method for driving liquid crystal display panel |
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| JPH1078592A (en) * | 1996-09-03 | 1998-03-24 | Semiconductor Energy Lab Co Ltd | Active matrix display device |
| US7375707B1 (en) * | 1999-09-07 | 2008-05-20 | Lg.Philips Lcd Co., Ltd. | Apparatus and method for compensating gamma voltage of liquid crystal display |
| CN102610205A (en) * | 2012-03-29 | 2012-07-25 | 深圳市华星光电技术有限公司 | Feed-through voltage compensation circuit, liquid crystal display device and feed-through voltage compensation method |
| CN104317086A (en) * | 2014-11-14 | 2015-01-28 | 深圳市华星光电技术有限公司 | Method for driving liquid crystal display panel |
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