JPH05210088A - Driving method for liquid crystal display device - Google Patents

Abstract

PURPOSE:To avert the degradation in a writing ratio and to decrease the driving voltage of a driver IC by shifting the rising and falling timing of the writing pulse and AC voltage pulse of a scanning signal line. CONSTITUTION:The writing pulse and the AC voltage pulse deviate by the time Ts shorter than the writing pulse Tg. Namely, the rising timing of the writing pulse is delayed by the time Ts from the rising timing of the intermediate voltage pulse at the time of writing a positive polarity and, therefore, the voltage of the scanning signal line changes from Vgm to Vgh at the time of the rising of the writing pulse and the voltage of the scanning signal line changes from Vgh to Vgl at the falling of the writing pulse. The AC voltage pulse synchronized at the same voltage amplitude, pulse width and pulse interval as the voltage amplitude, pulse width and pulse interval of the AC voltage pulse of the scanning signal line is applied to a counter electrode. The video signal pulse of a video signal line is nearly synchronized with the writing pulse but is delayed from the writing pulse by the delay time iotagd of the scanning signal line in a usual manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a method of driving a thin film transistor drive type liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display device (Liquid Crystal D
Thin film transistor (hereinafter abbreviated as TFT), which is an amorphous Si semiconductor thin film or polycrystalline Si semiconductor thin film, is used as one of isplay (hereinafter abbreviated as LCD) thin film transistor drive type liquid crystal display device (TFTLCD) Is known. This display device uses a TFT provided on a transparent substrate such as glass to control the voltage applied to the liquid crystal of one pixel (one unit of display), and therefore has the characteristic that the image quality is clear. , Is being widely used in terminals for OA equipment, TVs, and the like.

FIG. 5 shows an equivalent circuit of one pixel. A thin film transistor TFT310 is arranged at the intersection of the scanning signal line 311 and the video signal line 312, and a liquid crystal capacitor 313 and a storage capacitor 314 are connected. When the thin film transistor TFT 310 is turned on by the signal of the scanning signal line 311, the potential of the video signal line 312 is written in the pixel electrode 315, and electric charge is accumulated in the liquid crystal capacitor 313 and the storage capacitor 314. When the thin film transistor TFT310 is turned off, the charges accumulated in the liquid crystal capacitor 313 and the storage capacitor 314 are held. Liquid crystal deteriorates when a DC voltage is applied,
The writing and holding described above are alternately performed with positive and negative polarities with respect to the potential of the counter electrode 316. In this way, the potential written and held in the pixel electrode 315 and the counter electrode 3 are held.
The voltage Vrms effectively applied to the liquid crystal capacitor 313 is determined by time-averaging the potential difference from the potential of 16. This effective voltage Vrms determines the alignment state of the liquid crystal and controls the light transmittance of the liquid crystal.

A driver IC formed on a silicon chip is usually used to drive the scanning signal line and the video signal line. Since the thin film transistor TFT has a small current driving capability, the driver IC is driven at a high voltage. For example, the driver IC on the scanning signal line side usually needs a high voltage of about 25V, and the driver IC on the video signal line side usually needs a high voltage of about 16V. .. Because of the high voltage, it is necessary to increase the withstand voltage of the driver IC, which increases the chip size and the cost. In addition, since it is necessary to use a high breakdown voltage process different from the normal silicon IC manufacturing process for manufacturing the driver IC, the manufacturing cost is further increased. In particular, since the number of driver ICs on the video signal line side is large, the driver ICs are greatly affected, and it has been desired to reduce the driving voltage.

Therefore, as described in Japanese Patent Publication No. 2-10955, there is known a complete storage capacity method in which the storage capacity electrode 317 of the storage capacity 314 is a wiring independent of other wirings. According to this method, the counter electrode 316 and the storage capacitor electrode 317 which are electrodes facing the complete storage capacitor 314 and the liquid crystal capacitor 313 are AC-driven in synchronization with the signal of the video signal line 312, and the video signal line is written at the time of writing. The signal potential of the video signal line 312 can be reduced and the driving voltage of the driver IC can be reduced by superimposing the signal potential of the signal 312 and the AC potential of the counter electrode 316 to be a potential applied to the liquid crystal. Pulse width of this AC drive (1 of 1 cycle)
/ 2) is usually set equal to the selection time of one scanning signal line, and a so-called line inversion driving method is adopted. However, in this method, there is a problem that the number of wirings increases, the probability of disconnection and short circuit increases, and the yield decreases because it is necessary to newly form an electrode wiring of a complete storage capacitor on the TFT substrate. It was

Therefore, as described in Japanese Patent Application Laid-Open No. 2-913, an additional capacitance method is adopted in which the counter electrode 317 of the storage capacitor is used as the scanning signal line in the preceding stage, and in addition to the scanning signal on the scanning signal line, the above-mentioned counter electrode 316 is formed. An additional capacitance type line inversion driving method has been proposed in which the signal potential amplitude of the video signal line 312 is reduced and the driving voltage of the driver IC is reduced by applying an AC signal similar to the signal. Among them, the configuration shown in FIG. 10 and the driving method shown in FIG.
The counter electrodes 316 of No. 3 are common to the entire panel surface, and the TFT LCD can be formed at low cost and high yield. In this driving method, the liquid crystal application potential written at the time of writing is maintained almost as it is, and therefore the controllability of the liquid crystal application potential is excellent, and thus the gradation controllability is excellent. Further, since the pulse width of the AC drive is the same as the selection time of one scanning signal line and the line inversion drive is performed, the surface flicker can be avoided.

[0007]

However, in the above-mentioned known additional capacitance type line inversion driving method, the TFT LCD is used.
It has not been possible to deal with the problems associated with high definition, large size, and multicolor of the panel, that is, the problem of reducing the scanning signal application time (writing time). In other words, when the definition of the TFT LCD is increased, the selection time per scanning signal line is shortened and the write margin is reduced. Therefore, if the write time is further shortened, various display defects such as luminance change and flicker will occur. However, in the known addition capacitance line inversion driving method, the writing time is shorter than the selection time per scanning signal line by a time corresponding to the scanning signal line delay time in order to normally apply the modulation signal. That is, when the known driving method is applied, the writing time is further reduced, so that the reduction of the writing rate is increased and the above-mentioned defects are caused. Further, when the TFT LCD is made larger, the delay time of the scanning signal line becomes longer, but in the known method, the writing time is shortened by an amount corresponding to the delay time, so that the above-mentioned reduction of the writing rate becomes a further problem. In addition, a frame rate control method (Frame Rate Control, hereinafter referred to as F
(Abbreviated as RC), it is necessary to increase the frame frequency and shorten the selection time per scanning signal line in order to reduce the partial flicker of the screen. The write rate decline becomes more serious.

Further, the known method is not sufficient for the reduction of the driving voltage of the driver IC and the gradation controllability, which are one of the original purposes of the known additional capacitance type line inversion driving method. That is, in the known method, when the first modulation voltage is applied after the writing is completed, the potentials of the preceding scanning signal line 317 connected to the pixel electrode 315 by the additional capacitance Cadd 314 and the counter electrode 316 connected by the liquid crystal capacitance Clc 313 are changed. Although changing, the potential of the scanning signal line 311 of its own stage connected by the source-gate capacitance Cgs318 of the TFT does not change, so that the potential change amount of the pixel electrode 315 decreases corresponding to these capacitance ratios. That is, after applying the modulation voltage, the pixel electrode 3 until the next writing is performed.
The potential (liquid crystal applied voltage) between 15 and the counter electrode 316 is smaller than the liquid crystal applied voltage immediately after writing. In other words, in order to obtain a desired liquid crystal applied voltage, there is a problem that the potential obtained by superimposing the signal potential of the video signal line 312 and the AC potential of the counter electrode 316 needs to be higher than the originally required potential. .. In addition, as described above, there is a change in the voltage applied to the liquid crystal after the writing is completed, and this depends on the ratio of each capacitance, so that it is easily affected by manufacturing variations and the like, and gradation control is difficult.

[0009]

To solve these problems, in the present invention, a scanning signal line, a thin film transistor having a gate electrode connected to the scanning signal line, and a drain electrode of the thin film transistor are connected. A video signal line, a pixel electrode connected to the source electrode of the thin film transistor, an additional capacitance element formed between the pixel electrode and the scanning signal line in the preceding stage of the scanning signal line, and the source electrode facing the source electrode. In a pixel including a liquid crystal capacitance element formed between an electrode and a pixel, a writing pulse and an AC voltage pulse having the same pulse width as that of the writing pulse are applied to the scanning signal line,
The rising and falling timings of the write pulse were shifted from the rising and falling timings of the AC voltage pulse. An AC voltage pulse was also applied to the counter electrode.

[0010]

Since the rising and falling timings of the writing pulse and the AC voltage pulse of the scanning signal line are different from each other, the modulation voltage can be applied without reducing the writing pulse width. Therefore, the write pulse width can be made the same as the selection time per scanning signal line, which reduces the selection time per scanning signal line due to high definition, large size, and multicolor, and reduces the writing margin. Even if the size of the driver IC is reduced, a decrease in the write rate can be avoided and at the same time the driver IC
It is possible to reduce the drive voltage of the. In addition, since the AC voltage pulse of the same voltage is always applied to the scanning signal lines of the self-stage and the preceding stage capacitively coupled to the pixel electrode and the counter electrode, there is no change in the liquid crystal applied voltage in the holding state. Can be reduced, and gradation controllability can be improved.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 shows a TFTL to which the driving method of the present invention is applied.
It shows an equivalent circuit of one pixel of CD. The gate electrode 319 of the TFT 310 is connected to the scanning signal line 311, the drain electrode 320 is connected to the video signal line 312, and the source electrode is the pixel electrode 315. Here, since the source and the drain change their roles during operation, the electrode connected to the video signal line is referred to as a drain electrode, and the pixel electrode side is referred to as a source electrode here for convenience. An additional capacitance Cadd314 is formed between the pixel electrode 315 and the preceding scanning signal line 317, and a liquid crystal capacitance Clc313 is formed between the pixel electrode 315 and the counter electrode 316. Besides this, although not intentionally formed, a gate-source parasitic capacitance Cgs 318 and a drain electrode 320 are provided between the gate electrode 319 and the pixel electrode 315.
Source-drain parasitic capacitance C between the pixel electrode 315 and the pixel electrode 315.
sd321 is formed. Of these, the source-drain parasitic capacitance Csd321 is very small in a normal pixel design and can be ignored. Only the additional capacitance Cadd314, the liquid crystal capacitance Clc313, and the gate-source parasitic capacitance Cgs318 should be considered as the capacitance connected to the pixel electrode. ..
The values of the additional capacitance Cadd, the liquid crystal capacitance Clc, and the gate-source parasitic capacitance Cgs are, for example, Cadd = 0.75 pF, C
It is set to a value such as lc = 0.20 pF and Cgs = 0.07 pF.

FIG. 6 is a diagram showing a state in which a plurality of pixels are arranged. The additional capacitance Cadd of each pixel is connected to the preceding scanning signal line, and all the scanning signal lines are driven by the peripheral scanning side driver 401. It should be noted that the pixels on the first line do not have preceding pixels, so the scanning signal line 402 (hereinafter referred to as the 0th line) that compensates for this
Is provided. Further, the video signal lines are drawn out to the upper and lower parts of FIG. 6 and driven by the peripheral image side drivers 403 and 404. The counter electrode is an electrode on the side of the color filter that normally faces the TFT substrate with the liquid crystal sandwiched therebetween. This is a common electrode 406 for all pixels, and the drive circuit 40
Driven by five.

FIGS. 1, 2 and 3 and 4 show drive waveforms according to the present invention. 1 and 2 show waveforms of odd frames, that is, positive polarity writing, and FIGS. 3 and 4 show waveforms of even frames, that is, negative polarity writing. 1 and 3 (a) are waveforms of the scanning signal line in the preceding stage of the pixel of interest, FIG. 1 and FIG. 3 (b) are waveforms of the scanning signal line of the pixel of interest, FIG. 3 (c) is the waveform of the counter electrode,
1 and 3 (d) are waveforms of the video signal line, and FIGS.
(E) shows the waveform of the pixel electrode. The waveform of the scanning signal line has three voltage levels. When the highest voltage Vgh is applied, the TFT is turned on and writing is performed. The write pulse width Tg is equal to the selection time per scanning signal line, and is about 35 μs when the number of scanning signal lines is 480 and the frame frequency is 60 Hz, for example. The write pulse is sequentially applied to each scanning signal line. The voltage is held when other voltages are applied, and is fixed to the lowest voltage Vgl when the conventional AC voltage pulse is not applied, whereas in the present invention, the lowest voltage Vgl and the intermediate voltage Vgm are alternately changed. It becomes the alternating voltage. The AC voltage pulse width and pulse interval are the same as the write pulse width Tg, and are applied in synchronization to all the scanning signal lines. An important point in the present invention is that the write pulse and the AC voltage pulse are shifted by a time Ts shorter than Tg. As shown in FIG. 1B, since the rising timing of the write pulse is delayed from the rising timing of the intermediate voltage pulse by Ts in the positive polarity writing, the voltage of the scanning signal line is from Vgm to Vgh at the rising of the writing pulse.
When the write pulse falls, the voltage of the scanning signal line is V
Change from gh to Vgl. Further, as shown in FIG. 3B, the rising timing of the write pulse during negative polarity writing is T than the falling timing of the intermediate voltage pulse.
Since it is delayed by s, the voltage of the scanning signal line changes from Vgl to Vgh when the write pulse rises, and the voltage of the scanning signal line when the write pulse falls changes from Vgh to Vgm.
1, FIG. 2, FIG. 3, and FIG. 4, the shift time Ts is about 1 of Tg.
/ 2, for example, Ts in the above example
= 17 μs. 1 and 3
As shown in (a), the scan signal lines in the preceding stage are written with the opposite polarities. That is, each line is inverted. An AC voltage pulse having the same voltage amplitude, pulse width, and pulse interval as the AC voltage pulse of the scanning signal line and synchronized with this is applied to the counter electrode. The video signal pulse of the video signal line is almost synchronized with the writing pulse, but is delayed from the writing pulse by the delay time τgd of the scanning signal line as usual.

The potential change of the pixel electrode due to such driving is as follows.

In FIG. 2E, the potential change of the pixel electrode at the time of positive polarity writing is shown by a solid line, and the voltage waveforms of the scanning signal line, the counter electrode and the video signal line are shown by a dotted line. First, time t
When a write pulse is applied to the scanning signal line of the previous stage at 1, the potential of the pixel electrode is V due to capacitive coupling by the additional capacitance Cadd.
Increase from 1 to V2. Next, at time t2, the potential of the counter electrode changes from Vcoml to Vcomh, and the scanning signal line of its own stage changes from Vgl to Vgm. Therefore, the liquid crystal capacitance Cl
The potential of the pixel electrode increases up to V3 due to the capacitive coupling due to c and the gate-source parasitic capacitance Cgs. Next, at time t3, the writing of the scanning signal line in the previous stage is completed, and the potential changes from Vgh to Vgm, the potential of the pixel electrode drops to V4. At this time, since the scanning signal line in the previous stage changes from Vgh to the intermediate potential Vgm, the potential V4 of the pixel electrode is higher than when the conventional driving method changes from Vgh to the lowest voltage Vgl. Therefore, the positive polarity writing that is subsequently performed becomes easy, and the writing rate can be increased.
At time t3, the potential of the scanning signal line of the previous stage is turned off, and at the same time, the scanning signal line of the self stage is changed from Vgm to Vgh and is turned on. As a result, positive polarity writing is started, the potential of the pixel electrode approaches from V4 to the signal voltage Vsigh of the video signal line, and time t5 after writing time Tg.
Almost V5 = Vsig. That is, here, it is assumed that sufficient writing of, for example, 95% or more is performed during the writing time Tg as designed normally. Since the AC voltage pulse of the counter electrode is synchronized with the AC voltage pulse of the scanning signal line and deviates from the writing pulse, the potential of the counter electrode changes from Vcomh to Vc at time t4 during writing.
Change to oml. At time t5, the voltage applied to the liquid crystal has a potential difference between Vsig and Vcoml. At this time, the liquid crystal applied voltage is a liquid crystal applied voltage component Vc (= (Vcomh-Vcoml) / 2) due to the AC voltage of the counter electrode and the liquid crystal applied voltage component Vs (= (Vsigh) due to the signal voltage of the video signal line.
-Vsigl) / 2), the driving voltage of the driver IC for the video signal line is reduced by the liquid crystal application voltage Vc × 2 corresponding to the AC voltage of the counter electrode. Further, since the writing time Tg is the same as the selection time per scanning signal line and does not decrease below this, the writing rate does not decrease even if the driving method of the present invention is applied. At the time t5, writing is completed and the potential of the scanning signal line is V
Change from gh to Vgl. At this time, the potential of the pixel electrode is V5 due to capacitive coupling by the gate-source capacitance Cgs.
To V6. This is called a so-called jump voltage, and the liquid crystal applied voltage decreases, but since there is a similar change on the negative polarity side as described later, the entire potential of the counter electrode is V5.
To V6 can be compensated by shifting in the direction of low voltage. Next, at time t6, the scanning signal lines of the preceding stage and the scanning stage of the self stage change from Vgl to Vgm, and the counter electrode is Vc.
Change from oml to Vcomh. These potential change amounts are equal, and all of the electrodes that are substantially capacitively coupled to the pixel electrode change in potential by the same amount, so that the pixel electrode also changes in potential by the same amount and reaches the potential of V7. Here, the write pulse and the AC voltage pulse are deviated by Ts, and since the values are large, for example, half the write time Tg, the waveform change times of the respective electrodes do not overlap, and the potential change of the scanning signal line and the pixel The changes in the electric potential of are exactly the same. Hereinafter, during the positive holding state, the potential of the pixel electrode is displaced between V6 and V7 according to the AC voltage change of the scanning signal line and the counter electrode. During this time, the voltage between the pixel electrode and the counter electrode, that is, the liquid crystal applied voltage does not change from the value after the voltage change due to the jump. Therefore, there is no change in the voltage applied to the liquid crystal due to manufacturing variations and the like, and the gradation controllability is excellent. Also,
Since the voltage between the pixel electrode and the scanning signal line of its own stage does not change during the holding state, the source-gate voltage of the TFT is the same as when the conventional AC voltage is not applied.
The Vth shift amount of T is the same as the conventional one. As for the gate voltage at the time of writing with positive polarity, it is necessary to obtain a sufficient writing rate within the writing time. For example, the gate voltage Vgh-Vsigh
Is set to about 4v, a sufficient writing rate can be obtained with ordinary amorphous silicon TFTs and pixel parameters.

The same change occurs in the negative polarity writing in FIGS. 3 and 4. That is, as shown in FIG. 4E, first, at time t1 ′, the potential of the pixel electrode in the positive holding state described above and having the potential V7 is written to the scanning signal line in the previous stage. When a pulse is applied, the potential of the pixel electrode increases from V7 to V8 due to capacitive coupling by the additional capacitance Cadd. Next, at time t2 ′, the potential of the counter electrode is Vcom.
It changes from h to Vcoml, and the scanning signal line of its own stage is Vgm
Changes from Vgl to Vgl, the potential of the pixel electrode changes to V9 due to capacitive coupling by the liquid crystal capacitance Clc and the gate-source parasitic capacitance Cgs. Next, at time t3 ', the writing of the scanning signal line in the previous stage is completed and the potential changes from Vgh to Vgl, and the potential of the pixel electrode drops to V10.
At time t3 ′, the potential of the scanning signal line of the preceding stage is turned off, and at the same time, the scanning signal line of the self stage is changed from Vgl to Vgh and turned on. As a result, the writing of the negative polarity starts, the potential of the pixel electrode approaches the signal voltage Vsigl of the video signal line from V10, and at time t5 'after the writing time Tg, almost V11 = Vsigl. Since the AC voltage pulse of the counter electrode is synchronized with the AC voltage pulse of the scanning signal line and deviates from the write pulse, the potential of the counter electrode changes from Vcoml to Vcom at time t4 'during writing.
Change to mh. At time t5 ', the voltage applied to the liquid crystal has a potential difference between Vsigl and Vcomh. At this time, similarly to the above-mentioned positive polarity, the liquid crystal applied voltage is the liquid crystal applied voltage component Vc (= (Vcomh-
Vcoml) / 2) and the liquid crystal applied voltage Vs (= (Vsig-Vsigl) / 2) due to the signal voltage of the video signal line
Driver of the video signal line I
The drive voltage of C is reduced. Further, the writing time Tg can be made equal to the selection time per scanning signal line, and it does not decrease below this. Therefore, even if the driving method of the present invention is applied, the writing rate does not significantly decrease. Time t5 '
Writing is completed and the potential of the scanning signal line changes from Vgh to Vg.
change to l. At this time, the potential of the pixel electrode is changed from V11 to V12 by capacitive coupling by the gate-source capacitance Cgs.
Changes to. Since this jump-in voltage has almost the same value as that on the positive polarity side, it is compensated by shifting the potential of the counter electrode in the low voltage direction by the amount corresponding to the change from V2 to V3. Next, at time t6 ', the scanning signal lines of the preceding stage and its own stage change from Vgm to Vgl, and the counter electrode changes from Vcomh to Vcoml. These potential changes are equal,
Since all of the electrodes that are capacitively coupled to the pixel electrode change in potential by the same amount, the pixel electrode also changes in potential by the same amount, and V
The potential becomes 13 (= V1). Here, the write pulse and the AC voltage pulse are deviated by Ts, and since the values are large, for example, half the write time Tg, the waveform change times of the respective electrodes do not overlap, and the potential change of the scanning signal line and the pixel The changes in the electric potential of are exactly the same. In the following, during the holding state of the negative polarity, the potential of the pixel electrode is V1 according to the AC voltage change of the scanning signal line and the counter electrode as in the case of the positive polarity.
Displace between 2 and V13. During this time, the voltage between the pixel electrode and the counter electrode, that is, the liquid crystal applied voltage does not change from the value after the voltage change due to the jump. Therefore, there is no change in the voltage applied to the liquid crystal due to manufacturing variations and the like, and the gradation controllability is excellent. The potential of the pixel electrode in the negative holding state is set so that the TFT maintains the OFF state even when the liquid crystal applied voltage is maximum. For example, in a pixel with a normal design, the jump-in voltage may be considered to be about 2 V or less.
If 1-Vgm (= Vsigl-Vgm) is set to about 5v, the TFT maintains the OFF state.

In the above embodiment, the shift time Ts is set to about 1/2 of Tg, but when it is exactly 1/2, the rising and falling of the write pulse and the AC voltage pulse are half of the conventional value, Tg /. Since a clock signal having a pulse width of 2 can be given, a driver circuit can be formed without increasing the number of clock signals as compared with the conventional case. The circuit configuration will be described later.

FIG. 7 shows a drive waveform of the embodiment when the shift time Ts is sufficiently smaller than Tg. 7A shows a driving waveform of the scanning signal line at the time of writing in the positive polarity, FIG. 7B shows a driving waveform of the scanning signal line at the time of writing in the negative polarity, and FIG. 7C shows a driving waveform of the counter electrode. The change in potential of the pixel electrode in this case is the same as that in FIGS. 1, 2, 3, and 4. However, in this embodiment, the time (t4 to t) until the potentials of the scanning signal line and the counter electrode change after the writing pulse falls.
5, or t6 to t7) is long. Therefore, it is suitable for a panel in which the delay times τgd and τgd ′ of the scanning signal lines are long. However, since the time (t3 to t4, or t5 to t6) from the change of the potential of the counter electrode to the end of writing is short, it is preferable that the delay of the potential of the counter electrode is short.

FIG. 8 shows a driving waveform of the embodiment when the shift time Ts is slightly smaller than Tg. FIG. 8A is a drive waveform of the scanning signal line at the time of positive polarity writing, FIG. 8B is a drive waveform of the scanning signal line at the time of negative polarity writing, and FIG. 8C is a drive waveform of the counter electrode. The change in potential of the pixel electrode in this case is the same as that in FIGS. 1, 2, 3, and 4. However, in the present embodiment, the time (t3 to t4, or t5 to t) from the change of the potential of the counter electrode to the end of writing.
Since 6) is long, it is suitable when the delay time τcd of the potential of the counter electrode is long. However, since the time (t4 to t5, or t6 to t7) until the potentials of the scanning signal line and the counter electrode change after the falling of the writing pulse is short, a panel having a short scanning signal line delay time is preferable. Is preferred.

FIG. 9 shows the intermediate potential pulse width of the scanning signal line and the high potential pulse width Tgm of the counter electrode, the intermediate potential pulse interval of the scanning signal line and the high potential pulse interval Tgl of the counter electrode.
Shows an example in which is different. 9A shows a driving waveform of the scanning signal line at the time of writing in the positive polarity, FIG. 9B shows a driving waveform of the scanning signal line at the time of writing in the negative polarity, and FIG. 9C shows a driving waveform of the counter electrode. The change in potential of the pixel electrode in this case is the same as that in FIGS. 1, 2, 3, and 4. Tgm,
Although Tgl is different from Tg, the sum of them is 2Tg. Let Ts be the time difference between the rise of the intermediate potential pulse and the rise of the write pulse at the time of positive polarity write,
gm is set to be larger than Ts and smaller than Ts + Tg. As described above, in this embodiment, the degree of freedom in setting the pulse waveform is high. If Tgm is larger than Tg, the delay time of the scanning signal line is particularly problematic because it takes a long time until the potentials of the scanning signal line and the counter electrode change on the negative side.
It is suitable when the delay time of the scanning signal line is long.

In the above embodiments, the counter electrode is synchronized with the AC voltage pulse of the scanning signal line, so that they can be driven by the same signal source.

10 and 11 show an embodiment in which the counter electrode is not synchronized with the AC voltage pulse of the scanning signal line. Here, only the waveform of positive polarity writing is shown as in FIGS. That is, FIG. 10A is the waveform of the scanning signal line in the preceding stage of the pixel of interest, FIG. 10B is the waveform of the scanning signal line of the pixel of interest, and FIG.
Is the waveform of the counter electrode, FIG. 10D is the waveform of the video signal line,
FIG. 11E shows the waveform of the pixel electrode. The difference from the above-described embodiment is that the voltage change of the counter electrode is Tg-Ts or less Tf from the voltage change of the scanning signal line AC voltage pulse.
It's just to get started. The change in potential of the pixel electrode in this case is shown in FIG. 11 (e) as in FIGS.
First, when a write pulse is applied to the scanning signal line in the previous stage at time t1, the potential of the pixel electrode increases from V1 to V2 due to capacitive coupling by the additional capacitance Cadd. Next, at time t2, the potential of the counter electrode changes from Vcoml to Vcomh, so that the potential of the pixel electrode increases to V3 due to capacitive coupling by the liquid crystal capacitance Clc. Next, at time 3, the scanning signal line of its own stage changes from Vgl to Vgm, so that the potential of the pixel electrode increases to V4 due to capacitive coupling due to the gate-source parasitic capacitance Cgs. Next, at time t4, when the writing of the previous scanning signal line is completed and the potential changes from Vgh to Vgm, the potential of the pixel electrode drops to V5. At the same time, the scanning signal line of its own stage changes from Vgm to Vgh, and is turned on.
It becomes a state. With this, writing of positive polarity starts,
The potential of the pixel electrode is from V5 to the signal voltage Vsi of the video signal line.
When the write time Tg approaches gh, at time t7, almost V6 = Vsight. The AC voltage pulse of the counter electrode changes from Vcomh to Vcoml at time t5 during writing. At time t7, the voltage applied to the liquid crystal is V
There is a potential difference between sigh and Vcoml. At the time t7, the writing is completed and the potential of the scanning signal line changes from Vgh to Vgl. At this time, the potential of the pixel electrode is equal to the gate-source capacitance C
It changes from V6 to V7 due to capacitive coupling by gs.
Next, at time t8, the counter electrode changes from Vcoml to Vcomh.
Changes to. At this time, the potential of the pixel electrode is equal to the liquid crystal capacitance Clc.
It increases to V8 due to capacitive coupling by. Next, time t
In FIG. 9, the scanning signal lines of the previous stage and the self stage change from Vgl to Vgm. Therefore, the potential of the pixel electrode is V due to the capacitive coupling by the additional capacitance Cadd and the parasitic capacitance Cgs between the gate and the source.
Increase to 9. Next, at time t10, the counter electrode is Vco
Since mh changes to Vcoml, it decreases to V10 due to capacitive coupling by the liquid crystal capacitance Clc. Next, time t1
Since the scanning signal lines of the previous stage and the self stage change from Vgm to Vgl, the potential of the pixel electrode is V by the capacitive coupling by the additional capacitance Cadd and the gate-source parasitic capacitance Cgs.
It decreases to 11 (= V7). Hereinafter, in the positive holding state, the potential of the pixel electrode is displaced between V7, V8, V9, and V10 according to the AC voltage change of the scanning signal line and the counter electrode. Here, a major difference from the above-described embodiments is that the liquid crystal applied voltage changes from the value immediately after writing. That is, during the period after the write pulse delay time between times t7 and t8, the liquid crystal applied voltage does not change from the value immediately after writing as in the above-described embodiments, but only the counter electrode changes between times t8 and t9. Therefore, the voltage applied to the liquid crystal decreases Va from the value immediately after writing. Since the scanning signal line is also changing from time t9 to time t10, the liquid crystal applied voltage becomes the same as the value immediately after writing. From time t10 to t
Since only the counter electrode changes during the period 11, the liquid crystal applied voltage increases Va from the value immediately after writing. Hereinafter, the same change is repeated. Therefore, when the holding state is averaged, the liquid crystal applied voltage becomes the same as the value immediately after writing. For this reason,
The same effects as those of the above-described embodiments are obtained. With respect to the negative polarity, the same change as above is obtained. Further, in the driving method of this embodiment, by setting the deviation time Ts to be small, a stable potential change can be obtained even if there is a delay of the scanning signal line and a delay of the counter electrode. Further, if the counter electrode is synchronized with the potential change of the video signal line, it is not necessary to increase the clock signal for driving the counter electrode.

It goes without saying that the positive polarity writing and the negative polarity writing are alternately performed in any of the above embodiments. However, the number of scanning signal lines of a normal display device is 40.
It is an even number such as 0, 480, 768, 780, and 1024. Therefore, when the alternating voltage pulse is continuously applied to all the scanning signal lines and the first line writing is performed immediately after the final line writing, the conversion between the positive electrode and the negative electrode for each frame cannot be performed. Therefore, according to the present invention, as shown in FIG. 12, the 0th pixel connected to the additional electrode of the pixel on the first line is connected.
By applying a similar voltage to the lines and setting the total number of lines to an odd number, it is possible to convert the positive and negative polarities for each frame. Of course, in addition to this, it is also possible to provide a blanking period after writing the final line and adjust during this time.

FIG. 13 shows, in block units, an embodiment of a scanning signal line driver circuit for giving a waveform of a scanning signal line according to the present invention. This circuit is almost the same as a normal video signal line driver circuit. That is, it is easy to obtain the scanning signal line waveform of the present invention by using the video signal line driver capable of outputting a voltage level of three or more values. In FIG. 13, the selector counts the falling edge of CL2 and generates the latch signal of the latch circuit (1). In the latch circuit (1), the data of the scanning signal line waveform stored in another storage circuit or the like or given from another control circuit is fetched. In the latch circuit (2), the latch circuit (1)
Data of CL1 and CL3 delayed by the deviation time Ts
Latch with. Next, the level shifter boosts the liquid crystal drive voltage, and the liquid crystal drive circuit selects and outputs one of the three levels. If the shift time Ts is 1/2 of the write time Tg, it can be driven by setting CL1 to Tg / 2, and the delay circuit and CL3 are unnecessary. In addition to this, it goes without saying that any configuration can be applied as long as it is a circuit that gives the waveform of the scanning signal line. Further, it is preferable that the shift time Ts is adjusted by providing a controller or the like with an adjustable mechanism section such as a variable resistance or a variable capacitance.

[0026]

As described above, according to the present invention, the driving voltage of the video signal line driver can be lowered by the pixel having the additional capacitance structure, so that the cost and power consumption of the video signal line driver can be reduced. Further, since finer rules can be applied to the driver manufacturing process than in the conventional case, the chip size of the IC does not increase even if the circuit configuration for full color is used.

Further, since the writing pulse of the scanning signal line and the alternating voltage pulse are deviated, it is not necessary to reduce the writing pulse width even if the alternating voltage pulse is applied and the additional capacitance type line inversion driving method is applied. Therefore, no display defects will occur even when applied to a high-definition, large-sized or multicolor TFT panel.

[Brief description of drawings]

FIG. 1 is a diagram showing a drive waveform and a potential change of a pixel electrode according to an embodiment of the present invention.

FIG. 2 is a diagram showing a drive waveform and a potential change of a pixel electrode according to an embodiment of the present invention.

FIG. 3 is a diagram showing a drive waveform and a potential change of a pixel electrode.

FIG. 4 is a diagram showing a drive waveform and a potential change of a pixel electrode.

FIG. 5 is an equivalent circuit diagram of one pixel.

FIG. 6 is a diagram showing a configuration example of a TFT LCD in which a plurality of pixels are arranged.

FIG. 7 is a drive waveform chart of another embodiment of the present invention.

FIG. 8 is a drive waveform chart of another embodiment of the present invention.

FIG. 9 is a drive waveform chart of another embodiment of the present invention.

FIG. 10 is a diagram showing drive waveforms and potential changes of pixel electrodes according to another embodiment of the present invention.

FIG. 11 is a diagram showing a driving electric waveform and a potential change of a pixel electrode in another example.

FIG. 12 is a diagram showing an overall image of drive waveforms according to an embodiment of the present invention for each line and each frame.

FIG. 13 is a diagram showing an example of a driver circuit that outputs a drive waveform according to an example of the present invention.

[Explanation of symbols]

310 ... TFT, 311, ... Scan signal line, 312 ... Video signal line, 313 ... Liquid crystal capacity, 314 ... Additional capacity, 315 ...
Pixel electrode, 316 ... Counter electrode, 317 ... Scanning signal line of previous stage, 318 ... Gate-source capacitance, 319 ... Gate electrode, 320 ... Drain electrode, 321 ... Source-drain capacitance, 401 ... Scan side driver, 402 ... No. 0 Line scanning signal lines 403, 404 ... Video signal line side driver,
405 ... Counter electrode drive circuit, 406 ... Counter electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Fumiaki Nemoto 3-10-2 Bentencho, Hitachi-shi, Ibaraki Hitachi Haramachi Electronics Co., Ltd.

Claims (5)

[Claims] 1. A scanning signal line, a thin film transistor having a gate electrode connected to the scanning signal line, a video signal line connected to a drain electrode of the thin film transistor, and a pixel electrode connected to a source electrode of the thin film transistor. ,
In a pixel including an additional capacitance element formed between the pixel electrode and a scan signal line in the preceding stage of the scan signal line, and a liquid crystal capacitance element formed between the source electrode and the counter electrode, a scan signal A write pulse and an AC voltage pulse having the same pulse width and pulse interval as this pulse width are applied to the line, and the rising and falling timings of the write pulse are at least the write pulse width from the rising and falling timings of the AC voltage pulse. A method for driving a liquid crystal display device, wherein the same alternating voltage pulse as the alternating voltage pulse is applied to the counter electrode for a shorter period of time. 2. A liquid crystal display device according to claim 1, wherein the time difference between the rising and falling timings of the write pulse and the rising and falling timings of the AC voltage pulse is approximately 1/2 of the write pulse width. Driving method. 3. The method of driving a liquid crystal display device according to claim 1, wherein the AC voltage pulse of the counter electrode and the AC voltage pulse of the scanning signal line are applied in synchronization with each other. 4. The AC voltage pulse of the counter electrode leads the AC voltage pulse of the scanning signal line by a time shorter than a time obtained by subtracting a shift time from a writing pulse width. Driving method of the liquid crystal display device. 5. The scanning signal line has three voltage levels, an intermediate voltage level to a high voltage write pulse voltage level when the positive polarity write pulse rises, and a high voltage when the positive polarity write pulse falls. Write pulse voltage level changes to a low voltage level, the negative write pulse rises from a low voltage level to a high voltage write pulse voltage level, and the negative write pulse falls to a high voltage write pulse voltage level. To a medium voltage level, a method for driving a liquid crystal display device.