JPH11281956A - Planar display device and driving method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to prevent the occurrence of flickering and DC bias impression on a liquid crystal without incurring a great increase in a circuit scale by providing a control part for controlling a pulse shape of a correction pulse. SOLUTION: A correction time adjustment circuit 6 as a pulse shape control means is built in a controller 5. This correction time adjustment circuit 6 is a circuit for supplying a control signal to adjust a pulse width of the correction pulse (correction time), and the pulse width of the correction pulse is manually adjustable. A tunneling voltage caused by parasitic capacitance is corrected by controlling the pulse width and amplitude of pulse shape, and variations in the tunneling voltage of each product can easily be corrected. Moreover, compared with a method of adjusting a picture element potential by a common voltage, an increase in the circuit elements can be restricted to the lowest necessary amount. Therefore, flicker occurrence is suppressed and a DC bias is prevented from being impressed on the liquid crystal without incurring a great increase in a circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display and a method of driving the same, for example, an active matrix type liquid crystal display and a method of driving the same.

[0002]

2. Description of the Related Art FIG. 5 is an equivalent circuit diagram of each display pixel in a conventional active matrix type liquid crystal display device.
A thin film transistor (hereinafter, referred to as TFT) is arranged near the intersection of the image signal line Xi and the scanning signal line Yj. This T
The source (or drain) electrode of the FT is connected to the image signal line Xi, and the gate electrode is connected to the scanning signal line Yj. The drain (or source) electrode is connected to the pixel electrode E. A liquid crystal capacitor Clc is formed by the pixel electrode E and the counter electrode C, and a liquid crystal capacitor Clc is formed by the pixel electrode E and the scanning signal line Yj-1 at the previous stage of the scan in order to suppress the fluctuation of the pixel electrode potential due to the leak current of the TFT. An auxiliary capacitance Cs electrically connected in parallel with the capacitance Clc is connected.

In such a configuration, a parasitic capacitance Cgs inevitably exists between the gate and source (or drain) of the TFT and between the image signal line Xi and the pixel electrode E. For this reason, for example, in the case of an n-type TFT, when the voltage of the scanning signal line Yj changes from the ON state to the OFF state, the charge held in the liquid crystal capacitance Clc is redistributed to the parasitic capacitance Cgs. Will also decrease. That is, a voltage lower by a certain voltage (hereinafter referred to as “penetration voltage”) than the originally written voltage is applied to the pixel electrode E.

Accordingly, V (vertical) inversion driving for inverting the polarity of the potential difference applied between the pixel / counter electrode for each adjacent vertical pixel line (column), or applying the voltage between the pixel / counter electrode for each adjacent pixel. In an active matrix type liquid crystal display device driven by H / V (horizontal / vertical) inversion in which the polarity of the potential difference is inverted, the voltage on the positive polarity side and the voltage on the negative polarity side are set in consideration of the penetration voltage. Is required to suppress flicker. Further, if the penetration voltage is continuously applied to the liquid crystal as a DC bias, the liquid crystal may be deteriorated, and the life thereof may be shortened.

With respect to such a penetration voltage caused by the parasitic capacitance Cgs, for example, in Japanese Patent No. 2662645, a gate voltage including a compensation pulse is added to a gate voltage supplied to a TFT to reduce the voltage drop. A driving system that compensates (hereinafter, a compensating driving system) has been proposed. FIG. 6 shows an example of a gate pulse in the compensation driving method. The gate pulse for turning on / off the TFT includes a scan pulse including a gate-on potential Vgh for turning on the TFT and a gate-off potential Vgl for turning off the TFT, and a compensation pulse. The penetration compensation voltage (hereinafter referred to as compensation voltage) Vgc of the compensation pulse is set to a potential lower than the gate-off potential Vgl, and a voltage drop due to the penetration voltage is compensated for by this voltage.

[0006]

In this compensation driving method, a value such as a parasitic capacitance Cgs is calculated in advance, and a compensation voltage Vgc is determined based on this value.
The value of the compensation voltage Vgc applied to the gate electrode was fixed. However, since the penetration voltage described above depends on values such as the liquid crystal capacitance Clc, the auxiliary capacitance Cs, and the parasitic capacitance Cgs that vary from product to product, the driving with a fixed voltage value causes the penetration voltage for all products. Was difficult to compensate for. Therefore, in such a compensation driving method, as shown in FIG. 7, by adjusting the voltage value of the common voltage (Vcom) applied to the counter electrode, the transmittance of the pixel can be changed between the positive polarity and the negative polarity. I was trying to make them equal. However, in the adjustment by the common voltage, it is necessary to adopt a circuit configuration capable of absorbing the variation of each liquid crystal panel. Therefore, there is a problem that the number of power supplies increases and the circuit scale increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a flat display device and a driving method thereof which can prevent the occurrence of flicker and the application of a DC bias to a liquid crystal without significantly increasing the circuit scale. .

[0008]

In order to achieve the above object, a flat display device according to the present invention comprises an image signal line and a scanning signal line which cross each other, and an intersection of the image signal line and the scanning signal line. A switch element arranged in the vicinity,
A display panel including a pixel electrode electrically connected to the switch element, and an electrode wiring layered through the pixel electrode and an insulating film to form an auxiliary capacitor; and scanning the image signal line with an image signal. A flat panel display device comprising: a scan pulse on a signal line; and a drive circuit unit for outputting a compensation pulse for compensating a potential change of the pixel electrode due to an influence of a parasitic capacitance caused by turning off the switch element on the electrode wiring. The driving circuit unit includes a control unit that controls a pulse waveform of the compensation pulse.

Further, a driving method of a flat panel display device according to the present invention is a method of driving a flat display device, comprising: an image signal line and a scanning signal line intersecting each other; and a switch element arranged near an intersection of the image signal line and the scanning signal line. A pixel electrode electrically connected to the switch element, an electrode wiring layered on the pixel electrode and an insulating film to form an auxiliary capacitor, and a counter electrode facing the pixel electrode. An image signal whose polarity is inverted with respect to a reference voltage at a predetermined period is applied to a signal line, a scanning pulse is applied to the scanning signal line, and a potential change of the pixel electrode is caused by a parasitic capacitance caused by turning off the switch element to the electrode wiring. In the method of driving a flat panel display device that performs image display by supplying a compensation pulse for compensating for the following, the same is applied when the image signal has a positive polarity and a negative polarity with respect to a reference voltage. During scale display, the amplitude or pulse width difference is substantially equal such that the compensation pulse between the counter electrode and the pixel electrode is characterized by comprising been adjusted.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment in which a flat display device and a driving method thereof according to the present invention are applied to a liquid crystal display device and a driving method thereof will be described.

First, the circuit configuration of the liquid crystal display device according to this embodiment will be described. FIG. 1 is a block diagram illustrating a circuit configuration of the liquid crystal display device. This liquid crystal display device generates a liquid crystal panel 1, an image signal line driving circuit 2 and a scanning line driving circuit 3 for driving the liquid crystal panel 1, and a signal for driving the liquid crystal panel 1, and generates a driving circuit And a controller 5 for supplying the power to the controller 5.

In the liquid crystal panel 1, a plurality of liquid crystal pixels as shown in FIG. 5 are arranged in a matrix, and the source (or drain) electrodes of the TFTs constituting each pixel are connected to the image signal lines X1, X2 for each column. .. Xn, and the gate electrodes are connected to the scanning signal lines Y1, Y2,. The drain (or source) electrode is a pixel electrode E
To form a liquid crystal capacitor Clc with a liquid crystal layer interposed between the pixel electrode E and the counter electrode C. This counter electrode C
Are commonly connected to the counter electrode drive circuit 4.

The scanning signal line driving circuit 2 is constituted by a shift register, and sequentially outputs a gate pulse to each scanning signal line. The image signal line driving circuit 3 includes a shift register, a D / A
It includes a converter and a latch circuit that temporarily samples an analog signal output from the D / A converter, and outputs an image signal to each image signal line.

It is assumed that V inversion driving or H / V inversion driving is performed on the liquid crystal panel 1 by the image signal line driving circuit 2 and the scanning line driving circuit 3.

[Embodiment 1] In FIG. 1, a controller 5 causes a scan signal line drive circuit 3 to operate a start pulse for controlling a shift register in the drive circuit and the shift register at a predetermined timing. Signal, a control signal for adjusting a pulse width (compensation time) of a compensation pulse described later, and the like, and a start pulse, a clock signal, an image signal, and the like to the image signal line driving circuit 2. Has been supplied. Further, the controller 5 has a built-in compensation time adjustment circuit 6 as pulse waveform control means. This compensation time adjustment circuit 6
This circuit supplies a control signal for adjusting the pulse width (compensation time) of the compensation pulse, and is configured so that the pulse width of the compensation pulse can be manually adjusted. Note that the compensation time adjustment circuit 6 can be constituted by a resistance member such as a variable resistor. Further, the pulse width may be controlled by an external software operation.

FIG. 2 is a timing chart showing the relationship between the gate pulse output from the scanning signal line driving circuit 3 and the pixel potential. Gate pulse Vg (n-1), Vg
(N) indicates the potential applied to the scanning signal lines Yj-1 and Yj in FIG. 5, respectively, and the pixel potential Vs indicates the holding potential between the pixel electrode E and the counter electrode C in FIG. . In the pixel potential Vs, Vs1 indicates a holding potential before the compensation time t1 is changed, and Vs2 indicates a holding voltage after the compensation time t1 is changed.

The gate pulse Vg (n-1) shown in FIG.
At Vg (n), the compensation time t1 of the compensation potential Vgc of the compensation pulse is controlled to t1 'by the control signal from the compensation time adjustment circuit 6 of the controller 5.

First, the gate pulse Vg (n-1) of the preceding stage
, When the gate-on potential Vgh changes to the compensation potential Vgc, the compensation voltage Vgc of the gate pulse Vg (n−1) changes to the gate-off voltage Vgl before the pixel potential Vs completely penetrates. (Gate pulse Vg (n-1) is changed from Vgc to V
gl), which occurs earlier than Vs1. For this reason, the pixel potential Vs increases by ΔVs. Similarly, the second push-up occurs earlier in the subsequent own-stage gate pulse Vg (n), so that the pixel potential Vs becomes Δ
Vs. Therefore, the finally held pixel potential Vs is a potential Vs higher than Vs1 by ΔVs.
s2.

Therefore, as shown in FIG. 3A corresponding to FIG. 7, when the voltages V1 and V2 applied to the liquid crystal are not equal between the positive polarity and the negative polarity during the same gradation display, the compensation time t1
Is controlled as t1 'as shown in FIG.
Since the characteristic of s changes from Vs1 to Vs2, FIG.
As shown in the figure, the voltage V applied to the liquid crystal in positive polarity and negative polarity
1, V2 can be made equal. When the pixel potential Vs is adjusted in this manner, the transmittance of the pixel can be made equal between the positive polarity and the negative polarity, so that the occurrence of flicker can be suppressed. This adjustment can be easily performed by the examinee by visually adjusting the variable resistance and the like.

When the compensation time adjusting circuit 6 for adjusting the pulse width (compensation time t1) of the compensation pulse is incorporated in the controller 5 as in this embodiment, the circuit scale can be made smaller than in the prior art. Therefore, the cost can be reduced.

[Second Embodiment] In the controller 5 of the second embodiment, the control signal for controlling the start pulse, the clock signal, and the value of the compensation voltage Vgc (pulse amplitude) is supplied to the scanning signal line driving circuit 3. Supplying. For this reason, the controller 5 shown in FIG. 1 incorporates a compensation voltage adjustment circuit (not shown) instead of the compensation time adjustment circuit 6. Other circuit configurations are the same as those of the first embodiment.
Hereinafter, the same parts will be described with the same reference numerals.

In this embodiment, the same gradation display is performed by controlling the compensation voltage Vgc of the gate pulse so as to cancel out (compensate) the penetration voltage (V1) as shown in the voltage waveform diagram of FIG. Sometimes, the voltages V1 and V2 applied to the liquid crystal are set to be equal between the positive polarity and the negative polarity. The adjustment of the voltage value of the compensation voltage Vgc can be performed by a compensation voltage adjustment circuit (not shown) built in the controller 5 of FIG. Specifically, the value of the compensation voltage Vgc is determined from the liquid crystal capacitance Clc, the parasitic capacitance Cgs, and the like, and the compensation voltage adjustment circuit adjusts the compensation voltage Vgc to a reference voltage value in advance based on this value. Then, the voltage value is adjusted so that flicker becomes less noticeable by the observer while an image having the same luminance is displayed over the entire screen.

According to this, similarly to the first embodiment, the voltages applied to the liquid crystal can be made equal between the positive polarity and the negative polarity during the same gradation display. Accordingly, the transmissivity of the pixel becomes equal between the positive polarity and the negative polarity, and the occurrence of flicker can be suppressed. In particular, in the second embodiment, the common voltage (counter electrode potential) may be a constant voltage value (there is no need to change the voltage value), so that the circuit configuration can be simplified. For example, the common voltage value is changed to the ground voltage value (0
V), the common circuit can be omitted. In this case, the shielding properties of the liquid crystal panel can be improved,
Furthermore, it is considered that it is also useful for radio wave measures.

[0024]

As described above, in the flat panel display and the method of driving the same according to the present invention, the pulse waveform of the compensation pulse is configured to be controllable, and the pulse width and amplitude of the pulse waveform are controlled. Thus, the penetration voltage caused by the parasitic capacitance is compensated, so that the variation of the penetration voltage for each product can be easily corrected. Further, the increase in the circuit configuration can be minimized as compared with the method of adjusting the pixel potential by the common voltage. Therefore, the occurrence of flicker can be suppressed and the application of a DC bias to the liquid crystal can be prevented without significantly increasing the circuit scale.

In particular, when a mechanism for controlling the pulse waveform of the compensation pulse is incorporated in the controller IC, the circuit scale can be reduced as compared with the conventional case, and the cost can be reduced.

In particular, when the amplitude of the compensation pulse is controlled, the common voltage can be set to a constant voltage value. For example, if the common voltage value is set to the ground voltage value (0 V), The circuit can be omitted. In this case, the shielding properties of the liquid crystal panel can be improved, and the liquid crystal panel is also useful as a measure against radio waves.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a liquid crystal display device according to an embodiment.

FIG. 2 is a timing chart illustrating a relationship between a gate pulse output from a scanning signal line driving circuit and a pixel potential.

FIGS. 3A and 3B are voltage waveform diagrams of a pixel potential in positive polarity and negative polarity.

FIG. 4 is a voltage waveform diagram showing a relationship between a gate voltage and a pixel potential.

FIG. 5 is an equivalent circuit diagram of each display pixel in a conventional active matrix liquid crystal display device.

FIG. 6 is a voltage waveform diagram showing an example of a gate pulse in a compensation driving method.

FIG. 7 is a voltage waveform diagram in a case where a pixel potential is adjusted by a common voltage.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal panel 2 Scanning signal line drive circuit 3 Image signal line drive circuit 4 Counter electrode drive circuit 5 Controller 6 Compensation time adjustment circuit

Claims (8)

[Claims] An image signal line and a scanning signal line that intersect each other, a switch element disposed near an intersection of the image signal line and the scanning signal line, and a pixel electrically connected to the switch element An electrode, a display panel including an electrode wiring stacked on the pixel electrode and an insulating film to form an auxiliary capacitor, an image signal to the image signal line, a scanning pulse to the scanning signal line, and a scanning pulse to the electrode wiring. A flat panel display device comprising: a driving circuit unit that outputs a compensation pulse for compensating a potential change of the pixel electrode due to an influence of a parasitic capacitance caused by turning off the switch element. The driving circuit unit includes a pulse of the compensation pulse. A flat panel display device comprising a control unit for controlling a waveform. 2. The flat display device according to claim 1, wherein the control unit adjusts an amplitude of the pulse waveform. 3. The flat display device according to claim 1, wherein the control unit adjusts a pulse width of the pulse waveform. 4. The display panel according to claim 1, wherein the display panel includes a counter electrode facing the pixel electrode, and the driving circuit supplies a counter electrode voltage fixed to the counter electrode. Flat panel display. 5. The flat display device according to claim 1, wherein the electrode wiring is another scanning signal line adjacent to the scanning signal line. 6. An image signal line and a scanning signal line crossing each other, a switch element disposed near an intersection of the image signal line and the scanning signal line, and a pixel electrically connected to the switch element. The signal line of the display panel, including an electrode, an electrode wiring laminated to the pixel electrode via an insulating film to form an auxiliary capacitor, and a counter electrode facing the pixel electrode, has a polarity with respect to a reference voltage at a predetermined cycle. The image display is performed by supplying an image signal which is inverted, a scan pulse to the scan signal line, and a compensation pulse for compensating a potential change of the pixel electrode due to the influence of a parasitic capacitance caused by turning off the switch element to the electrode wiring. The method of driving a flat panel display device according to claim 1, wherein the image signal has a positive polarity and a negative polarity with respect to a reference voltage. The driving method of the flat panel display difference, characterized in that the amplitude or pulse width substantially equal such that the compensation pulse is adjusted. 7. The method according to claim 6, wherein the inversion of the polarity of the image signal is performed for each scanning signal line. 8. The method according to claim 6, wherein the inversion of the polarity of the image signal is performed for each image signal line.