201250649 六、發明說明： 【發明所屬之技術領域】 【先前技術】 ’ _產品，特別是數位化之視訊 ίϊ if 般日常生活中所常見的產品。目 二是配合光電技術與半導體製造技術所 ^ j，、I為’例如液晶顯示器（Liquid Crystal 二：，、舌旦二由於液晶顯示器具有低電壓操作、無輻射 、’、月、里二以及體積小等優點，而成為近年來顯示器 研究的主要課題。 :般而言，液晶顯示器在開啟及關閉時的電源時序皆 有一定的規定，但液晶顯示器在某些運作狀態下，電源時 序會不符合規定’以致於液晶顯示器的運作會產生錯誤。 在液晶顯示器運作錯誤的情況下，液晶顯示器的時序控制 器（timing controller，TCON)會工作異常，以致於液晶顯 示器的源極驅動器（s〇urce driver)的會搁取錯像素資料， 進而使液晶顯示器顯示異常。 【發明内容】 本發明提供一種顯示裝置及其運作方法，可避免源極 驅動器擷取錯誤的像素資料而顯示異常。 201250649 元、時序控^及、;^ 括顯示面板、重置單 號及動器。重置單元接收資料致能信 行計數，以及在叶數、拿 ί為致能時依據時脈信號進 :，1器依據重置信號進行重置。源極驅動ΐ ，顯不面板及時序控制器，以依據 ^ 迷控制信號輸出多個像素電壓至顯示面板。 在本發明之一實施你中，_ 數電路及邏輯電路。偵例電路包括偵測電路、計 致能信號為致能時輸出':知广:身料致能信號，在資料 號，, 出通知仏唬。計數電路接收時脈信 信進行計數後輸出計數結果。邏輯電 路進行計數，並且路’以依據通知信脸制計數電 在本發明之-實施果為預設值時輸出重置信號。 數電路及決策電路；電路括開關電路、計 號，在資料致能信號為丄二=恤號及時脈信 接開關電路，以接M M L輪出時脈信號。計數電軸 進行計數後輸出計數結果。決策電 ΪΙΓί計數結果為預設值時輸出重置信號。 制電路。施例+ ’重置單元包括開關電路及控 致能接〜料致能信號及時脈信號，在資料 路ίίί致 時脈錢。控制電路據開關電 開關電路輸㈣時脈信號，並依額關電路輸 4 201250649 :時脈信號進行計數，並且在計數達預設值時輸出重置 號及=之致收資料_ 内部時脈信號及上述控制信號。及時脈信號產生上述 在本發明之一實施例令，上述 一内部時脈信號及-第二内部時脈虎包括一第 括—栓鎖控制信號。時序控制器““電:控:信f包 延遲電路、筮-知a & '、頻電路、第一相位 電路接收資料致H㈣f及第三相位延遲電路。除頻 進行除信號’除頻電路對時脈信號 =考==-相位延遲電轉接除頻電 早7^ w依據參考時脈信號產生第 置 行相位延遲後輸出，以乃㈣去$円。N夺脈b虎並於進 位延遲雷據重置信號進行重置。第二相 =電路’耦接除頻電路及重置單元，以依 : ϊίίϊ第二内部時脈信號並於進行相位延遲後輸出ί 及依據重置信號進行重置。第三 叛出以 路及重置單元，以+ l遲電路耦接除頻電 置早①以依據參考時脈信號產 延遲後輸出’以及依據重置信號進行重置= =第-相位延遲電路、第二相位二 遲電路的延遲相位彼此不同。 ㈣相位延 位延- =例中’第—相位延遲電路、第二相 式遲電路的延遲相位的關係如下列 5 201250649 延遲H位1遲電_延勒位< 第二相位延遲電路的 H第二相位延遲電路的延遲相位（式-）。 信號的頻中’參考時脈信號的頻率為時脈 禁能實施例中，重置單元於資料致能信號為 ，發日轉提出—雜稀置的運作方法，適用於 二驟的顯示裝置，顯示裝置的運作方法包括Ϊ列 =時:=能信號及時脈信號。在資料致能信號: 重置信號以數。在計數達預設值時產生 ^本發明之—實施财，其巾預設值為卜 轉，本發3讀__轉置及錢作方法， 在計騎賴，並且 此，時,»。 生重置^7虎以重置時序控制器。藉 置一 & I制器會在每-個晝面期間進行資料寫入之前重 信號^以Ϊ時序控制器輸出的内部時脈信號及栓鎖控制 資料而!:異㊁常’進而避免源極驅動器擷取錯誤的像素 舉ft讓本發明之上述特徵和優點能更明顯易懂，下文特 貫施例，並配合所附圖式作詳細說明如下。 6 201250649 【實施方式】 圖1為依據本發明一實施例的顯示裝置的系統示意 圖。請參照圖1，在本實施例中，顯示裝置100包括重置 單元110、時序控制器120、源極驅動器130、閘極驅動器 140及顯示面板15〇。重置單元110接收資料致能信號DE 及時脈信號CLK。時序控制器120接收資料致能信號de 及時脈信號CLK並耦接重置單元11〇。源極驅動器13〇耦 接時序控制器120及顯示面板150。閘極驅動器14〇耦接 時序控制器120及顯示面板150。 在本實施例中’顯示面板15〇是以雙閘極（Duai Gate) 的顯示面板為例，亦即顯示面板150的每一像素列（未繪 示）會對應兩條掃描線（未繪示），此時源極驅動器 會分開地擷取每一像素列的奇數像素資料及偶數像素資料 以刀別對應兩條掃描線（未繪示），因此時序控制器 會輪出兩個内部時脈信號（即第—内料脈信號丨。二及 第-内部時脈信號iCLK2)及-個栓鎖控制信號^，以 =源極驅動^ 13G擷取像素資料的依據。並且，源極驅 為130會依據所擷取的像素資料輸出多個像素電壓 。閘極轉II 14G紐於時序㈣$ 12Q :掃描信號sc錢_板15G，雜序開啟_序=出15夕〇 的母一個像素（未繪示）。 在八他實施例中’顯示面板i 50可以是單間極（Single ate)的顯不面板，而第一内部日夺脈信號icLK卜 内 辦脈信號lCLK2可整合為一内部時脈信號，甚至可省略 201250649 栓鎖控制信號la τ，此可依據本領域通常知識者的設計而 變動。 在本實施例重置單元110會在資料致能信號DE 為致能（例如為高準位）時依據時脈信號CLK進行計數， 並且在計數達一預設值（例如為1)時產生重置信號RS。 時序控制器120會依據資料致能信號de及時脈信號CLK 產生第一内部時脈信號iCLKl、第二内部時脈信號iCLK2 及栓鎖控制信號LAT，並依據重置信號rs進行重置。此 外，重置單元110於資料致能信號][)£為禁能（例如為低 準位）時重置計數。 換言之，重置單元110會在每一個畫面期間（即資料 致忐彳§號DE的兩個相鄰的上升緣之間）輸出一次重置信 號RS，並且重置信號RS會輸出於將像素資料（對應像素 電壓VP)寫入顯示面板15〇之前（即資料致能信號DE為 致能後的一預設時間内）。因此，時序控制器12〇會在每 :個畫面期間進行資料寫入之前重置一次，以使時序控制 器120輸出的第一内部時脈信號iCLK1、第二内部時脈信 號1CLK2及栓鎖控制信號lat的波形為正常，進而避免 源極驅動器130擷取錯誤的像素資料而顯示異常。 圖2A為圖1依據本發明—實施例的時序控制器的電 路不意圖。圖2B為圖1的資料致能信號DE、時脈信號 CLK、第-内部時脈信號lCLKl、第二内部時脈信號扣如 及栓鎖控制信號LAT的時序示意圖。請參照圖i、圖 及2B’在本實施例中’時序控制器12()包括除頻電路加、 8 201250649 第一相位延遲電路220 位延遲電路240。 第二相位延遲電路230 及第三相 除^電路21〇接收資料致能信號de及時脈 牙'頻電路21〇對時脈信號CLK進行除頻後產生表^ RCLK ’並且依據資料致能信號DE輪出參考時 #U RCLK。在本實施例中，除頻電路210對時脈信?# CLK，仃4倍除頻後產生參考時脈錢rclk，亦即參^ 時脈信號RCLK的頻率為時脈信號CLK的頻率的四&之 ’並且參考時脈信號RCLK會在資料致能信號DE為致 能且經過預設時間（即時間τυ後輸出。其中，預設時間 例如是將資料致能信號DE致能後至輸出像素資料 間。 ， 第一相位延遲電路220耦接除頻電路21〇及重置單元 110，以依據參考時脈信號RCLK產生第一内部時脈信號 lCLKl並於進行相位延遲後輸出，並依據重置信號RS進 行重置。第二相位延遲電路230柄接除頻電路21〇及重置 單元110，以依據參考時脈信號rCLK產生第二内部時脈 信號iCLK2並於進行相位延遲後輸出，並依據重置信號 RS進行重置。第三相位延遲電路240耦接除頻電路210 及重置單元110，以依據參考時脈信號RCLK產生栓鎖控 制信號LAT並於進行相位延遲後輸出，並依據重置信號 RS進行重置。其中’第一相位延遲電路220、第二相位延 遲電路230及第三相位延遲電路240的延遲相位的關係例 如如下列式一所示： 201250649 亦即，第一相位延遲電路、第二相位延遲電路及 相位延遲電路的延遲相位彼此不同。 〜 在本實施例中’例如第一相位延遲電路220的延遲 =為〇’第二相位延遲f路23G的延遲她為i個脈波 =間T2) ’第三相位延遲電路23()的延遲相位為3 5個脈 ;即時間T3)。並且，第一相位延遲電路22〇、第 =延，電路230及第三相位延遲電路24〇 ▲資料致能信號 .致能前（亦即為禁能）沒有輸出預設準位（在此以 低準位為例）而輸出非預設準位（在此以高準位為例）。 在資料致能信號1^為致能後，重置單元u〇開始計 。右重置單元110的計數為正緣觸發且預設值為卜則 f料致能信號DE為致能後時脈信號的第丨個正緣，重 置單几110會輸出重置信號RS’以致於第一相位延遲電路 2〇第—相位延遲電路23〇及第三相位延遲電路會重 置而輪出預設準位（即低準位）。藉此，由於第-相位延 遲電路220、第二相位延遲電路23〇及第三相位延遲電路 240會重置而輸出預設準位，因此可避免準位錯誤而使源 極驅動器130擷取錯誤的像素資料。 在時間τι後’除頻電路21〇會輸出參考時脈信號 RCLK至第一相位延遲電路22〇、第二相位延遲電路 及第—相位延遲電路24〇，並且第一相位延遲電路第 201250649 一相位延遲電路230及第三相位延遲電路24〇分別產生第 一内部時脈信號iCLK卜第二内部時脈錢iCLK2及检鎖 控制信號LAT並進行對應的相位延遲後依序輸出。 此外一，若第一相位延遲電路22〇、第二相位延遲電路 ^〇及第三相位延遲電路24〇在資料致能信號加為致能 前為輸出預設準位（例如為低準位），則第—相位延遲電 路220、第二相位延遲電路230及第三相位延遲電路24〇 在重置後㈣輸出預設準位，因料會料電路的運作。 圖3為圖1依據本發明一實施例的重置 意圖。請參照圖3,在本實施射，重置單以 測電路310、邏輯電路32〇及計數電路33〇。债測電路310 接收1料致能信號DE，在資料致能信號de為致能時輸出 通知1號NT至邏輯電路32〇。邏輯電路32 路310及計數電路，以在接收到通知信號财後控^ »十數電路330進行計數，亦即依據通知信號控制計數 ，路33〇進㈣數。計數電路33〇接收時脈信號CLK，且 輯電路32。進行計數後’會依據時脈信號CLK 進们十數並輪出計數結果CR。邏輯電路32〇在計數結 果⑶為預设值（例如為1)時輸出重置信號RS。其中， 偵利電路310可利用正反器來實現，例如d型正反器。 一立圖4為®1依據本發明另-實施例的重置單it的電路 不思圖°月參照圖4，在本實施例中，重置單元110”包括 開關電路410、斗献兩^ ^ 編㈣—i计數電路42G及決咸電路43G。開關電路 貝料欵能信號DE及時脈信號CLK，且在資料致 11 201250649 忐k號DE為致能時輸出所接收的時脈信號CLK (即時脈 “號CLK’）。計數電路420耦接開關電路41〇，以接收開 關電路410輸出的時脈信號CLK，，並依據開關電路41〇 輸出的時脈信號CLK’進行計數後輸出計數結果CR。決策 電路430耦接計數電路420，在計數結果CR為預設值（例 如為1)時輸出重置信號RS。其中，開關電路41〇可利用 電晶體來實現，例如NMOS電晶體。 圖5為圖1依據本發明又一實施例的重置單元的電路 示意圖。請參照圖5，在本實施例中，重置單元11〇,，，包 括開關電路510及控制電路52〇。開關電路510接收資料 致能信號DE及時脈信號CLK，且在資料致能信號DE為 致能時輸出所接收的時脈信號CLK(即時脈信號CXK，）。 控制電路520搞接開關電路51〇，以接收開關電路$ 1 〇輸 出的時脈信號CLK’，並依據開關電路51〇輸出的時脈信 號CLK’進行計數，並且在計數達預設值（例如為丨）時輸 出重置信號RS。其中，開關電路510可利用電晶體來實 現，例如NMOS電晶體。 依據上述’可彙整一運作方法以應用於上述顯示裝 置。圖6為依據本發明一實施例的顯示裝置的運作方法的 流程圖。請參照圖6，在本實施例中，會先接收資料致能 k號及時脈彳§號（步驟S610 )。在資料致能信號為致能時， 依據時脈信號進行計數’（步驟S620)，並且在計數達預 設值時產生重置信號以重置時序控制器（步驟S63〇)。以 及，在資料致能信號為禁能時重置計數（步驟S64〇)。其 12 201250649 ^^驟漏、s㈣及S64〇會重覆執行，以使時序控制 晝面㈣重置-次’並且上述各步驟的細節可參 狀上述實施例’在此則不再贅述。 ，上所述，本發明實施例的顯示裝置及其運作方法， 其於資料缝錢紐能雜據時脈錄騎計數，並且 f計數達預設值時產生重置信號以重置時序控制器。騎 lit序控制器會在每—個晝面期間進行資料寫入之前i 人，以使時序控制器輸出的第一内部時脈信號、第二 内4時脈錢及栓馳制健的波形為正常，進而 極驅動器擷取錯誤的像素資料而顯示異常。 ’、 雖然本發明已以實施例揭露如上，然其並非用 發明’任何所職術賴+财通 月之精神和範圍内，當可作些許之更動與潤= X月之保濩乾圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖圖1為依據本發明一實施例的顯示裝置的系統示音 ，2A為圖i依據本發明一實施例的時序控制器的電 略"不思圖。 圖2B為圖1的資料致能信號DE、時脈信號 内j時脈信號iCLKl、iCLK2及栓鎖控制信虹Αγ 示意圖。 守厅 圖3為圖1依據本發明一實施例的重置單元的電路示 13 201250649 意圖。 圖4為圖1依據本發明另一實施例的重置單元的電路 示意圖。 圖5為圖1依據本發明又一實施例的重置單元的電路 示意圖。 圖6為依據本發明一實施例的顯示裝置的運作方法的 流程圖。 【主要元件符號說明】 100 :顯示裝置 110、110’、110”、110，’’ ：重置單元 120 :時序控制器 130 :源極驅動器 140 :閘極驅動器 150 :顯示面板 210 :除頻電路 220 :第一相位延遲電路 230 :第二相位延遲電路 240 :第三相位延遲電路 310 :偵測電路 320 :邏輯電路 330、420 :計數電路 410、510 :開關電路 430 :決策電路 14 201250649 520.:控制電路 CLK、CLK’ ：時脈信號 CR :計數結果 DE :資料致能信號 iCLK卜iCLK2 :内部時脈信號 LAT :栓鎖控制信號 RCLK :參考時脈信號 RS :重置信號 ΤΙ、T2、T3 : B寺間 NT :通知信號 SC :掃描信號 VP :像素電壓 S610、S620、S630、S640 :步驟 15201250649 VI. Description of the invention: [Technical field to which the invention pertains] [Prior Art] ‘ _ products, especially digital video ϊ ϊ like products that are common in everyday life. The second is to cooperate with optoelectronic technology and semiconductor manufacturing technology, such as liquid crystal display (Liquid Crystal II:, tongue two due to liquid crystal display with low voltage operation, no radiation, ', month, second and volume Small advantages have become the main subject of display research in recent years. Generally speaking, the power supply timing of liquid crystal display is on and off when there are certain regulations. However, in some operating states, the power supply timing will not match. The regulation 'so that the operation of the liquid crystal display will produce errors. In the case of a wrong operation of the liquid crystal display, the timing controller (TCON) of the liquid crystal display will work abnormally, so that the source driver of the liquid crystal display (s〇urce driver) The invention will provide an abnormality in the liquid crystal display. The present invention provides a display device and a method for operating the same, which can prevent the source driver from erroneously capturing pixel data and display an abnormality. 201250649 yuan, timing Control ^ and , ; ^ display panel, reset single number and actuator. Reset unit Receive data enable signal line count, and according to the clock number when the number of leaves and ί are enabled: 1 is reset according to the reset signal. The source drive ΐ, the display panel and the timing controller are based on ^ The control signal outputs a plurality of pixel voltages to the display panel. In one implementation of the present invention, the _ number circuit and the logic circuit. The detection circuit includes a detection circuit, and the meter enable signal is output when enabled. : The body enable signal, in the data number, the notification 仏唬. The counting circuit receives the clock signal and counts the output and outputs the counting result. The logic circuit counts, and the way to count the electricity according to the notification face in the present invention - The implementation of the fruit is the preset value when the output reset signal. The number circuit and the decision circuit; the circuit includes the switch circuit, the meter number, the data enable signal is the second = shirt number, the pulse signal switch circuit, to connect the MML wheel The clock signal is output. The counting result is output after counting the electric axis. The reset signal is output when the counting result is the preset value. Circuitry. Example + 'Reset unit includes switching circuit and controllable connection The material enables the signal and the pulse signal, and the control circuit outputs the (four) clock signal according to the switch electric switch circuit, and according to the circuit output 4 201250649: the clock signal is counted, and the count is up. When the value is set, the reset number and the received data _ internal clock signal and the above control signal are output. The time pulse signal generates the above-mentioned one internal clock signal and the second internal clock in an embodiment of the present invention. The tiger includes a hexadecimal-latching control signal. The timing controller ""electric: control: signal f packet delay circuit, 筮-know a & ', frequency circuit, first phase circuit receiving data to H (four) f and third phase delay Circuit. In addition to the frequency to remove the signal 'frequency divider circuit for the clock signal = test == - phase delay power transfer frequency backup 7^ w according to the reference clock signal to generate the first line phase delay output, to (4) go $円. N takes the pulse and restarts the reset delay signal. The second phase = circuit 'couples the frequency dividing circuit and the reset unit to: ϊ ϊ ϊ the second internal clock signal and output the phase delay after the phase delay and reset according to the reset signal. The third rebel channel and the reset unit are coupled with the + l delay circuit to remove the frequency set 1 to output the delay according to the reference clock signal, and to reset according to the reset signal == the first phase delay circuit The delay phases of the second phase two-late circuit are different from each other. (4) Phase delay delay - = The relationship between the delay phase of the 'phase-phase delay circuit and the second phase-type delay circuit in the example is as follows. 5 201250649 Delay H-bit 1 late power_Yanle bit < Second phase delay circuit H The delay phase of the second phase delay circuit (formula-). In the frequency of the signal, the frequency of the reference clock signal is the clock-off disable embodiment. In the embodiment, the reset unit is in the data enable signal, and the operation method of the divergence is proposed, which is suitable for the display device of the second step. The operation method of the display device includes the queue = time: = energy signal and pulse signal. In the data enable signal: reset the signal to the number. When the count reaches the preset value, the invention is implemented - the implementation of the money, the default value of the towel is the transfer, the third read __transpose and the money method, in the ride, and this, when. Reset the ^7 tiger to reset the timing controller. Borrowing an & I will re-sign the internal clock signal and latch control data output by the timing controller before each data is written. The above-described features and advantages of the present invention will be more apparent and understood by the polar driver. The following detailed description is given in conjunction with the accompanying drawings. 6 201250649 [Embodiment] FIG. 1 is a system diagram of a display device according to an embodiment of the present invention. Referring to FIG. 1, in the embodiment, the display device 100 includes a reset unit 110, a timing controller 120, a source driver 130, a gate driver 140, and a display panel 15A. The reset unit 110 receives the data enable signal DE and the pulse signal CLK. The timing controller 120 receives the data enable signal de timely pulse signal CLK and is coupled to the reset unit 11A. The source driver 13 is coupled to the timing controller 120 and the display panel 150. The gate driver 14 is coupled to the timing controller 120 and the display panel 150. In the present embodiment, the display panel 15 is a dual-gate (Duai Gate) display panel, that is, each pixel column (not shown) of the display panel 150 corresponds to two scan lines (not shown). ), at this time, the source driver separately captures the odd pixel data and the even pixel data of each pixel column to correspond to two scan lines (not shown), so the timing controller will rotate two internal clocks. The signal (ie, the first-inner pulse signal 丨.2 and the first-internal clock signal iCLK2) and the latching control signal ^ are used as the basis for the source data to drive the pixel data. Moreover, the source driver 130 outputs a plurality of pixel voltages according to the captured pixel data. Gate turn II 14G Newton in timing (four) $12Q: scan signal sc money _ board 15G, miscellaneous open _ sequence = out 15 〇 mother one pixel (not shown). In the eighth embodiment, the display panel i 50 can be a single panel display panel, and the first internal day-of-day pulse signal icLK can be integrated into an internal clock signal, or even The 201250649 latch control signal la τ is omitted, which may vary depending on the design of those of ordinary skill in the art. In this embodiment, the reset unit 110 counts the clock signal CLK when the data enable signal DE is enabled (for example, a high level), and generates a weight when the count reaches a preset value (for example, 1). Set the signal RS. The timing controller 120 generates the first internal clock signal iCLK1, the second internal clock signal iCLK2, and the latch control signal LAT according to the data enable signal de clock signal CLK, and reset according to the reset signal rs. In addition, the reset unit 110 resets the count when the data enable signal [] is disabled (e.g., low level). In other words, the reset unit 110 outputs a reset signal RS during each picture period (ie, between two adjacent rising edges of the data § § DE), and the reset signal RS is outputted to the pixel data. (corresponding to the pixel voltage VP) before the display panel 15 is written (that is, a predetermined time after the data enable signal DE is enabled). Therefore, the timing controller 12 重置 is reset once before data writing is performed during each picture period, so that the first internal clock signal iCLK1, the second internal clock signal 1CLK2, and the latch control output by the timing controller 120 are controlled. The waveform of the signal lat is normal, thereby preventing the source driver 130 from capturing the wrong pixel data and displaying an abnormality. Figure 2A is a circuit diagram of the timing controller of Figure 1 in accordance with the present invention. 2B is a timing diagram of the data enable signal DE, the clock signal CLK, the first internal clock signal lCLK1, the second internal clock signal buckle, and the latch control signal LAT of FIG. Referring to Figures i, 2 and 2B', in the present embodiment, the timing controller 12() includes a frequency dividing circuit plus, 8 201250649 first phase delay circuit 220 bit delay circuit 240. The second phase delay circuit 230 and the third phase dividing circuit 21 receive the data enable signal, and the pulse pulse frequency circuit 21 除 divides the clock signal CLK to generate a table RCLK ' and according to the data enable signal DE #U RCLK when the reference is rotated. In this embodiment, the frequency dividing circuit 210 generates a reference clock rclk after dividing the frequency by 仃4 times, that is, the frequency of the clock signal RCLK is four of the frequency of the clock signal CLK. & and the reference clock signal RCLK is enabled after the data enable signal DE is enabled and after a preset time (ie, time τυ), wherein the preset time is, for example, the data enable signal DE is enabled to the output. The first phase delay circuit 220 is coupled to the frequency dividing circuit 21 and the reset unit 110 to generate the first internal clock signal lCLK1 according to the reference clock signal RCLK and output after phase delay, and according to the weight The signal RS is reset, and the second phase delay circuit 230 is connected to the frequency dividing circuit 21 and the reset unit 110 to generate the second internal clock signal iCLK2 according to the reference clock signal rCLK and output after the phase delay, and The resetting is performed according to the reset signal RS. The third phase delay circuit 240 is coupled to the frequency dividing circuit 210 and the resetting unit 110 to generate the latching control signal LAT according to the reference clock signal RCLK and output after phase delay, and according to Reset The RS is reset, wherein the relationship of the delay phases of the first phase delay circuit 220, the second phase delay circuit 230, and the third phase delay circuit 240 is as shown in the following Equation 1: 201250649, that is, the first phase delay circuit The delay phases of the second phase delay circuit and the phase delay circuit are different from each other. In the present embodiment, for example, the delay of the first phase delay circuit 220 = 〇 'the delay of the second phase delay f path 23G is i pulses Wave = Inter-T2) 'The delay phase of the third phase delay circuit 23() is 35 pulses; that is, time T3). Moreover, the first phase delay circuit 22, the third delay, the circuit 230, and the third phase delay circuit 24 ▲ ▲ data enable signal. Before the enable (that is, disable), no preset level is output (here The low level is an example) and the non-preset level is output (here, the high level is taken as an example). After the data enable signal 1^ is enabled, the reset unit u〇 starts counting. The count of the right reset unit 110 is a positive edge trigger and the preset value is the first positive edge of the enable clock signal, and the reset single chip 110 outputs a reset signal RS'. Therefore, the first phase delay circuit 2 〇 the first phase delay circuit 23 〇 and the third phase delay circuit are reset to rotate the preset level (ie, the low level). Thereby, since the first phase delay circuit 220, the second phase delay circuit 23, and the third phase delay circuit 240 are reset to output a preset level, the level error can be avoided and the source driver 130 can be mistakenly captured. Pixel data. After the time τι, the 'dividing circuit 21' outputs the reference clock signal RCLK to the first phase delay circuit 22, the second phase delay circuit and the first phase delay circuit 24, and the first phase delay circuit is 201250649. The delay circuit 230 and the third phase delay circuit 24 are respectively generated by the first internal clock signal iCLK, the second internal clock money iCLK2, and the lock control signal LAT, and sequentially output the corresponding phase delay. In addition, if the first phase delay circuit 22, the second phase delay circuit, and the third phase delay circuit 24 are output preset levels (eg, low level) before the data enable signal is enabled. Then, the first phase delay circuit 220, the second phase delay circuit 230, and the third phase delay circuit 24 are outputted at a predetermined level after the reset (four), and the operation of the circuit is expected. Figure 3 is a diagram of the resetting intent of Figure 1 in accordance with one embodiment of the present invention. Referring to Fig. 3, in the present embodiment, the single test circuit 310, the logic circuit 32, and the counter circuit 33 are reset. The debt measuring circuit 310 receives the material enable signal DE, and outputs the notification NT to the logic circuit 32〇 when the data enable signal is enabled. The logic circuit 32 has a path 310 and a counting circuit for counting the number of circuits 330 after receiving the notification signal, that is, controlling the count according to the notification signal, and the path 33 is incremented by (four). The counting circuit 33 receives the clock signal CLK and the circuit 32. After counting, it will enter the number of counts according to the clock signal CLK and rotate the counting result CR. The logic circuit 32 outputs a reset signal RS when the count result (3) is a preset value (for example, 1). The detection circuit 310 can be implemented by using a flip-flop, such as a d-type flip-flop. A vertical diagram 4 is a circuit for resetting a single according to another embodiment of the present invention. Referring to FIG. 4, in the present embodiment, the reset unit 110" includes a switch circuit 410 and a bucket. ^ Edit (4) - i counting circuit 42G and damaging circuit 43G. The switching circuit is capable of signal DE and time pulse signal CLK, and outputs the received clock signal CLK when the data is 11 201250649 忐k DE is enabled. (immediate pulse "No. CLK'). The counting circuit 420 is coupled to the switching circuit 41A to receive the clock signal CLK output from the switching circuit 410, and outputs a counting result CR according to the clock signal CLK' outputted by the switching circuit 41A. The decision circuit 430 is coupled to the counter circuit 420 to output a reset signal RS when the count result CR is a preset value (e.g., 1). Among them, the switching circuit 41 can be realized by a transistor, such as an NMOS transistor. FIG. 5 is a circuit diagram of the reset unit of FIG. 1 according to still another embodiment of the present invention. Referring to FIG. 5, in the present embodiment, the reset unit 11A, including the switch circuit 510 and the control circuit 52A. The switch circuit 510 receives the data enable signal DE and the pulse signal CLK, and outputs the received clock signal CLK (immediate pulse signal CXK,) when the data enable signal DE is enabled. The control circuit 520 is connected to the switch circuit 51A to receive the clock signal CLK' outputted by the switch circuit $1 ,, and counts according to the clock signal CLK' output by the switch circuit 51〇, and counts up to a preset value (for example, When 丨), the reset signal RS is output. Among them, the switching circuit 510 can be implemented by using a transistor, such as an NMOS transistor. According to the above, a method of operation can be applied to the above display device. Figure 6 is a flow chart showing a method of operating a display device in accordance with an embodiment of the present invention. Referring to FIG. 6, in the embodiment, the data enable k number and the time pulse number are received first (step S610). When the data enable signal is enabled, it is counted based on the clock signal' (step S620), and a reset signal is generated to reset the timing controller when the count reaches the preset value (step S63). And, the count is reset when the data enable signal is disabled (step S64). The 12 201250649 ^^jump, s(4), and S64〇 are repeatedly executed, so that the timing control (4) is reset-time and the details of the above steps can be referred to the above embodiment, and will not be described herein. As described above, the display device and the method for operating the same according to the embodiments of the present invention generate a reset signal to reset the timing controller when the data is counted by the clock and the count is up to a preset value. . The rider's sequence controller will write the data before each time, so that the first internal clock signal output by the timing controller, the second inner 4 clock money, and the waveform of the lock-up are Normal, and the polar driver picks up the wrong pixel data and displays an exception. 'Although the present invention has been disclosed above by way of example, it is not invented by the invention of any of the functions of Lai + Cai Tongyue, and when it is possible to make some changes and run = X months of protection This is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a system diagram of a display device according to an embodiment of the present invention, and FIG. 2A is a schematic diagram of a timing controller according to an embodiment of the present invention. 2B is a schematic diagram of the data enable signal DE of FIG. 1, the j-th clock signals iCLK1, iCLK2, and the latch control signal rainbow Α in the clock signal. Guard hall Figure 3 is a circuit diagram of the reset unit of Figure 1 in accordance with an embodiment of the present invention. 4 is a circuit diagram of the reset unit of FIG. 1 according to another embodiment of the present invention. FIG. 5 is a circuit diagram of the reset unit of FIG. 1 according to still another embodiment of the present invention. Figure 6 is a flow chart showing a method of operating a display device in accordance with an embodiment of the present invention. [Main component symbol description] 100: display device 110, 110', 110", 110, '': reset unit 120: timing controller 130: source driver 140: gate driver 150: display panel 210: frequency dividing circuit 220: first phase delay circuit 230: second phase delay circuit 240: third phase delay circuit 310: detection circuit 320: logic circuit 330, 420: counting circuit 410, 510: switching circuit 430: decision circuit 14 201250649 520. : Control circuit CLK, CLK': Clock signal CR: Counting result DE: Data enable signal iCLK Bu iCLK2: Internal clock signal LAT: Latch control signal RCLK: Reference clock signal RS: Reset signal ΤΙ, T2 T3 : Inter-Situ NT: Notification signal SC: Scanning signal VP: Pixel voltages S610, S620, S630, S640: Step 15