CN100448265C - Method and device for regulating horizontal synchronous signal and vertical synchronous signal - Google Patents
Method and device for regulating horizontal synchronous signal and vertical synchronous signal Download PDFInfo
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- CN100448265C CN100448265C CNB02130369XA CN02130369A CN100448265C CN 100448265 C CN100448265 C CN 100448265C CN B02130369X A CNB02130369X A CN B02130369XA CN 02130369 A CN02130369 A CN 02130369A CN 100448265 C CN100448265 C CN 100448265C
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Abstract
The present invention relates to a method and a device for adjusting horizontal synchronous signals and vertical synchronous signals, which is used for displays. The horizontal synchronous signals and the vertical synchronous signals are respectively provided with a plurality of pulses. The method firstly defines that a section of time before to after each pulse rise/fall edge in the vertical synchronous signals is a danger range; when the pulse rise/fall edges of the horizontal synchronous signals are in the danger range, the vertical synchronous signals are delayed; so the danger range is in the pulse rise/fall edges of the horizontal synchronous signals, and unstable and shaking pictures because of floating frequency can be effectively avoided.
Description
[technical field]
The present invention relates to a kind of method and device of adjusting horizontal-drive signal and vertical synchronizing signal, particularly a kind ofly be used for eliminating display picture beat level and vertical synchronizing signal method of adjustment and device with unstable situation.
[background technology]
Display must show for example 30 width of cloth pictures in one second, constitute consecutive image with the persistence of vision phenomenon that meets human eye, and each picture comprises the multi-strip scanning line respectively, and each scan line then comprises a plurality of pixels.So the picture signal that display receives from image processing system is the data of a succession of each pixel of correspondence.For allowing display confirm that each data answers pixel position corresponding, image processing system can be sent synchronously with picture signal and represent a scan line to open the beginning horizontal-drive signal of (claim not only line feed) and represent a width of cloth picture to open the beginning vertical synchronizing signal of (but also title skips).For purposes of illustration, following narration level and vertical synchronizing signal are that the rising edge (promptly being altered to the address of high level by low level) of peek word pulse is represented line feed respectively and skipped, so when display receives the rising edge of horizontal synchronization signal pulses, know that promptly it will receive the data of next bar scan line, and when receiving the rising edge of vertical synchronizing signal pulse, know the data that are received as next width of cloth picture thereafter, picture signal is correctly shown in regular turn.
Yet, during actual displayed, influenced by external factors such as interference, cross-talk, cause the frequency of horizontal-drive signal and vertical synchronizing signal to produce a little floating, frequency or increase or subtract.If by chance both rising edge time of occurrences are very nearly the same originally and be close to when overlapping,, can cause both successively to produce each other and beat in case frequency is floated.As Fig. 1, the transverse axis express time, horizontal-drive signal 11 almost is overlapped in same time location with the rising edge 111,121 of vertical synchronizing signal 12, and frequency is floated and can be caused the leading one-period T of rising edge of vertical synchronizing signal rising edge 121 relative horizontal-drive signals 111 or delay one-period T.If when N opens picture, horizontal-drive signal 11 rising edges 111 are after vertical synchronizing signal 12 rising edges 121, so be judged as first row of this width of cloth picture, and the N+1 that arrives is when opening, horizontal-drive signal 11 rising edges 111 are but before vertical synchronizing signal 12 rising edges 121, continuity is not shown by erroneous judgement from first line data of N width of cloth picture, change with second line data as first the row and present.If when N+2 opens, horizontal-drive signal 11 rising edges 111 float to again after vertical synchronizing signal 12 rising edges 121, can make in the picture of continuity, and first line data cuts in and out, and make image frame up and down, present unsettled shake and the image quality of deterioration demonstration.
On the contrary, as Fig. 2, if the rising edge 111 ' that the rising edge of vertical synchronizing signal 12 ' 121 ' falls behind horizontal-drive signal 11 ' greater than the risk range that may beat, even occurrence frequency floats, still can not produce the situation of picture shakiness.
Yet, this kind seriously jeopardized the factor payment of image display quality and give probability and fortune, not responsible rather.If can guarantee to keep between the rising edge 111 ', 121 ' of horizontal-drive signal 11 ' and vertical synchronizing signal 12 ' distance (promptly greater than risk range) regularly, can effectively check the unsteady phenomenon of frequency and cause the precedence relationship of 111,121 of two rising edges to change, avoid this phenomenon backward and forward with thorough solution foregoing problems.So, this case principal character promptly between two rising edges the time apart from less than risk range the time, widen distance between the two automatically, guarantee that both keep certain distance when safe, picture shakiness and the jitter conditions of fully avoiding frequency to float and cause.
[summary of the invention]
A purpose of the present invention is to provide a kind of method of adjusting horizontal-drive signal and vertical synchronizing signal, to reach the effect of avoiding automatically because of the unsteady picture shakiness that causes of frequency.
Another object of the present invention is to provide a kind of device of adjusting horizontal-drive signal and vertical synchronizing signal, the effect of distance when reaching that constant maintenance is safe between rising/trailing edge of guaranteeing level and vertical synchronizing signal.
So the method for adjustment horizontal-drive signal of the present invention and vertical synchronizing signal be used for display, and this horizontal-drive signal and vertical synchronizing signal has a plurality of pulses respectively, the method includes the steps of:
A) with the original vertical sync signal delay that is received, be equal to or greater than a display clock signal period T its time of delay, form one first vertical synchronizing signal, and postpone this first vertical synchronizing signal again and form one second vertical synchronizing signal, by between this original vertical synchronizing signal and this second vertical synchronizing signal rising/trailing edge the time apart from forming a risk range; And
B) if when the rising/trailing edge of this horizontal synchronization signal pulses is positioned at this risk range, then postpone this first vertical synchronizing signal, so that this risk range is positioned at after the rising/trailing edge of this horizontal synchronization signal pulses.
So a kind of device of adjusting horizontal-drive signal and vertical synchronizing signal is arranged in the display, the clock signal cycle of this display is T, and this horizontal-drive signal and vertical synchronizing signal have a plurality of pulses respectively, it is characterized in that this device comprises:
One dangerous pulse shaping circuit has:
One first delay circuit is used for receiving from the outside original vertical synchronizing signal and it is postponed one and exports after being equal to or greater than first time of delay of one-period T, with as one first vertical synchronizing signal;
One second delay circuit forms the output of one second vertical synchronizing signal after being used to receive this first vertical synchronizing signal and making it postpone for one second time of delay; And
One pulse generator, be used to receive this second vertical synchronizing signal and this original vertical synchronizing signal and corresponding between the rising/trailing edge of this two signal the time apart from forming a dangerous pulse;
One decision circuit, be used to receive output signal and this horizontal-drive signal of this danger pulse shaping circuit and judge whether the rising/trailing edge of this horizontal synchronization signal pulses is positioned at this danger pulse, and when judgement is positioned at this danger pulse, export a triggering signal; And
One delay loop is used to receive this first vertical synchronizing signal and is activated when receiving this triggering signal, so that this first vertical synchronizing signal postpones back output, causes this danger pulse to be positioned at after the rising/trailing edge of this horizontal synchronization signal pulses.
[description of drawings]
The present invention is described in detail below in conjunction with drawings and Examples:
Fig. 1 is a kind of horizontal-drive signal of routine and the oscillogram of vertical synchronizing signal, and wherein, a rising edge of horizontal-drive signal and the rising edge of vertical synchronizing signal occur simultaneously.
Fig. 2 is a kind of horizontal-drive signal of routine and the oscillogram of vertical synchronizing signal, and wherein, a rising edge of horizontal-drive signal lags behind the rising edge of vertical synchronizing signal.
Fig. 3 is the block diagram of a preferred embodiment of the present invention, and this preferred embodiment is incorporated in the display.
Fig. 4 is the detailed circuit diagram of preferred embodiment shown in Figure 3.
Fig. 5 is an oscillogram, an example of the input of first delay circuit and output signal in the key diagram 4.
Fig. 6 is an oscillogram, an example of the input of second delay circuit and output signal in the key diagram 4.
Fig. 7 is an oscillogram, an example of the input of pulse generator and output signal in the key diagram 4.
Fig. 8 is an oscillogram, an example of the input of decision circuit and output signal in the key diagram 4.
Fig. 9 is an oscillogram, another example of the input of decision circuit and output signal in the key diagram 4.
Figure 10 is an oscillogram, an example of the input of delay loop and output signal in the key diagram 4.
Figure 11 is the signal processing flow figure of Fig. 4 embodiment.
[embodiment]
Sv, original level synchronizing signal Ho, and original vertical synchronizing signal Vo to a display 3, and by the image processing circuit 5 in the display 3 according to the indication of signal Sv, Vo, Ho driving display 3 display image pictures.As previously mentioned, before the image processing circuit 5 of original vertical and horizontal-drive signal Vo, Ho input display 3, should guarantee certain at interval distance when safe of rising/trailing edge of two synchronizing signal Vo, Ho, with avoid taking place picture unstable with the situation of beating.Horizontal-drive signal of one embodiment of the invention and the adjusting device of vertical synchronizing signal 4 are arranged in the display 3, and are positioned at 5 of image processing system 2 and image processing circuits.Adjusting device 4 comprises a dangerous pulse shaping circuit 41, a decision circuit 42 and a delay loop 43.General original level and vertical synchronizing signal Ho, Vo are made of a plurality of pulse, and trigger image processing circuit 5 with rising edge (or trailing edge) and enter a new line or skip, for ease of explanation, suppose that hereinafter original level and vertical synchronizing signal Ho, Vo all carry out trigger action with its rising edge.
Among the corresponding respectively original vertical synchronizing signal of dangerous pulse shaping circuit 41 Vo behind the rising edge of each pulse a period of time form a dangerous pulse, defining a risk range, and the dangerous pulse of consecutive constitutes a dangerous pulse signal VP thus.Dangerous pulse shaping circuit 41 has one first delay circuit 411, one second delay circuit 412 and a pulse generator 413.
With reference to Fig. 4, first delay circuit 411 of present embodiment be by one or door (OR gate) 60, one resistance 61 and an electric capacity 62 constituted.Resistance 61 1 ends are electrically connected and are used to transmit original vertical synchronizing signal V
0 Circuit 22, the other end is electrically connected or two interconnective inputs 601,602 of door 60.Two inputs 601,602 of electrical connection of electric capacity 62 1 ends or door 60, other end ground connection.As shown in Figure 5, as original vertical synchronizing signal V
0During feed-in first delay circuit 411, utilize the late effect (being the capacitor charge and discharge effect) of electric capacity 62, make overall waveform one first time of delay of displacement backward, be not less than one-period T (cycle of the clock signal of display 3) and available variable resistor and electric capacity this first time of delay and set.So, or 603 outputs of door 60 output than original vertical synchronizing signal V
0The first vertical synchronizing signal V that postpones a period of time
S1
By aforementioned first and second delay circuit 411,412, the second vertical synchronizing signal V
S2Each rising edge fall behind original vertical synchronizing signal V
0Rising edge a period of time (adding for second time of delay first time of delay), and with this period be a risk range.Meaning is promptly as horizontal-drive signal H
0Come across this section in the period,, can make the picture instability, so the corresponding two vertical synchronizing signal V of pulse generator 413 difference in case frequency is floated
0, V
S2Rising edge between period form a dangerous pulse, use to detect as thereafter decision circuit.
This routine pulse generator 413 comprise an XOR gate (exclusive-OR) 67 and one and the door (AND gate) 68.XOR gate 67 1 inputs 671 are electrically connected output 653 second delay circuit 412 or door 65, and another input is electrically connected to and is used to transmit original vertical synchronizing signal V
0Circuit 22.Be electrically connected the output 673 of XOR gate 67 with an input 681 of door 68, another input 682 is electrically connected and is used to transmit original vertical synchronizing signal V
0Circuit 22.Cooperate Fig. 7, when XOR gate 67 receives the second vertical synchronizing signal V
S2With original vertical synchronizing signal V
0The time, output high level when having only in two signals one for high level, output low level then when both identical (promptly are all high level or are all low level) is so the second vertical synchronizing signal V
S2With original vertical synchronizing signal V
0Between level just can not be output the promptly corresponding second vertical synchronizing signal V simultaneously
S2With original vertical synchronizing signal V
0Rising edge (trailing edge) between delay the time two vertical synchronizing signal V
S2With original vertical synchronizing signal V
0Between level just can not be output the promptly corresponding second vertical synchronizing signal V simultaneously
S2With original vertical synchronizing signal V
0Rising edge (trailing edge) between delay period part, can form a series of pulse signal, and export to and the door 68 with original vertical synchronizing signal V
0Relatively, with the only corresponding two synchronizing signal V of output
0, V
S2Postpone the dangerous pulse of period between rising edge, and delete the pulse of corresponding trailing edge part, form dangerous pulse signal V at last
P Export decision circuit 42 to.Certainly, just as skilled in the art will understand, also can change the delay period of selecting between trailing edge herein into.
Because dangerous pulse signal V
PIn each dangerous pulse promptly represent original vertical synchronizing signal V
0In near each rising edge risk range, if horizontal-drive signal H
0Rising edge falls within therebetween, then may when frequency is floated the picture shakiness take place, otherwise then not have this doubt, so decision circuit 42 is promptly in order to determined level synchronizing signal H
0Rising edge whether fall within this scope.
This routine decision circuit 42 comprises one and postpones flip-flop (claiming D type flip-flop again) 69 and one or door 70.Or a door input 701 of 70 is electrically connected to the forward output Q that postpones flip-flop 69, and another input 702 is electrically connected to pulse generator 413 and output 683 door 68, to receive dangerous pulse signal V
P, 703 of outputs are electrically connected to the signal input part D that postpones flip-flop 69.The sequential input CLK that postpones flip-flop 69 is electrically connected to the circuit 23 that is used for transmit level synchronizing signal Ho, to receive horizontal-drive signal Ho.When the rising edge feed-in of horizontal-drive signal Ho, if postpone the dangerous pulse signal V of the signal input part D of flip-flop 69
PWhen by chance being dangerous pulse (high level), its forward output Q can export dangerous pulse (being high level), as a triggering signal V
TIn the feed-in delay loop 43, and because or door 70 feedback control, make this triggering signal always by value preserving output.
When decision circuit 42 receives the rising edge of horizontal-drive signal Ho, just the dangerous pulse signal V of feed-in this moment
POutput, as shown in Figure 8, if this moment the dangerous pulse signal V of feed-in just in time
P, then output becomes the triggering signal V of high level
T, and this signal meeting feedback input decision circuit 42, when making next rising edge feed-in of horizontal-drive signal Ho, decision circuit 42 is still kept high level output, and locking triggering signal V
TSo, in case when horizontal-drive signal Ho fell in the risk range, decision circuit 42 can continue the output triggering signal.On the contrary, receive the first vertical synchronizing signal V as delay loop 43
S1With triggering signal V
P, when receiving triggering signal V
TThe time, then make the first vertical synchronizing signal V
S1Ability input image processing circuit 5 causes dangerous pulse to be positioned at horizontal-drive signal H after postponing a period of time
0Rising edge after (as Fig. 2).On the contrary, if do not receive triggering signal V
TThe time, then allow the first vertical synchronizing signal V
S1Almost do not postpone promptly to export to image processing circuit 5.
The delay circuit 43 of present embodiment comprises a switch element 431 and one the 3rd delay circuit 432.As shown in Figure 4, this switch element 431 is transistors 71, and its base stage 711 is electrically connected to positive output end Q, 713 ground connection of its emitter that postpone flip-flop 65 through a resistance 72.The 3rd delay circuit 432 is similar with aforementioned first and second delay circuit 411,412, comprises a resistance 73, one or door 74 and one electric capacity 75.Resistance 73 1 ends be electrically connected to first delay circuit 411 or door 60 output 603, the other end are electrically connected to or two interconnective inputs 741,742 of door 74.Electric capacity 75 1 ends are electrically connected to or door 74 two inputs 741,742, the collector electrode 712 that the other end is electrically connected to transistor 71.
So, as triggering signal V
TNot during feed-in transistor 71, then transistor 71 not conductings, because the electric capacity 75 of the 3rd delay circuit 432 and unearthed, the delay feature of the 3rd delay circuit 432 is inoperative, the first vertical synchronizing signal V
S1Not delayed (this " not delayed " is meant without electric capacity 75 influences and causes tangible time delay, but because the first vertical synchronizing signal V
S1By the output of the 3rd delay circuit 432, so output signal and FD feed have a little time difference, 9ns for example, but because of very less than time of delay, and can ignore), promptly by or 74 output 743 export image processing circuit 5 to.In this embodiment, because the vertical synchronizing signal of feed-in image processing circuit 5 is the first vertical synchronizing signal V through 411 outputs of first delay circuit
S1So dangerous pulse can be considered with respect to the first vertical synchronizing signal V
S1A period of time after reaching before the rising edge.
On the contrary, if pulse signal V
TDuring feed-in transistor 71, transistor 71 is switched on, and electric capacity 75 can be through the collector electrode 712 of transistor 71 with emitter 713 and ground connection makes the 3rd delay circuit 432 performance delay features, as shown in figure 10, and the first vertical synchronizing signal V
S1Can postpone one section safety time (for example 90ns), and with the 3rd vertical synchronizing signal V
S3Export image processing circuit 5 to, make dangerous pulse be positioned at horizontal-drive signal H
0After the rising edge, make the vertical synchronizing signal V of input image processing circuit 5
S3With horizontal-drive signal H
0Rising edge between keep one period time interval that is not less than risk range.Thereby,, still can guarantee vertical synchronizing signal V even occurrence frequency floats
S3With horizontal-drive signal H
0The mutual alignment relation of rising edge can not change, situation does not backward and forward promptly take place, and then avoids the situation of picture shakiness to take place.
Thereby in the present embodiment, when display 3 began from image processing system 2 received signals, original vertical synchronizing signal Vo is the device 4 of this example of input earlier, with original level synchronizing signal H
0After the comparison process, just image processing apparatus 5 can be exported to, so the horizontal-drive signal H that image processing circuit 5 is received can be guaranteed
0The rising edge and the first vertical synchronizing signal V
S1Keep a safe distance between the rising edge, effectively avoid the float of floating and being caused because of frequency.So hereinafter, according to aforesaid element and correlation thereof, cooperate Figure 11 that signal processing flow in the present embodiment is explained.
In step 81, utilize dangerous pulse shaping circuit 41 to form corresponding to the first vertical synchronizing signal V
S1(the i.e. original vertical synchronizing signal V that postpones through first delay circuit 411
0) the dangerous pulse signal V of rising edge
P, promptly define the first vertical synchronizing signal V
S1The risk range of each rising edge.At this, allow original vertical synchronizing signal V earlier
0Form the second vertical synchronizing signal V through first and second delay circuit 411
S2, this second vertical synchronizing signal V
S2Fall behind original synchronizing signal V
0One period (promptly adding for second time of delay first time of delay) that the possibility occurrence frequency floats and causes danger, the XOR gate 67 of utilizing pulse generator 413 again is for the second vertical synchronizing signal V
S2With original vertical synchronizing signal V
0Between the place of level differences form pulse (this pulse is near the risk range risings/trailing edge), utilize at last with door 68 these pulse signals of deletion in corresponding to the pulse of trailing edge, with the dangerous pulse signal V of formation corresponding to rising edge
P
Secondly, in step 82, utilize decision circuit 42 to monitor horizontal-drive signal H
0Whether be positioned at dangerous pulse signal V
PEach dangerous pulse in, promptly whether fall within the risk range, if sometimes, then export triggering signal V
TInform delay loop 43.In this example, the delay flip-flop 69 in the decision circuit 42 receives dangerous pulse signal V
PAnd utilize horizontal-drive signal H
0As sequential, so can be at horizontal-drive signal H
0With dangerous pulse signal V
PThe simultaneous situation of pulse under (this situation meaning horizontal-drive signal H
0Be positioned at the first vertical synchronizing signal V
S1Risk range in), output triggering signal V
T(because being input as the dangerous pulse of high level) by input D, and enter in the step 83, start with the delay feature that makes delay loop 43.On the contrary, if through determined level synchronizing signal H
0Rising edge when not being positioned at risk range (i.e. Dui Ying dangerous pulse), then finish, and since the delay feature of delay loop 43 be not activated, so the vertical synchronizing signal of feed-in image processing circuit 5 is the first vertical synchronizing signal V
S1
In step 83, delay loop 43 receives triggering signal V
TAfter, can start its delay feature, the first vertical synchronizing signal V that order is passed through
S1Postpone a period of time (as 90ns), become the 3rd vertical synchronizing signal V
S3After export to again in the image processing circuit 5.In this example, because the switch element 431 (being transistor 71) of delay loop 43 receives triggering signal V
TThen can conducting, make electric capacity 75 ground connection of the 3rd delay circuit 432, and then make the first vertical synchronizing signal V
S1Can postpone a period of time, change to horizontal-drive signal H to make risk range
0Rising edge after, cause level and vertical synchronizing signal H
0, V
INThe certain safe distance of the constant maintenance of rising edge, to solve the problem of picture shakiness in the past.
Described before combining, utilize the present invention come prior detection level with vertical with signal H
0, V
S1Rising/trailing edge between the time apart from whether less than risk range, and less than risk range the time, then postpone the first vertical synchronizing signal V
S1Make it surpass risk range with lengthening time distance between the two, so can effectively avoid situation unstable because of the unsteady picture that causes of frequency and shake.
Though it should be noted that aforesaid embodiment is to postpone vertical synchronizing signal V
0Make its rising/trailing edge away from horizontal-drive signal H
0Rising/trailing edge, yet also can postpone horizontal-drive signal H
0Mode make between the two the time distance that keeps surpassing risk range.
Claims (9)
1. a method of adjusting horizontal-drive signal and vertical synchronizing signal be used for display, and this horizontal-drive signal and vertical synchronizing signal has a plurality of pulses respectively, it is characterized in that the method includes the steps of:
A) with the original vertical sync signal delay that is received, be equal to or greater than a display clock signal period T its time of delay, form one first vertical synchronizing signal, and postpone this first vertical synchronizing signal again and form one second vertical synchronizing signal, by between this original vertical synchronizing signal and this second vertical synchronizing signal rising/trailing edge the time apart from forming a risk range; And
B) if when the rising/trailing edge of the pulse of this horizontal-drive signal is positioned at this risk range, then postpone this first vertical synchronizing signal, cause this risk range to be positioned at after the rising/trailing edge of pulse of this horizontal-drive signal.
2. the method for claim 1 is characterized in that:
Step B) comprise a substep B-1), whether be positioned at this risk range in order to the rising/trailing edge that detects this horizontal synchronization signal pulses.
3. the method for claim 1 is characterized in that:
This method also comprises one and is positioned at this step B) after step C), continued to carry out in order to the delay of guaranteeing this first vertical synchronizing signal.
4. a device of adjusting horizontal-drive signal and vertical synchronizing signal is arranged in the display, and the clock signal cycle of this display is T, and this horizontal-drive signal and vertical synchronizing signal have a plurality of pulses respectively, it is characterized in that this device comprises:
One dangerous pulse shaping circuit has:
One first delay circuit is used for receiving from the outside original vertical synchronizing signal and it is postponed one and exports after being equal to or greater than first time of delay of one-period T, with as one first vertical synchronizing signal;
One second delay circuit forms the output of one second vertical synchronizing signal after being used to receive this first vertical synchronizing signal and making it postpone for one second time of delay; And
One pulse generator, be used to receive this second vertical synchronizing signal and this original vertical synchronizing signal and corresponding between the rising/trailing edge of this two signal the time apart from forming a dangerous pulse;
One decision circuit, be used to receive output signal and this horizontal-drive signal of this danger pulse shaping circuit and judge whether the rising/trailing edge of this horizontal synchronization signal pulses is positioned at this danger pulse, and when judgement is positioned at this danger pulse, export a triggering signal; And
One delay loop is used to receive this first vertical synchronizing signal and is activated when receiving this triggering signal, so that this first vertical synchronizing signal postpones back output, causes this danger pulse to be positioned at after the rising/trailing edge of this horizontal synchronization signal pulses.
5. device as claimed in claim 4 is characterized in that:
This first delay circuit comprises a resistance, an electric capacity and one or door, one termination of this resistance is received this original vertical synchronizing signal, the other end connects two interconnective inputs of this or door, one end of this electric capacity is electrically connected two inputs of this or door and other end ground connection, exports this first vertical synchronizing signal with the output from this or door.
6. device as claimed in claim 4 is characterized in that:
This second delay circuit comprises a resistance, an electric capacity and one or door, one termination of this resistance is received this first vertical synchronizing signal and the other end connects two interconnective inputs of this or door, one end of this electric capacity is electrically connected two inputs of this or door and other end ground connection, exports this second vertical synchronizing signal with the output from this or door.
7. device as claimed in claim 4 is characterized in that:
This pulse generator have an XOR gate and one and the door, one input of this XOR gate receives this original vertical synchronizing signal, another input of this XOR gate receives this second vertical synchronizing signal, one output that should be connected this XOR gate with an input of door, should be electrically connected this original vertical synchronizing signal with another input of door, to export dangerous pulse from this output with door.
8. device as claimed in claim 4 is characterized in that this decision circuit comprises one and postpones flip-flop and one or door, wherein,
Should or an input of door receive dangerous pulse, another input is connected to the positive output end of this delays flip-flop, should or an output of door connect the signal input part of this delay flip-flop;
The signal input part of this delay flip-flop connects the output of this or door to receive dangerous pulse, the sequential input of this delay flip-flop receives this horizontal-drive signal, and when the rising of this horizontal-drive signal/trailing edge feed-in, if the dangerous pulse signal of the signal input part of this delay flip-flop is dangerous pulse, the positive output end that then should postpone flip-flop is this danger pulse output, with as triggering signal.
9. device as claimed in claim 8 is characterized in that:
This delay loop comprises one and is subjected to the switch element and of this start trigger signal to be subjected to the 3rd delay circuit of this switch element control, the 3rd delay circuit is driven by this switch element and postpones this first vertical synchronizing signal and export, this switch element is a transistor, its base stage receives this triggering signal and grounded emitter, the 3rd delay circuit comprises a resistance, one electric capacity and one or the door, one termination of this resistance is received this first vertical synchronizing signal and the other end connects two interconnective inputs the 3rd delay circuit or door, and an end of this electric capacity is electrically connected two inputs the 3rd delay circuit or door and the other end connects this transistorized collector electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02130369XA CN100448265C (en) | 2002-08-16 | 2002-08-16 | Method and device for regulating horizontal synchronous signal and vertical synchronous signal |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02130369XA CN100448265C (en) | 2002-08-16 | 2002-08-16 | Method and device for regulating horizontal synchronous signal and vertical synchronous signal |
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| CN1476233A CN1476233A (en) | 2004-02-18 |
| CN100448265C true CN100448265C (en) | 2008-12-31 |
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| JP5251926B2 (en) * | 2010-06-16 | 2013-07-31 | セイコーエプソン株式会社 | Imaging apparatus and timing control circuit |
| KR101861723B1 (en) | 2011-12-20 | 2018-05-30 | 삼성전자주식회사 | Devices and method of adjusting synchronization signal preventing tearing and flicker |
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| CN1187084A (en) * | 1996-12-31 | 1998-07-08 | 三星电子株式会社 | Jitter compensating device for OSD |
| JP2000132137A (en) * | 1998-10-28 | 2000-05-12 | Matsushita Electric Ind Co Ltd | Vertical synchronous signal detecting circuit |
| CN1266331A (en) * | 1999-03-08 | 2000-09-13 | 明碁电脑股份有限公司 | Method and device for preventing OSD display area jumping on screen |
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2002
- 2002-08-16 CN CNB02130369XA patent/CN100448265C/en not_active Expired - Lifetime
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|---|---|---|---|---|
| US5436668A (en) * | 1991-07-02 | 1995-07-25 | Thomson Consumer Electronics, Inc. | Horizontal line counter stabilization in a video receiver |
| CN1139347A (en) * | 1995-03-24 | 1997-01-01 | 松下电器产业株式会社 | Speed variable playback device |
| JPH1013760A (en) * | 1996-06-26 | 1998-01-16 | Matsushita Electric Ind Co Ltd | On-screen display position correction device |
| CN1187084A (en) * | 1996-12-31 | 1998-07-08 | 三星电子株式会社 | Jitter compensating device for OSD |
| JP2000132137A (en) * | 1998-10-28 | 2000-05-12 | Matsushita Electric Ind Co Ltd | Vertical synchronous signal detecting circuit |
| CN1266331A (en) * | 1999-03-08 | 2000-09-13 | 明碁电脑股份有限公司 | Method and device for preventing OSD display area jumping on screen |
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| CN1476233A (en) | 2004-02-18 |
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