559858 A7 ___ B7 五、發明説明（1 ) 【發明所屬之技術領域】 本發明係關於低啓始値Μ〇S電晶體的電源備用電路 ，尤其是適用於爲實現低電源電壓作動將設定較低之 Μ〇S電晶體之啓始値（臨限値）電壓設定於較低之 M〇S型半導體積體電路的電源備用電路。 【先前技術】 大多數由CM〇S電路等所構成之裝置，具有作動模 式與備用模式。所謂備用模式，藉在未使用時將電路之流 入電流使其爲零，企圖成爲低消耗電力之模式。但是，在 這種情況，還是需要對裝置施加電壓。 例如，構成連接在目的裝置之控制用微電腦（個人電 腦）等，目的裝置停機時，爲存儲器之保護或其他電路之 控制，使微電腦爲開機狀態之情形頗多。此時，若使目的 裝置之電壓完全切斷時，自微型電腦之輸出電壓會流入目 的裝置，恐怕有破壞電路之危險。因此，在目的裝置待機 時，有施加電壓的必要。 以往，此種動作模式與備用模式之電力控制，藉由切 換施加之偏壓電壓之導通/非導通加以實現。圖1爲具有 偏壓切換功能之以往的電源備用電路構成例之顯示圖。在 圖 1 ，31 、2 即爲 PMOSFET。 p Μ〇S F E 丁 3 1之閘極連接到開關3之輸出端。 此開關3之一側之切換端子a連接到電源電壓V D D，另 一側之切換端子b接地。由此，當開關3連接到一側之切 ---------r-4-=---- 本纸張尺度適用中國國家榇準（CNS ) A4規格（21 OX 297公釐） 衣-- (請先閲讀背面之注意事項再填寫本頁)559858 A7 ___ B7 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a power backup circuit of a low-start MOS transistor, and is particularly suitable for setting a low value for low-voltage operation. The initial voltage (threshold voltage) of the MOS transistor is set at a lower power backup circuit of the MOS semiconductor integrated circuit. [Prior art] Most devices made up of CMOS circuits, etc., have an operating mode and a standby mode. The so-called standby mode attempts to become a low power consumption mode by reducing the current flowing into the circuit to zero when not in use. However, in this case, a voltage needs to be applied to the device. For example, when a control microcomputer (personal computer) is connected to the destination device, when the destination device is stopped, the protection of the memory or the control of other circuits causes the microcomputer to be turned on. At this time, if the voltage of the destination device is completely cut off, the output voltage from the microcomputer may flow into the destination device, and there is a danger that the circuit may be damaged. Therefore, it is necessary to apply a voltage when the destination device is on standby. Conventionally, the power control of such an operation mode and a standby mode is realized by switching on / off of the applied bias voltage. FIG. 1 is a diagram showing a configuration example of a conventional power backup circuit having a bias switching function. In Figure 1, 31 and 2 are PMOSFETs. The gate of p MOS F D 3 31 is connected to the output of switch 3. The switching terminal a on one side of the switch 3 is connected to the power supply voltage V D D, and the switching terminal b on the other side is grounded. Therefore, when the switch 3 is connected to one side --------- r-4-= ---- This paper size is applicable to China National Standard (CNS) A4 (21 OX 297 mm) ) Clothing-(Please read the precautions on the back before filling this page)
、1T 經濟部智慧財產场员工消t合作社 559858 A7 B7 五、發明説明（2 ) 換端子a側時p Μ〇S F E T 3 1爲非導通，連接到另一 側之切換端子b時ρ Μ〇S F Ε Τ 3 1爲導通。又， (請先閱讀背面之注意事項再填寫本頁) PM〇S F ΕΤ 3 1之源極連接到電源電壓VDD，洩極 連接到ρ Μ〇S F Ε Τ 2之閘極。 PM0SFET2之閘極連接到偏壓Vb i a s同時 ，藉由pM〇SFET3 1連接到電源電壓VDD。且， PM0SFET2之源極連接到電源電壓VDD，洩極連 接到目的裝置之電路4。而PM0SFET2爲導通時， 目的裝置之電路4即通上電源電壓VDD。 其次，說明作動。在作動模式，開關3連接到切換端 子a側時，ρ Μ〇S F E 丁 3 1爲非導通。由此， PM0SFET2之閘極施加偏壓Vb i a s，在 PM〇S F ET 2之閘極與源極之間產生電壓差，故 PM0SFET2爲導通。 一方面，於備用模式，當開關3連接到切換端子b側 時，PM0SFET3 1爲導通。由此， 經濟部智慈財產苟S工消贽合作社印繁 PM〇S F Ε T 2之閘極與源極施加相同電源電壓VD D ，對ρ Μ〇S F Ε T 2之施加的偏壓V b i a s切斷之。 此時，因閘-源間電壓V g s成爲零電位， PM0SFET2爲非導通。 由此，在以往之電源備用電路，偏壓之切斷乃控制 Ρ Μ〇S F Ε T 2之閘—源間電壓V g s爲零電位，使該 pM〇S F Ε T2爲非導通而實現之。 近年來，隨著半導體裝置之細微化技術之進步， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 559858 A7 B7 五、發明説明（3 ) M〇S F E T等之M〇S電晶體之通道長度大幅度地縮短 。此結果，由於耐壓等之關係即產生降低電源電壓V D D 之電準位之必要性。在此低電源電壓化之狀況下，爲維持 裝置之動作速度於高速，則降低Μ 0 S電晶體之啓始値電 壓V t h應付之。 但且，單純地降低Μ 0 S電晶體之啓始値電壓V t h ，會發生隨之而來Μ〇S電晶體之漏電流增大之問題。圖 2爲顯示Μ〇S電晶體之啓始値電壓V t h與漏電流I l之 關係之特性圖。於圖2，橫軸爲表示啓始値電壓V t h ( Μ〇S電晶體之閘極-源極間電壓V g s )，縱軸爲表示 漏電流I L ( Μ〇S電晶體之洩極電流I d )。 如圖2所示，Μ ◦ S電晶體之啓始値電壓爲較大之 V t h 1時，在閘極一源極間電壓V g s = 〇之偏壓切斷 情形下，大體上不產生漏電流。但是，Μ〇S電晶體之啓 始値電壓下降至V t h 2時，由於洩極電流I d之特性傾 向未變化，在閘極-源極間電壓V g s = 〇之偏壓切斷情 形下，會產生漏電流I k。且啓始値電壓V t h愈小漏電流 I L愈增大。 又，漏電流I L之發生處爲多數段存在之電路時，1段 的漏電流I 雖少，多段則成爲大漏電流。 本發明即爲解決此問題而成之，於使用低啓始値 Μ〇S電晶體的電源備用電路，能減低偏壓切斷時之漏電 流爲目的。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) •^^衣· -訂 經濟部智慧財员工消费合作社卬Κ 559858 A7 B7 五、發明説明（4 ) 【發明內容】 本發明之低啓始値Μ 0 S電晶體的電源備用電路其特 徵爲，乃是爲實現低電源電壓作動設定較低之Μ 0 S電晶 體之啓始値電壓之Μ〇S型半導體積體電路，對應作動模 式及備用模式之切換之裝置控制偏壓的施加之電源備用電 路，具備有連接到上述偏壓之第一 MO S電晶體，與藉由 上述第一 Μ 0 S電晶體之洩極電流路徑以導通/非導通地 切換對上述裝置控制上述偏壓的施加之第二Μ 0 S電晶體 〇 本發明之其他形態，其特徵爲實現低電源電壓動作將 設定較低之Μ〇S電晶體之啓始値電壓之Μ〇S型半導體 積體電路，對應作動模式及備用模式之切換控制偏壓的施 加之電源備用電路，具有閘極連接到上述偏壓同時，源極 連接到上述低電源電壓之第一 Μ〇S電晶體，與連接到上 述第一 Μ〇S電晶體之洩極之上述裝置，與洩極連接到上 述裝置同時，使源極接地，且對應閘極之輸入以進行導通 /非導通之第二Μ〇S電晶體。 本發明之其他形態，其特徵爲實現低電源電壓動作將 設定較低之MO S電晶體之啓始値電壓之Μ〇S型半導體 積體電路，對應作動模式及備用模式之切換控制偏壓的施 加之電源備用電路，具有閘極連接到上述偏壓同時，源極 連接到上述低電源電壓之第一 Μ 0 S電晶體，與一端接地 之上述裝置，以及連接到上述第一 Μ 0 S電晶體與上述裝 置之間，且對應閘極之輸入以進行導通/非導通之第二 子 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 559858 A7 B7 五、發明説明（5 ) Μ〇S電晶體。 本發明之其他形態，其特徵爲上述第二Μ〇S電晶體 是 nMOSFET。 【圖示簡單說明】 圖1爲以往電源備用電路之構成顯示圖。 圖2爲Μ〇S電晶體之啓始値電壓與漏電流之關係示 意特性圖。 圖3爲本實施形態之低啓始値Μ ◦ S電晶體的電源備 用電路構成例顯示圖。 圖4爲本實施形態之低啓始値Μ〇S電晶體的電源備 用電路其他構成例顯示圖。 【符號說明】1T Cooperative 559858 A7 B7 in the Intellectual Property Field of the Ministry of Economic Affairs 5. Description of the Invention (2) When the terminal a side is changed, p MOSFET 3 1 is non-conducting, when it is connected to the switching terminal b on the other side ρ Μ〇SF ET 3 1 is on. Also, (please read the precautions on the back before filling this page) The source of PM〇S F ET 3 1 is connected to the power supply voltage VDD, and the drain is connected to the gate of ρ ＭＯFS F Ε Τ 2. The gate of PM0SFET2 is connected to the bias voltage Vb i a s and at the same time, it is connected to the power supply voltage VDD through pMOSFET3 1. The source of PM0SFET2 is connected to the power supply voltage VDD, and the drain is connected to circuit 4 of the destination device. When PMOSFET2 is turned on, the circuit 4 of the target device is turned on with the power supply voltage VDD. Next, the operation will be explained. In the operating mode, when the switch 3 is connected to the switching terminal a side, ρ MOS F E D 31 31 is non-conducting. As a result, the bias voltage Vb i a s is applied to the gate of PM0SFET2, and a voltage difference is generated between the gate and source of PM0S F ET 2, so PM0SFET2 is turned on. On the other hand, in the standby mode, when the switch 3 is connected to the switching terminal b side, PM0SFET3 1 is turned on. As a result, the gate and source of the PM SF ET 2 are applied with the same power supply voltage VD D by the intellectual property of the Ministry of Economic Affairs and Industrial Cooperatives, and the bias voltage V bias applied to ρ ΜSF ET 2 Cut it off. At this time, since the gate-source voltage V g s becomes zero potential, PM0SFET2 is non-conductive. Therefore, in the conventional power backup circuit, the bias is cut off by controlling the gate-source voltage V g s of P MOS F ET 2 to zero potential, so that the p MOS F ET 2 is made non-conductive. In recent years, with the advancement of the miniaturization technology of semiconductor devices, this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 559858 A7 B7 V. Description of the invention (3) M0SFETs such as M0SFET The channel length of the crystal is greatly reduced. As a result, it is necessary to reduce the electric level of the power supply voltage V D D due to the relationship between the withstand voltage and the like. Under the condition of low power supply voltage, in order to maintain the operation speed of the device at a high speed, the initial voltage V t h of the M 0s transistor should be reduced to cope with it. However, simply reducing the initial voltage V t h of the M 0S transistor will cause a problem that the leakage current of the M0S transistor will increase. FIG. 2 is a characteristic diagram showing the relationship between the initial voltage V t h of the MOS transistor and the leakage current I l. In FIG. 2, the horizontal axis is the initial voltage V th (gate-source voltage V gs of the MOS transistor), and the vertical axis is the leakage current IL (the drain current I of the MOS transistor I d). As shown in Fig. 2, when the initial voltage of the M transistor is Vth 1 which is relatively large, no leakage will be generated in the case of the gate-source voltage V gs = 0. Current. However, when the initial voltage of the MOS transistor drops to V th 2, the characteristic tendency of the drain current I d has not changed, and in the case of the bias-off condition of the gate-source voltage V gs = 〇 , Will produce leakage current I k. And the smaller the initial voltage V t h is, the larger the leakage current I L is. When the leakage current I L is generated by a circuit having a plurality of stages, although the leakage current I in one stage is small, the leakage current I in a plurality of stages becomes a large leakage current. The present invention is made to solve this problem. The purpose is to reduce the leakage current when the bias voltage is cut off by using a power supply backup circuit with a low start-up MOS transistor. This paper size applies the Chinese National Standard (CNS) Α4 specification (210X297 mm) (please read the precautions on the back before filling this page) • ^^ ··-Order the Ministry of Economic Affairs ’Smart Financial Staff Consumer Cooperative 卬 Κ 559858 A7 B7 5 4. Description of the invention (4) [Summary of the invention] The power backup circuit of the low-start MEMS transistor of the present invention is characterized by the start of setting a low-level MOS transistor for low power supply voltage operation. The MOS-type semiconductor integrated circuit of ， voltage, a power supply backup circuit that controls the application of a bias voltage in response to the device switching between the operating mode and the standby mode, is provided with a first MOS transistor connected to the above bias voltage, and The drain current path of the first M 0 S transistor is switched on / off to switch the second M 0 S transistor to control the application of the bias voltage to the above device. In another aspect of the present invention, a low power source is realized. The voltage operation will set the starting voltage of the MOS semiconductor integrated circuit of the lower MOS transistor, corresponding to the power supply backup circuit that controls the application of the bias in the switching of the operating mode and standby mode The above device having the gate connected to the bias voltage and the source connected to the first MOS transistor of the low power supply voltage and the drain connected to the first MOS transistor is connected to the drain In the above device, the source is grounded and a second MOS transistor corresponding to the gate input for conducting / non-conducting. The other aspect of the present invention is characterized in that the low-voltage operation of the MOS type semiconductor integrated circuit that will set a lower initial voltage of the MOS transistor is corresponding to the switching control bias of the operating mode and the standby mode. The applied power backup circuit has the first M 0 S transistor with the gate connected to the above bias voltage, the source connected to the low power voltage, the device grounded to one end, and the first M 0 S power The second part between the crystal and the above device, and corresponding to the input of the gate for conducting / non-conducting (please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) Α4 specification (210 × 297 (Mm) 559858 A7 B7 V. Description of the invention (5) MOS transistor. Another aspect of the present invention is characterized in that the second MOS transistor is an nMOSFET. [Brief description of the diagram] FIG. 1 is a structural display diagram of a conventional power backup circuit. Fig. 2 is a graph showing the relationship between the initial voltage and leakage current of a MOS transistor. Fig. 3 is a diagram showing an example of a configuration of a power backup circuit of a low start-up 値 S S transistor of this embodiment. Fig. 4 is a diagram showing another configuration example of the power backup circuit of the low-start MOS transistor of the embodiment. 【Symbol Description】
1 nMOSFET1 nMOSFET
2 pMOSFET 3 開關 4 電路2 pMOSFET 3 switch 4 circuit
31 p Μ 0 S F E T a，b 切換端子 【實施方式】 以下，將本發明一實施形態參照圖示說明。 圖3爲本實施形態之低啓始値Μ〇S電晶體的電源備 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） "8 " —水-- (請先閱讀背面之注意事項再填寫本頁) 、1Τ 經濟部智慈財產苟員工消骨合作社卬災 559858 A7 _____B7_ 五、發明説明（6 ) 用電路構成例顯示圖。在圖3，與圖1所示構成要素相同 之構成要素即賦予相同之符號。 β ί m I lit I s n^l - - - - I - I (請先閲讀背面之注意事項再填寫本頁) 在圖 3 ，1 爲 nMOSFET ，2 爲 pMOSFET 。且nMOSFETl之啓始値電壓Vth比 pMOSFET2還大。 η Μ〇S F E T 1之閘極則連接到開關3之輸出端。 該開關3之一側切換端子a連接到電源電壓V D D，另一 側切換端子b接地。由此，開關3連接到一側切換端子a 側時，η Μ〇S F E T 1爲導通，連接到另一側切換端子 b側時，η Μ〇S F Ε Τ 1爲非導通。又， η Μ 0 S F Ε Τ 1之源極接地，洩極連接到目的裝置之電 路4。 Ρ Μ〇S F Ε Τ 2之閘極連接到偏壓V b i a s ，源 極連接到電源電壓V D D，洩極連接到目的裝置。如此， 於本發明實施形態，p Μ〇S F E T 2之閘極經常施加偏 壓Vb i a s 。偏壓之切斷並非藉使pM〇SFET2之 經濟部智总財產^員工消費合作^卬製 閘極-源極間電壓V g s爲零電位予以實現，而是藉使洩 極電流I d爲零電位實現之。 其次，說明動作。在作動模式，開關3連接到切換端 子a側時，n Μ〇S F E T 1爲導通。此時， Ρ Μ〇S F Ε Τ 2之閘極施加偏壓V b i a s ，在 Ρ Μ〇S F E T 2之閘極與源極之間發生電壓差，致 Ρ Μ〇S F Ε 丁 2爲導通。由此，自電源電壓V D D經 Ρ Μ〇S F Ε Τ 2 、電路4 、η Μ〇S F Ε Τ 1到達接地 本^：尺^適用中國國家標準（（^5)八4規格（210'/297公楚) ^ 559858 A7 __ B7 五、發明説明（7 ) 之路徑即爲導通。 另外，在備用模式，當開關3連接到切換端子b側時 ，η Μ〇S F E T 1即爲非導通。此時， pM〇S F ΕΤ2雖爲導通，自電源電壓VDD經 PM0SFET2 、電路 4 、nMOSFETl 到達接地 之路徑卻爲非導通，致洩極電流I d爲零電位。由此，對 於PM0SFET2之偏壓Vb i a s施加實質上已被切 如上，依據本實施形態，由於使洩極電流I d爲零電 位以實現切斷偏壓，且使p Μ〇S F E T 2之閘極-源極 間電壓V g s經常非零電位，故可抑制偏壓切斷時發生漏 電流（參照圖2 )。又，促使洩極電流I d爲零電位所需 開關元件之nMOSFETl ，比起PM0SFET2其 漏電流較少，故更可以減低漏電流之產生。 圖4爲本實施形態之低啓始値Μ 0 S電晶體的電源備 用電路其他構成例顯示圖。在圖4，與圖3所示構成要素 相同之構成要素即賦予相同之符號，並省略重複說明。 在圖3所示構成，將nM〇S F ΕΤ 1連接到電路4 與接地之間。此時，電路4與接地之間發生電位差八¥， 料想對電路之作動產生影響。針對，圖4所示構成，由於 將nMOSFETl連接到PM0SFET2與電路4之 間，且電路4直接連接接地。故此，可防止上述電位差△ V引起之對於電路4之不良影響。 又，在上述實施形態，就減低偏壓切斷時之漏電流發 -^6—--- -------^^衣-- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智¾財/i^s (工消t合作社印：¾ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 559858 經濟部智慧財產局員工消t合作社印—裝 Α7 Β7 五、發明説明（8 ) 生加以說明。針對，例如在偏壓施加時，藉對應所施加偏 壓控制p Μ〇S F E T 2之啓始値電壓越大，則亦可降低 偏壓的施加時之漏電流。 其他，以上說明之實施形態，只不過是實施本發明之 具體化一例示而已，不應藉此將本發明之技術性範圍加以 限定解釋。β卩，本發明可不脫離其精神、或其主要特徵以 各種形態加以實施。 本發明係如上述，將第一 Μ〇S電晶體之洩極電流加 以導通/非導通切換以控制偏壓之施加，致在偏壓切斷時 亦能避免第一 Μ 0 S電晶體之閘極-源極間電壓爲零電位 ，而可抑制在啓始値電壓設定爲較低之第一 Μ 0 S電晶體 發生漏電流。 又，依據本發明之其他特徵，將導通/非導通地切換 第一 Μ〇S電晶體之洩極電流路徑所用之第二Μ〇S電晶 體由nM〇S F ΕΤ構成，而比起以pM〇S F ΕΤ構成 時可降低漏電流。 【產業上之可利用性】 本發明係在使用低啓始値Μ〇S電晶體的電源備用電 路，對於偏壓切斷時促使降低漏電流頗爲有作用。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） — 衣-- (請先閱讀背面之注意事項再填寫本頁) J— I _ i 、1Τ31 p M 0 S F E T a, b switching terminal [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Figure 3 shows the power supply of the low-start MOS transistor of this embodiment. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm). &Quot; 8 " —Water-- (Please read first Note on the back, please fill out this page again), 1T Ministry of Economy, Intellectual Property, Employees, Bone Relief Cooperative, Disaster Relief 559858 A7 _____B7_ V. Description of Invention (6) The circuit structure is shown as an example. In FIG. 3, the same components as those shown in FIG. 1 are assigned the same reference numerals. β ί m I lit I s n ^ l----I-I (Please read the precautions on the back before filling out this page) In Figure 3, 1 is nMOSFET and 2 is pMOSFET. And the initial voltage Vth of nMOSFET1 is larger than pMOSFET2. The gate of η MOS F E T 1 is connected to the output of switch 3. One side of the switch 3 is connected to the power supply voltage V D D, and the other side of the switching terminal b is grounded. Therefore, when the switch 3 is connected to the switching terminal a on one side, η MOS F E T 1 is conductive, and when the switch 3 is connected to the switching terminal b on the other side, η MOS F E T 1 is non-conductive. The source of η M 0 S F E T 1 is grounded, and the drain is connected to circuit 4 of the destination device. The gate of P MOS F ET 2 is connected to the bias voltage V b i a s, the source is connected to the power supply voltage V D D, and the drain is connected to the destination device. As such, in the embodiment of the present invention, the gate of p MOS F E T 2 often applies a bias voltage Vb i a s. The cut off of the bias voltage is not achieved by the intellectual property of the Ministry of Economic Affairs of pMOSFET2 ^ employee consumption cooperation ^ the gate-source voltage V gs is zero potential to achieve, but the drain current I d is zero The potential is achieved. Next, the operation will be described. When the switch 3 is connected to the switching terminal a side in the operation mode, n MOS F E T 1 is turned on. At this time, a bias voltage V b i a s is applied to the gate of the P MOS F E T 2, and a voltage difference occurs between the gate and the source of the P MOS F E T 2, so that the P MOS F ET 2 is turned on. As a result, the self-power voltage VDD reaches the ground via P MOSSF ET 2, circuit 4, and η MOSSF ET 1 ^: Rule ^ Applicable to the Chinese National Standard ((^ 5) 8 4 specifications (210 '/ 297 (Gongchu) ^ 559858 A7 __ B7 5. The path of the invention description (7) is conductive. In addition, in the standby mode, when the switch 3 is connected to the switching terminal b side, ηMOSFET 1 is non-conductive. At this time Although pM0SF ET2 is on, the path from power supply voltage VDD through PM0SFET2, circuit 4, and nMOSFET1 to ground is non-conductive, causing the drain current Id to be zero potential. Therefore, the bias Vb ias of PM0SFET2 is applied It has been substantially cut as described above. According to this embodiment, the drain current I d is set to zero potential to realize the cut-off bias, and the gate-source voltage V gs of p MOSFET 2 is often non-zero potential. Therefore, leakage current can be suppressed when the bias is cut off (refer to FIG. 2). In addition, the nMOSFETl of the switching element required to cause the drain current Id to be at zero potential has less leakage current than PM0SFET2, so the leakage can be reduced even more. Generation of electric current. Fig. 4 shows the low starting 値 Μ 0 S of this embodiment. A diagram showing another configuration example of the power supply backup circuit of the crystal. In FIG. 4, the same components as those shown in FIG. 3 are given the same reference numerals, and repeated descriptions are omitted. In the structure shown in FIG. 3, nM0SF ET 1 Connected between circuit 4 and ground. At this time, a potential difference of 8 ¥ occurs between circuit 4 and ground. It is expected to affect the operation of the circuit. For the configuration shown in FIG. 4, the nMOSFET1 is connected between PM0SFET2 and circuit 4. And the circuit 4 is directly connected to the ground. Therefore, the adverse effect on the circuit 4 caused by the potential difference ΔV can be prevented. In addition, in the above embodiment, the leakage current at the time of bias cut-off is reduced-^ 6 ----- ------- ^^ 衣-(Please read the precautions on the back before filling out this page) Order the Ministry of Economic Affairs and Finance / i ^ s (Industrial Consumer Cooperative Cooperative Press: ¾ This paper size applies to Chinese national standards (CNS) A4 specification (210X297 mm) 559858 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the cooperative—A7 B7 V. Description of the invention (8). For example, when applying a bias voltage, apply the corresponding bias. Voltage control p MOSFET 2 The larger the initial voltage, the lower the leakage current when the bias voltage is applied. In addition, the embodiment described above is just an example of implementing the invention, and the technicality of the invention should not be taken by this The scope is limited and explained. Β 卩, the present invention can be implemented in various forms without departing from its spirit or its main features. The present invention is as described above, the drain current of the first MOS transistor is switched on / off Controlling the application of the bias voltage can prevent the gate-source voltage of the first M 0 S transistor from being zero potential when the bias voltage is cut off, and can suppress the voltage at the beginning to be set to a lower first voltage. Leakage current occurred in the M 0 S transistor. In addition, according to other features of the present invention, the second MOS transistor used to switch the drain current path of the first MOS transistor on / off is composed of nMOF ET, rather than pM0. SF ET can reduce leakage current. [Industrial Applicability] The present invention is a power backup circuit using a low start-up MOS transistor, which is effective for reducing the leakage current when the bias is cut off. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) — clothing-(Please read the precautions on the back before filling this page) J— I _ i 、 1Τ