TW557561B - Flip chip package structure - Google Patents

Flip chip package structure Download PDF

Info

Publication number
TW557561B
TW557561B TW091117856A TW91117856A TW557561B TW 557561 B TW557561 B TW 557561B TW 091117856 A TW091117856 A TW 091117856A TW 91117856 A TW91117856 A TW 91117856A TW 557561 B TW557561 B TW 557561B
Authority
TW
Taiwan
Prior art keywords
pads
bump
wafer
flip
bump pad
Prior art date
Application number
TW091117856A
Other languages
English (en)
Inventor
Kun-Ching Chen
Ho-Ming Tong
Chun-Chi Lee
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW091117856A priority Critical patent/TW557561B/zh
Priority to US10/249,369 priority patent/US6714421B2/en
Application granted granted Critical
Publication of TW557561B publication Critical patent/TW557561B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0295—Programmable, customizable or modifiable circuits adapted for choosing between different types or different locations of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09954—More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

557561 五、發明說明（1) 本發明是有關於一種晶片封裝基板，且特別是有關於 一種覆晶構裝基板，其可覆晶接合至一組具有相同之銲墊 排列方式’但具有不同之銲墊間距設計的多個晶片。 覆晶接合技術（Flip Chip Interconnect Technology，簡稱FC )主要係利用面陣列（area array ) 的方式’將銲塾（pad )配置於晶片之主動表面（active surface)上，並在各個銲墊上形成凸塊（bump)，接著 在將晶片翻覆（f 1 ip )之後，利用晶片上的凸塊分別對應 連接至承載器（carrier )上的接點（c〇ntact )，所以晶 片將可經由凸塊而電性連接承載器，並經由承載器之内部 線路而電性連接至外界的電子裝置。由於覆晶接合技術係 可適用於咼腳數（High Pin Count)之晶片封裝，並具有 縮小晶片封裝面積及縮短訊號傳輸路徑等優點，使得^曰 接合技術已被廣泛地應用在晶片封裝領域之中。目前a 7 應用覆晶接合技術之晶片封裝結構包括有覆晶球袼陣= (Flip Chip Ball Grid Array ’FCBGA)及覆晶 以⑴ip Chip Pin Gri“rra” FcpGA )等晶片封格裝？ 請參考第1圖，其繪示習知之一種覆晶球格 結構的剖示圖。覆晶晶片10 (以下簡稱晶片10) t封裝 面12係配置有多個銲墊14，用以作為晶片1〇之=動表 端，而銲墊14上更分別配置有一凸塊3〇，用以又二，出入 晶構裝基板20 (以下簡稱基板2〇 )之頂面21二|連接覆 (―痛“其中，基板20主要塊塾 受你由夕層圖案化之導
9247twf.ptd 第5頁 557561 五、發明說明（2) 線層2 3及多層絕緣層2 6所相互交錯疊合而成，並可利用多 個導電插塞28分別貫穿絕緣層26，用以電性連接二層或二 層以上的導線層23，其中導電插塞28包括鍍通插塞 (Plating Through Hole，PTH ) 2 8a 及導通插塞（via ) 2 8b，兩者依照製程之不同，而有孔徑尺寸上的差異。另 外’基板20之頂面21上的凸塊墊24係由這些導線層23之最 頂層者（即導線層23a )所構成，並利用銲罩層（s〇ider Mask)27a來保護導線層23a，同時暴露而定義出由導線層 23a所構成之凸塊墊24。 請同樣參考第1圖，基板2〇之底面22更配置有多個銲球 墊（ball pad ) 25，其係由這些導線層23之最底層者（即 導線層23b)所構成，並同樣利用一圖案化之銲罩層27b來 保護導線層23b，同時暴露而定義出導線層23b之銲球墊 25，而銲球墊25上更可配置銲球（BaU ) 4〇 構，用以與外界之其他電子裝置相互電性連接 $電、: 片^之銲塾U將可經由凸塊3Q，而電性及機械性連接至= ‘塞2^2凸塊？24 ’再經由各層導線層23及各個導電 μ二々曰、冓成之内部線路，而向下繞線至基板20之底面22 電社才’最後經由輝球墊25上之銲球40等或其他導 電、u冓，而電性及機械性連接至下一層級（η 7:、：導 之電子裝置，例如印刷電路板（pcB) 。 vel ) 樣參考第1圖，當晶片10之面積縮小時，晶片心 ί干墊1 4的間距將相對縮小， 日日片1 0之 位置必須分別斟雁而鍺卜， 基板 所有凸塊塾24的 刀別對應面積縮小之晶㈣ 们
557561 五、發明說明（3) 置，如此一來，使得基板2〇必須重新設計，特 之所有凸塊墊24的位置必須重新設計，因而盔=基板20 晶片1 0之覆晶封裝的製程時間。 /有效縮短 有鑑於此，本發明係提供一種覆晶構裝基 晶接合至一組具有相同之銲墊排列方式，但且其可覆 塾間距設計的多個晶片，使得這些晶片銲 ?裝基板，故可省略覆晶構裝基板之設計步驟，=一3晶 晶片於覆晶封裝之時程。 ^鄉，因而縮短 基於本發明之上述目的，本發明提出一稽薄曰 板，適用於覆晶接合至一第一曰種覆阳構裝基 一，其中第一晶片具有一笛7 ^ 一第二晶片其中之 且這些第一銲墊係配置於第 2面及多個第一銲墊， 1二主動表面及多：動ί:此：第二晶片具有 晶構裝基板包括有圖荦：之二主動表面。此覆 合；至少-絕緣層導序相互疊 這些導線層，ϋ與這此導績f -導線層之間，用以隔離 其中此覆晶構裝之，J:M用以電性連接該些導電層。 凸換執，【因—鬼塾群刀別具有一第一凸塊塾及一第二 相互電性連接，m!:第一凸塊墊及第二凸塊墊係 係分別對應於第二晶片=楚且這些第二凸塊塾之位置 曰曰片之些第二銲墊的位置。
第7頁 557561 五、發明說明（4) 為讓本發明之上述目的、特徵和優點能明顯易懂，下 文特舉一較佳實施例，並配合所附圖示，作詳細說明如 下： 圖式之標示說明 10 晶片 12 主動表面 14 辉塾 20 覆晶構裝基板 21 頂面 22 底面 23、23a、23b :導線層 24 ： 凸塊墊 25 ·· 鮮球塾 26 ： 絕緣層 2Ί、 27a、27b :銲罩層 28 ·· 導電插塞 28a : :鍍通插塞 28b : :導通插塞 30 ： 凸塊 40 ： 鮮球 100a •第一晶片 100b • 第二晶片 102a ••第一主動表面 102b :第二主動表面
9247twf.ptd 第8頁 557561 五、發明說明（5) 104a :第一銲墊 104b ··第二銲墊 2 0 0 :覆晶構裝基板 202 :頂面 2 0 4 ··凸塊墊群組 204a :第一凸塊墊 204b ·第一凸塊塾 2 0 6 :導線 3 0 0 :凸塊墊群組 3 0 2 :凸塊墊 3 0 4 :導線 較佳膏施例 本發明之覆晶構裝基板係可覆晶接合至多個具有相同 鮮塾排列方式’但具有不同銲墊間距之凸塊墊的晶片。 本發明之覆晶構裝基板主要係由圖案化之多層導線層 及多層絕緣層相互交錯疊合而成，並利用多個導電插塞分 絕緣層’而電性連接二層或二層以上的導線層，且 i ΐ八32 ί頂層者係構成多個凸塊墊，使得晶片之銲 塾，再經由覆晶構裝裳基板之這些凸塊 有關於本發明之覆晶構裝基板的結構板圖 557561 五、發明說明（6) 及其相關之說明，於此不再詳加贅述。 請參考第2圖，其繪示兩種具有相同銲墊排列方式，但 不同鮮塾間距之晶片的局部底視圖。第一晶片i 〇〇a具有〆 第一主動表面102a (如第1圖所示之主動表面12)及多個 第一銲墊104a (如第1圖所示之銲墊14)，其中第一主動 表面102a係泛指第一晶片1〇〇&之具有主動元件（active device)的一面，而這些第一銲墊1〇乜係以面陣列的方 式’配置於第一晶片100a之第一主動表面1〇2&上。
請參考第3圖，其繪示本發明之較佳實施例之覆晶構裝 基板的局部俯視圖。覆晶構裝基板2〇〇 (以下簡稱基板2〇〇 )之頂面2 0 2係配置有多個凸塊墊群組2 〇 4，其係由基板 2〇〇之最頂層的導線層（如第1圖所示之導線層23a )所構 成’而這些凸塊墊群組2 〇 4分別具有至少二凸塊墊，例如 第一凸塊墊204a及第二凸塊墊2〇4b，其中這些第一凸塊墊 20 4a之位置係分別對應第2圖之第一銲墊丨〇4a的位置，因 此’基板200係可經由這些凸塊墊群組2〇4所具有之第一凸 塊2 0 4 a墊，而對應覆晶接合至第一晶片丨〇 〇 a之第一鋒墊 104a。
請再參考第2圖，為了提高單片晶圓所切割成之晶片數 1 ’或是為了其他的因素，當第一晶片l〇〇a之面積尺寸縮 J、至第一晶片100b之面積尺寸大小時，第^一録塾104a之位 置將相對地移動到第二銲墊1 〇4b之位置，就習知技術而 a ’在這樣的情況之下，則必須重新設計另一種凸塊塾排 列方式之覆晶構裝基板，用以對應覆晶接合至第二晶片
9247twf.ptd 第10頁 557561 五、發明說明（7) \00b，而無法沿用原先覆晶接合至第一晶片1〇〇3的覆晶構 哀基板。然而，如第3圖所示，本發明之覆晶構裝基板2 〇 〇 則可覆晶接合至上述之第一晶片l〇〇a及第二晶片1〇〇b。 請同時參考第2、3圖，基板200之頂面係具有多個凸塊 墊群組204，其分別具有第一凸塊墊2〇4a及第二凸塊墊 2 0 4b，而同一凸塊墊群組之第一凸塊墊及第二凸塊墊係可 經由導線層（如第1圖所示之導線層23a )所構成之導線 206而彼此電性連接，用以提供單一電流路徑。因此，基 板2 0 0除了可以利用這些第一凸塊墊2 〇 4 a ,來對應覆晶接 合至第一晶片l〇〇a之第一鮮墊之外，更可利用這些第 二凸塊塾204a，來覆晶接合至第二晶片1〇〇b之第二銲墊 104b。如此一來，第一晶片1〇〇a及第二晶片1〇〇13將可分別 經由凸塊墊群組2〇4之第一凸塊墊2〇4a及第二凸塊墊 204b ’而覆晶接合至基板2〇〇之頂面2〇2，因而共用此一基 板200。 請參考第4圖，其繪示第3圖之凸塊墊群組，其具有多 個凸塊塾的示意圖。為了使得第3圖之覆晶構裝基板2〇〇可 覆晶接合多種具有相同銲墊排列方式，但具有不同銲墊間 距的晶片’因此’凸塊墊群組3〇〇更可具有多個凸塊墊 3胃02 ’其數量係對應於可共用第2圖之基板2〇〇的晶片數 置’而不止於第4圖所示之四個凸塊墊，而這些凸塊墊3〇2 之間均係同樣以導線3〇4 (即第3圖之導線2〇6 )彼此相互 電性連接’用以提供單一電流路徑。 值得注意的是，為了預防晶片與基板於覆晶接合時，
. ptd 第11頁 557561 五、發明說明（8) 以錫敍合金為材質之凸塊（如第1圖所示之凸塊3〇)於迴 銲處理（reflow)時坍塌至第3圖之導線2〇6及第4圖之導 線304的表面，必須利用第j圖之銲罩層27a來遮蓋住導線 層23a之導線（即第3圖之導線206及第4圖之導線3〇4)， 使得鮮罩層2 7a僅暴露而定義出第4圖之凸塊墊群組3 〇〇的 凸塊墊302，並遮蓋住凸塊墊302之間作為電性連接用的導 線 3 0 4 〇 本發明之覆晶構裝基板係可對應覆晶接合至一第一晶 片、一第二晶片、…，其中這些晶片具有相同之銲墊排列 方式，但具有不同之銲墊間距。本發明係在覆晶 之頂面配置有多個凸塊墊群組，而這些凸塊墊群組分別具 有多個凸塊墊，其依序為一第一凸塊墊、一第二凸塊 墊、…，且同一凸塊墊群組的凸塊墊之間係相互電性連 $，其中這些第一凸塊墊之位置係分別對應於第一晶片之 ^，的位置，而這些第二凸塊墊之位置則分別對應於第二 :之銲墊的位置，其餘之凸塊墊及晶片則以此類推。因 此，本發明之覆晶構裝基板將可對應覆晶接合至第一晶 片、第二晶片、…等多個晶片，因而無 = 而分^設計不肖之覆晶構裝基板。 于不门之曰曰片 5 上/L述，本發明之覆晶構裝基板係可對應覆晶接合 传ΐΐ::相同銲墊排列方式，❻不同銲墊間距的晶片， A :迈二曰曰片、均可共用本發明之同一結構設計的覆晶構裝 二f : ΐ:省略覆晶構裴基板之設計步驟，因而縮短晶片 於覆晶封裝的時程。 71
557561 五、發明說明（9) 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。
9247twf.ptd 第13頁 557561 圖式簡單說明 第1圖繪示習知之一種覆晶球格陣列型封裝結構的剖示 圖， 第2圖繪示兩種具有相同銲墊排列方式，但不同銲墊間 距之晶片的局部底視圖， 第3圖繪示本發明之較佳實施例之覆晶構裝基板的局部 俯視圖；以及 第4圖繪示第3圖之凸塊墊群組，其具有多個凸塊墊的 示意圖。
9247twf.ptd 第14頁

Claims (1)

  1. 557561 六、申請專利範圍 1· 一種覆晶構裝基板，適於覆晶接合至一第一晶片及 一第二晶片其中之一，其中該第一晶片具有一第一主動表 面及複數個第一銲墊，且該些第一銲塾係配置於該第一主 動表面，而該第二晶片具有一第二主動表面及複數個第二 銲塾，且該些第二銲墊係對應該些第一銲墊之排列方式， 而配置於該第二主動表面，該覆晶構裝基板包括： 圖案化之複數個導線層，依序相互疊合； 至少一絕緣層，配置於相鄰二該些導線層之間，用以 隔離該些導線層，並與該些導線層相互交錯疊合；以及 複數個導電插塞，分別貫穿該絕緣層，用以電性連接 該些導電層； 其中該導線層之最頂層者具有複數個凸塊墊群組，而 該些凸塊墊群組分別具有一第一凸塊墊及一第二凸塊墊， 且同一該些凸塊墊群組之該第一凸塊墊及該第二凸塊墊係 相互電性連接’而該些第一凸塊墊之位置係分別對應於該 第一晶片之該些第一銲墊的位置，且該些第二凸塊墊之位 置係分別對應於該第二晶片之該些第二銲墊的位置。 2·如申請專利範圍第1項所述之覆晶構裝基板，其中 同一該些凸塊墊群組之該第一凸塊墊及該第二凸塊墊係經 由该些導線層之最頂層者所構成的導線而相互電性連接。 3·如申請專利範圍第1項所述之覆晶構裝基板，更包 括圖案化之一銲罩層，其覆蓋於該些導線層之最頂層者及 該絕緣層，並暴露出該些第一凸塊墊及該些第二凸塊塾。 4· 一種覆晶構裝基板，適於覆晶接合至一第一晶片及
    9247twi.ptd 第15頁 557561 六、申請專利範圍 一第二晶片其中之一，其中該第一晶片具有一第一主動表 面及複數個第一鲜塾，且該些第一鲜塾係配置於該第一主 動表面，而該第二晶片具有一第二主動表面及複數個第二 銲塾’且該些第二銲墊係對應該些第一銲墊之排列方式， 而配置於該第二主動表面，該覆晶構裝基板具有複數個凸 塊墊群組’其配置於該覆晶構裝基板之頂面，而該些凸塊 塾群組分別具有一第一凸塊墊及一第二凸塊塾，且同一該 些凸塊塾群組之該第一凸塊墊及該第二凸塊墊係相互電性 連接’而該些第一凸塊墊之位置係分別對應於該第一晶片 之該些第一銲墊的位置，且該些第二凸塊墊之位置係分別 對應於該第二晶片之該些第二銲墊的位置。置係刀別 5·如申請專利範圍第1項所述之覆晶構裝基板，更包 圖案化之一銲罩層，其覆蓋於該些導線層 该絕緣層’並暴露出該些第一凸塊墊及該些第
    9247 tw[.ptd 第16頁
TW091117856A 2002-08-08 2002-08-08 Flip chip package structure TW557561B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW091117856A TW557561B (en) 2002-08-08 2002-08-08 Flip chip package structure
US10/249,369 US6714421B2 (en) 2002-08-08 2003-04-03 Flip chip package substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW091117856A TW557561B (en) 2002-08-08 2002-08-08 Flip chip package structure

Publications (1)

Publication Number Publication Date
TW557561B true TW557561B (en) 2003-10-11

Family

ID=31493281

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091117856A TW557561B (en) 2002-08-08 2002-08-08 Flip chip package structure

Country Status (2)

Country Link
US (1) US6714421B2 (zh)
TW (1) TW557561B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6573592B2 (en) * 2001-08-21 2003-06-03 Micron Technology, Inc. Semiconductor die packages with standard ball grid array footprint and method for assembling the same
US20030218246A1 (en) * 2002-05-22 2003-11-27 Hirofumi Abe Semiconductor device passing large electric current
TWI245377B (en) * 2004-11-05 2005-12-11 Advanced Semiconductor Eng Staggered wirebonding configuration
US20080054455A1 (en) * 2006-08-29 2008-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor ball grid array package
KR101736984B1 (ko) * 2010-09-16 2017-05-17 삼성전자 주식회사 벌집형 범프 패드를 갖는 반도체 패키지 기판용 인쇄회로기판 및 이를 포함하는 반도체 패키지
US9425149B1 (en) * 2013-11-22 2016-08-23 Altera Corporation Integrated circuit package routing with reduced crosstalk

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4489365A (en) * 1982-09-17 1984-12-18 Burroughs Corporation Universal leadless chip carrier mounting pad
US5237131A (en) * 1990-10-03 1993-08-17 Chips & Technologies, Inc. Printed circuit board design for multiple versions of integrated circuit device
US6011695A (en) * 1998-11-02 2000-01-04 Intel Corporation External bus interface printed circuit board routing for a ball grid array integrated circuit package

Also Published As

Publication number Publication date
US6714421B2 (en) 2004-03-30
US20040026797A1 (en) 2004-02-12

Similar Documents

Publication Publication Date Title
US7119427B2 (en) Stacked BGA packages
US6281577B1 (en) Chips arranged in plurality of planes and electrically connected to one another
JP4473807B2 (ja) 積層半導体装置及び積層半導体装置の下層モジュール
EP0098932B1 (en) Repairable multi-level system for semiconductor device
US5394303A (en) Semiconductor device
US6441476B1 (en) Flexible tape carrier with external terminals formed on interposers
KR100497997B1 (ko) 반도체 모듈
US20040135243A1 (en) Semiconductor device, its manufacturing method and electronic device
TW200921884A (en) Method for making copper-core layer multi-layer encapsulation substrate
JPH08213543A (ja) マルチダイパッケージ装置
US8552549B2 (en) Semiconductor device, and inspection method thereof
JP2009141169A (ja) 半導体装置
KR20120029169A (ko) 벌집형 범프 패드를 갖는 반도체 패키지 기판용 인쇄회로기판 및 이를 포함하는 반도체 패키지
JP2010130004A (ja) 集積回路基板及びマルチチップ集積回路素子パッケージ
TW557561B (en) Flip chip package structure
US20040256715A1 (en) Wiring board, semiconductor device and process of fabricating wiring board
KR20110037169A (ko) 반도체 패키지
KR20100095901A (ko) 적층형 반도체 패키지
JP3180758B2 (ja) 積層可能な半導体装置とこれらの半導体装置モジュール
JP4521984B2 (ja) 積層型半導体装置および実装基板
JP2003273281A (ja) チップパッケージ及びその製造方法
JP3394479B2 (ja) 半導体装置
KR20090044496A (ko) 스택 패키지
JP2001060638A (ja) 半導体装置
US20070114578A1 (en) Layout structure of ball grid array

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees