TW554505B - Semiconductor package - Google Patents

Abstract

A semiconductor package for controlling the formation of void unwanted in a gap between an integrated circuit die and a substrate comprises a thermoplastic coating layer to be applied on each corner of the die attachment area of the substrate, wherein the height of the thermoplastic coating layer according to warpage of the perimeter of the die attachment area of the substrate. During curing process, the thermoplastic coating layer melts in high temperature environment so as to fill into the gap between the die and the substrate due to warpage of the substrate or not to suffuse an adhesive for die attachment, and in order to enhance the reliability of the semi-conductor package.

Description

554505 Case No. 91101945 / Revised January! Ⅴ. Description of the invention (1) [Background of the invention] The present invention relates to a semiconductor package, especially a ball grid array semiconductor package using a substrate as a wafer carrier. . The manufacturing of Bal 1 Grid Array (BGA) semiconductor packages is generally done in batches on a matrix plate (Matri XS trip) in advance to define a plurality of substrate units, and then preset in each substrate unit at least

I i a wafer receiving area for carrying the wafer after the semiconductor wafer is placed. However, in the traditional packaging process, a plurality of diced semiconductor wafers must be firmly attached to these substrate units, and a die attachment process must be implemented, that is, a coating process must be performed in the wafer attachment area of each substrate unit. A silver glue is applied, and then each semiconductor wafer is touched on the adhesive so that the silver glue can be evenly dispersed between the wafer and the wafer receiving area on the substrate, and then the baking process is completed. Because silver glue is a fluid glue, its distribution is based on the downward pressure applied to the glue when the wafer is positioned so that the silver glue diffuses toward the surroundings and assumes a radial outward distribution in the center (such as the first (Shown in the figure), however, because the direction of the adhesive diffusion flow often cannot match the shape of the wafer, the corners of the wafer often cannot be filled with the adhesive, so there is often a gap between the wafer and the substrate (see Figure 2). In addition, because these semiconductor wafers are constructed on the same matrix plate at the same time, the plate is heated and slightly bent during crystal baking, which will affect the flatness of the substrate, resulting in the lack of adhesive filling between the substrate and the corner of the wafer. A notch, this phenomenon will be more significant when packaging rectangular or large-sized wafers. The formation of a gap between the substrate and the corner of the wafer will cause the glue filling dead corner to form the fusion of the packaging gel when the subsequent packaging glue system is implemented. 7

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] 652] silicon product.pic page 5 554505 _ case number 91101945 year of the dagger q > 7 said _iMz_ 5. Description of the invention (2) As a result, delamination or even popcorn is caused in subsequent processes, Damage to the chip will affect the quality and reliability of the product. [Summary of the invention] The main purpose of the present invention is to set a plurality of bumps made of hot-melt material in advance on the wafer receiving area for melting during baking to fill the gaps around the semiconductor wafer and the substrate that cannot be filled with adhesive. Therefore, even if the substrate is heated and bent, the flatness of the wafer contact area can be maintained, and the semiconductor package to ensure the wafer placement quality. Another object of the present invention is to set a plurality of bumps made of hot-melt material in advance on the wafer receiving area for melting during baking to fill the gaps around the semiconductor wafer and the substrate that cannot be filled with adhesive to avoid molding operations. In the semiconductor package, the molten packaging resin cannot flow into the gap and form air holes, thereby improving the yield of the packaged product. In order to achieve the disclosure and other purposes, the present invention discloses a semiconductor package including: a substrate, the substrate having a first surface and an opposite second surface, on which more than one wafer interface is defined in advance; Placement area for wafer fixed placement, wherein the wafer attachment area is provided with a plurality of hot-melt bumps corresponding to the corner ends of the wafer to be carried, and according to the actual curvature generated by heating during the substrate test Determine the placement height of these bumps; at least one semiconductor wafer, the semiconductor wafer is adhered to the wafer receiving area by an adhesive (such as silver glue); a plurality of conductive elements, provided by the semiconductor wafer! Forming an electrical connection relationship with the substrate; and

I I covers the packaging body of the semiconductor wafer. t The wafer placement process is implemented by first positioning the semiconductor wafer in a pre-coating position.

] 652] 沙 品 pic Page 6 554505 _Case No. 91101945 c |〉 year η month > 7th amendment _ V. Description of the invention (3)

The wafer bonding area on which the adhesive is applied is then baked to cure the fluid adhesive to facilitate a stable bond between the wafer and the substrate. However, the high-temperature environment generated by baking will force the hot-melt bumps to melt to form a flowing state, so as to fill the areas between the semiconductor wafer and the substrate that cannot be coated with a fluid adhesive, and the hot-melt bumps The coating thickness is calculated based on the actual heating curvature of the test substrate. Therefore, even if the substrate is heated at a high temperature (War page), the molten bumps in the flowing state can still fill the periphery of the wafer attachment area and cannot be glued. In the area covered by the adhesive cloth, the semiconductor wafer is completely adhered to the surface of the substrate by the adhesive and the melting bumps, and no gap is formed between the wafer and the substrate, which can prevent the sealing resin from being melted during the molding process. Flowing into the gap to form an air hole significantly improves the quality reliability of the packaged product. [Description of component symbols] 1 0 1 substrate 1 0 5 substrate first surface 1 0 9 solder ball 2 0 5 non-active surface 2 0 9 gold wire 3 0 3 adhesive 3 0 7 void 1 0 0 packaged component 1 0 2 Wafer receiving area 107 Substrate second surface 2 0 2 Wafer 2 0 7 Active surface

3 0 1 encapsulated colloid 3 0 5 hot-melt bumps [schematic description]-The following is a detailed description of the features and effects of the present invention with better specific examples and the accompanying drawings: Figure 1 shows a conventional semiconductor package The semiconductor wafer is adhered to an adhesive

Relative graph of I i adhesive; i

] 652] 沙 品 .pic Page 7 554505 Amendment No. 91101945 V. Description of the Invention (4) Figure 2 is a schematic cross-sectional view of a conventional semiconductor package completed with packaging; Figure 3 is a semiconductor according to the first embodiment of the present invention A schematic cross-sectional view of a package; FIG. 4 is a schematic cross-sectional view of a substrate used in a semiconductor package of the present invention during a baking test; I FIG. 5 is a schematic cross-sectional view of a semiconductor package of the present invention during a placement process; and FIG. A schematic cross-sectional view of the semiconductor package of the present invention during the baking operation. [Description of the Preferred Embodiment] As shown in FIG. 3, the semiconductor package of the present invention includes a substrate (1 0 1), on which at least one wafer receiving area 1 0 2 is defined in advance, so that the substrate 1 0 1 A plurality of hot-melt bumps 3 0 5 can be formed at an appropriate position on the wafer receiving area 1 0 2 during fabrication; an adhesive 3 0 3 is coated on the wafer receiving area 1 0 2 to Used for mounting crystals; at least one semiconductor wafer 202 is covered with the adhesive 3 03 and the wafer 202 is firmly adhered to the substrate 1 01 by baking; a plurality of gold wires 2 0 9 is used to provide the chip 202 electrically connected to the substrate 10 1; and a packaging gel 3 (Π.) Which covers the semiconductor wafer 202 and a plurality of gold wires 2 0 9 The substrate 101 There is a first surface 105 and a second surface 107 corresponding to the first surface 105, and the first surface 105 is defined in advance to one wafer receiving area 1 to 2 Wherein, at the wafer receiving area 1 0 2 I of the substrate corresponding to the corner end of the wafer to be carried, the cloth is provided with a plurality of preset thicknesses.

16521 石 夕 品 .pic Page 8 554505-^ Case No. 91101945 Π / month) 7th amendment _ V. The description of the invention (5) of the bumps 3 0 5, these bumps 3 0 5 can be used as silver glue, Solder resist (Solder M ask) and epoxy resin (£ p 0 xy) or other dazzling materials similar to the thermal expansion coefficient of the adhesive, and determined according to the deformation of the actual bending of the substrate 1 〇 during the baking test The coating height of the bump 3 0 5; when the substrate 1 1 1 is made of FR-4 or BT (Bismaleimide 1 ^ 32; [1 ^) whose thermal expansion coefficient is smaller, the degree of the substrate 1 0 1's heat bending Less obvious, the vertical height difference h between the two sides of the substrate 101 and the wafer receiving area 1 02 from the horizontal plane L is very small (as shown in Fig. 4). The adhesion of 2 0 2 is difficult, and the height of the bump 3 5 5 coated on the surface of the organic material substrate is generally between 0.02 and 0.07 mm, and 0.0 2 5 _ is the best. As shown in Figure 5, the adhesive 3 0 3 is an insulating material made of a material selected from silver wins or epoxy resins, and it is in a flowing state at room temperature. Therefore, after the adhesive 3 0 3 is applied to the central part of the wafer receiving area 1 2 by a conventional adhesive applying device (not shown), the flowing adhesive 3 3 must still be roasted through high temperature (Cu ring) can be stably fixed on the first surface 101 of the substrate 101. The semiconductor wafer 202 has an active surface 207 and an opposite non-active surface 205. When the crystal moon 002 is aligned to the wafer receiving area j 〇2, the non-active surface is used. When the surface 2 0 5 touches the adhesive 3 0 3, the semiconductor wafer 2 0 2 will apply the adhesive 3 0 3-downward pressure forces the adhesive to flow around, as shown in FIG. 5. After that, the fluid adhesive 3 0 3 is cured through high temperature baking, as shown in FIG. 6, because the bumps 3 0 5 placed around the wafer receiving area 1 q 2 are made of a hot-melt material, and The coating thickness has also taken into account the deformation and curvature of the substrate, and then the high temperature is baked to make the bumps 305 on the substrate 101 melt and form a flowing state, which can just fill the bottom of the wafer 202. The adhesive cannot be used. 3 〇3 times

] 652] 硅 品 .plc Page 9 554505 _Case No. 91101945 η Date Modified _5. Description of the Invention (6) The area of the cloth, so even if the substrate 101 is heated and bent, the bottom of the semiconductor wafer 2 02 is still It can be completely filled with the adhesive 3 0 3 and the molten bump 3 0 5 without leaving a gap between the wafer 2 2 and the substrate 1 0 1. Finally, please trace back to the figure 3, electrically connect the semiconductor wafer 2 0 2 to the substrate 1 0 with a plurality of gold wires 2 0 9, and move the semi-finished package carrying the semiconductor wafer 2 2 2 into A conventional mold (not shown) is subjected to a molding process, and then the semiconductor i-chip 20 2 and most of the gold wires 20 9 are covered with a conventional encapsulant 3 01 such as epoxy resin to be molded on the substrate 101. Since the hot-melt bumps 3 0 5 in the flowing state during wafer filling have filled the areas where the adhesive 3 3 cannot be filled in the wafer receiving area 1 2, there is no gap between the semiconductor wafer and the substrate. The melt-sealing resin forming the sealing colloid 301 will not flow into the bottom gap of the wafer 202, so it can prevent the formation of air holes or the problem of delamination.

II The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the essential technical content of the present invention. For example, those who are familiar with the technology can do it without departing from the spirit and principle disclosed by the present invention. For changes or retouching, i should still be covered by the patents mentioned later.

] 652] Sands pic page 10

Claims (1)

554505 _ Case No. 91101945 "μyear r [month: // day amendments_ VI. Patent application scope 1. A semiconductor package, comprising: a substrate, the substrate has a first surface and an opposite second surface, Wherein, at least one wafer receiving area is preset on the first surface, and an adhesive is coated thereon, and a plurality of bumps are formed in the wafer receiving area that the adhesive cannot penetrate; The wafer is adhered to the wafer receiving area of the substrate by the adhesive and forms an electrical connection relationship with the substrate; and a packaging gel for covering the semiconductor wafer. 2. The semiconductor package of item 1 in the patent application scope, wherein the glue is silver glue. 3. For the semiconductor package of item 1 of the patent application scope, wherein the bump is made of a hot-melt material. 4. For example, the semiconductor package of claim 1, wherein the bump is selected from the group consisting of solder resist (S ο 1 der M ask), epoxy resin (e ρ ο X y), and silver paste (si 1 verpaste) and so on. 5. The semiconductor package according to item 1 of the scope of patent application, wherein the coating thickness of the bump is determined by the thermal bending distance from the two sides of the wafer receiving area to the south of the horizontal plane. 6. The semiconductor package according to item 1 of the scope of patent application, wherein the bumps are arranged on the corner end portions of the wafer receiving area. 7. The semiconductor package according to item 1 of the patent application scope, wherein the height of the bump | is between 0.02 mm and 0.07_. 8. For the semiconductor package according to item 1 of the patent application scope, the height of the bump is preferably 0.025 mm. ] 6ς2] 19 pin.pic p. 11