TW201714257A - Chip package having protection piece compliantly attached on chip sensor surface - Google Patents

Abstract

Disclose is a chip package having protection piece compliantly attached on chip sensor surface, comprising a substrate, a main chip disposed on the substrate, an adhesive protection piece covering the main chip and a package body encapsulating the main chip. The main chip has a chip-sensing surface far from the substrate and a connection terminal electrically connected to the substrate. The adhesive protection piece consists essentially of a pick-and-place sheet and a die bonding layer. The package body completely encapsulates the die bonding layer and doesn't cover the outer surface of the pick-and-place sheet. The adhesive protection piece is compliantly attached onto the chip sensing surface by pick-and-place operation so that the die bonding layer can adhere to the chip sensing surface and maintain the stable adhesive gap. Moreover, the outer surface of the pick-and-place sheet is parallel to the chip sensing surface, which is not effected by the level error of the substrate to solve the issue about sensing distortion when a sensing chip covered by a protection piece.

Description

Chip package structure with protective sheet attached to the wafer sensing surface

The present invention relates to the field of inductive chip packaging, and more particularly to a chip package structure in which a protective sheet is attached to a wafer sensing surface, which can be applied to a capping package product of a fingerprint identification chip.

As the core of microelectronic devices, semiconductor wafers mainly differ in the following categories according to their functions: IC chip, LED chip, sensor chip, solar cell. Solar cell chip and MEMS chip. The sensing chip can be further divided into a fingerprint identification chip, an image sensing chip, a pressure sensing chip, and the like. Different functional wafers require a corresponding package structure and should meet the requirements of protecting the wafer, transferring the wafer electrical signals to the outside, and not affecting the wafer function.

In the conventional package design of the fingerprint recognition wafer, the sensing surface of the wafer must be exposed outside the package structure for the finger to touch the wafer sensing surface. However, exposed wafer sensing surfaces are susceptible to contamination or damage, resulting in product failure.

In the US Patent No. US Pat. No. 8,803,258, the entire disclosure of the entire disclosure of the entire disclosure of the disclosure of the entire disclosure of The pattern identifier comprises a mounting substrate, an integrated circuit chip carried on the mounting substrate and having an array of electric field polarized fingerprint identifying elements, and an electrical connector coupling the mounting substrate and the IC wafer. Additionally, the fingerprint recognition device includes a protective plate attached to the array of fingerprinting elements, the protective plate being defined as a capacitive lens for use on an array of electric field polarized fingerprinting elements. The fingerprint identification device further includes a sealing material adjacent to the mounting substrate and the IC chip and located around the electrical connector. The width of the protection board on the short side of the wafer must be large to connect the solder; the length of the protection board on the long side of the wafer must be small to avoid the bonding of the bonding wires of the wafer bonding pads, so the protective board fails to adhere. On the wafer sensing surface. Generally, the method of adding the protective plate is first pressed onto the wafer by a mother piece, and the horizontal plane of the substrate is used as the mounting level of the protective plate mother piece. When the adhesive between the wafer and the substrate is cured, the mounting level error of the wafer is The gap between the sensing wafer and the protective plate is affected, so that the sensitivity of the wafer is reduced, so that the problem of inductive distortion after the protective wafer is attached to the protective sheet is prone to occur.

In order to solve the above problems, the main object of the present invention is to provide a chip package structure in which a protective sheet is attached to a wafer sensing surface, which avoids the problem that the sensing wafer is susceptible to inductive distortion after the protective sheet is attached, and improves the manufacturing yield rate. Productivity.

A second object of the present invention is to provide a chip package structure in which a protective sheet is attached to a wafer sensing surface. When applied to a multi-wafer structure of a fingerprint identification chip and other wafers, the wafer size package can be met, and the fingerprint identification crystal The bottom of the film does not need to open the cavity, and the packaging method is simple, so the additional production cost is avoided and the structural strength of the fingerprint identification wafer itself is maintained.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a chip package structure in which a protective sheet is attached to a wafer sensing surface, and comprises a substrate, a main wafer, a viscous protective sheet and a package. The main wafer is disposed on the substrate. The main wafer has a wafer sensing surface and a connection end. The wafer sensing surface is relatively far from the substrate, and the connection end is electrically connected to the substrate. The adhesive protection film is mainly composed of a pick-and-place film and a first adhesive layer, the pick-and-place film has an inner surface and an outer surface, and the first adhesive layer covers the pick-and-place sheet. In the inner surface, the adhesive protection sheet is adhered to the wafer sensing surface in a pick-and-place manner, so that the first adhesive layer adheres to the wafer sensing surface and maintains a fixed adhesive gap, and the pick-and-place sheet The outer surface is parallel to the wafer sensing surface without being affected by the horizontal error of the substrate. The packaging system is formed on the substrate to seal the main wafer, the packaging system has a sealing height on the substrate, which is greater than the thickness of the main wafer and does not exceed the outer surface of the pick-and-place sheet, so that The package completely seals the first die layer and does not cover the outer surface of the pick and place sheet. Thereby, the parallelism between the outer surface of the pick-and-place sheet and the wafer sensing surface of the main wafer is good, and the problem of inductive distortion after the protective wafer is attached to the protective sheet is avoided.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing package structure, a second adhesive layer may be further included Between the main wafer and the substrate, the coverage area of the second adhesive layer can be smaller than the coverage area of the first adhesive layer, and the main wafer can be ignored regardless of the level of the substrate, like a general IC chip. The mounting method mounts the main wafer having the wafer sensing surface on the substrate.

In the foregoing package structure, at least one wafer may be further disposed on the substrate and located between the main wafer and the substrate, and the thickness of the second adhesive layer may be greater than the thickness of the first adhesive layer, The second bonding layer is sealed to the sub-wafer, so that the main wafer can be unaffected to the substrate, and the horizontal deviation of the main wafer relative to the substrate does not affect the outer surface of the pick-and-place wafer and the wafer of the main wafer. The parallelism of the sensing surfaces avoids the problem of distortion of the sensitivity after the protective sheet is attached and the secondary wafer is hidden.

In the foregoing package structure, at least one passive component may be further disposed on the substrate and located between the main wafer and the substrate, and the second adhesive layer may seal the passive component more, so more small components It can be embedded under the main wafer, and the surface coverage area of the overall package structure can be further reduced.

In the foregoing package structure, the first adhesive layer completely covers the inner surface of the pick-and-place sheet, and a first dimension of the pick-and-place sheet is preferably larger than a second size of the main wafer and smaller than The third dimension of the substrate is such that the package partially covers the periphery of the pick-and-place sheet, so that the first adhesive layer is completely sealed by the package to avoid exposure of the die-bonding material.

In the foregoing package structure, a metal cover may be further included to cover the package, and the metal cover preferably has an opening to expose the pick-and-place film. The outer surface can form a circuit loop, so that the wafer fingerprint recognition function can be realized, and the electrostatic protection function is provided to expose the outer surface of the pick-and-place sheet for finger pressure sensing or receiving external information.

In the above package structure, a circuit board may be further included, and the metal cover can be individually bonded to the circuit board, so that the bonding stress of the metal cover does not directly act on the package and the adhesive protection sheet.

In the above package structure, the connection end is a peripheral pad located on the sensing surface of the chip, and the connection end is connected to the substrate by a bonding wire, and the bonding wire is in a line arc portion above the main wafer. Preferably embedded in the first die layer. Therefore, the first die layer can closely fit the wafer sensing surface and the position of the connection end can be made without special formation to form a recessed region of the main wafer.

In the above package structure, the connection end is disposed on a lower surface of the main wafer relative to the sensing surface of the wafer, and the connection end point may include at least one bump, so that the main wafer can be flipped through the main wafer. The conductive bump is electrically connected to the substrate, and the first die layer is thinner in design.

In the foregoing package structure, the wafer sensing surface includes a fingerprint identification area, and the first adhesive layer preferably covers the fingerprint identification area. Therefore, the first adhesive layer closely adheres to the fingerprint recognition area and enhances sensitivity.

According to the above technical means, the present invention utilizes the adhesive protection sheet to adhere to the wafer sensing surface in a pick-and-place manner, so that the first adhesive layer adheres to the wafer sensing surface and maintains a fixed adhesive gap. And the outer surface of the pick-and-place film is parallel to the wafer sensing surface without being affected by the horizontal error of the substrate... The method avoids the problem of inductive distortion after the sensor chip is mounted with the protective sheet, and improves the yield and production efficiency.

The first size of the L1‧‧‧ pick and place film

The second size of the L2‧‧‧ main wafer

The third size of the L3‧‧‧ substrate

10‧‧‧ cutting device

100‧‧‧ Chip package construction

110‧‧‧Substrate

111‧‧‧External mat

112‧‧‧Internal finger

120‧‧‧Main chip

121‧‧‧ wafer sensing surface

122‧‧‧Connection endpoint

123‧‧‧Fingerprint identification area

124‧‧‧welding line

130‧‧‧Adhesive protection film

131‧‧‧ pick and drop

132‧‧‧First sticky layer

133‧‧‧ inner surface

134‧‧‧ outer surface

140‧‧‧Package

141‧‧‧ Seal height

150‧‧‧Second layer

160‧‧‧ wafers

161‧‧‧The third layer of adhesion

162‧‧‧welding line

200‧‧‧ Chip package construction

270‧‧‧Metal cover

271‧‧‧Opening

280‧‧‧ boards

281‧‧‧ joint pad

300‧‧‧ Chip package construction

361‧‧‧ Passive components

400‧‧‧ Chip package construction

450‧‧‧Second layer

500‧‧‧ Chip package construction

550‧‧‧Second bonding layer

570‧‧‧Metal cover

571‧‧‧Opening

580‧‧‧ boards

581‧‧‧ joint pad

600‧‧‧ Chip package construction

622‧‧‧Connection endpoint

624‧‧‧ lower surface

700‧‧‧ Chip package construction

770‧‧‧Metal cover

771‧‧‧ openings

780‧‧‧ circuit board

781‧‧‧Join pad

800‧‧‧Inductive chip package construction

810‧‧‧Substrate

811‧‧‧External mat

820‧‧‧Main chip

821‧‧‧ wafer sensing surface

822‧‧‧Connection endpoint

823‧‧‧Fingerprint identification area

824‧‧‧welding line

825‧‧‧ crystal back cavity

830‧‧‧protection film

832‧‧‧First sticky layer

840‧‧‧Package

850‧‧‧Second layer

860‧‧‧ wafers

1 is a cross-sectional view showing a sensing chip package structure with a protective sheet according to an exemplary embodiment of the present invention.

2 is a cross-sectional view showing a wafer package structure in which a protective sheet is attached to a wafer sensing surface according to a first embodiment of the present invention.

3A to 3I are cross-sectional views showing the components in the respective process steps of fabricating the wafer package structure in which the protective sheet is attached to the wafer sensing surface in accordance with the first embodiment of the present invention.

Figure 4 is a cross-sectional view showing another embodiment of the present invention in which a protective sheet is attached to a wafer package structure of a wafer sensing surface.

Fig. 5 is a cross-sectional view showing another wafer package structure in which a protective sheet is attached to a wafer sensing surface in accordance with a third embodiment of the present invention.

Figure 6 is a cross-sectional view showing a wafer package structure in which a protective sheet is attached to a wafer sensing surface in accordance with a fourth embodiment of the present invention.

7A to 7G are cross-sectional views showing the components in the respective process steps of fabricating the wafer package structure in which the protective sheet is attached to the wafer sensing surface in accordance with the fourth embodiment of the present invention.

Figure 8 is a cross-sectional view showing another embodiment of the present invention, in which the protective sheet is attached to the wafer package structure of the wafer sensing surface.

Figure 9 is a cross-sectional view showing another embodiment of the present invention, in which the protective sheet is attached to the wafer package structure of the wafer sensing surface.

10A to 10F are cross-sectional views showing the components in the respective process steps of fabricating the wafer package structure in which the protective sheet is attached to the wafer sensing surface in accordance with the sixth embodiment of the present invention.

Figure 11 is a cross-sectional view showing a wafer package structure in which a protective sheet is attached to a wafer sensing surface in accordance with a seventh embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

In an exemplary embodiment of the present invention, an attempt is made to provide an inductive wafer package structure 800 with a protective sheet attached, as illustrated in the cross-sectional view of FIG. The inductive chip package structure 800 includes a substrate 810, a main wafer 820, a protective sheet 830, and a package 840. The substrate 810 is a line carrier and has a plurality of external pads 811 for externally bonding a circuit board. In the packaging process, the substrate 810 is provided in a plurality of ways in a master.

A plurality of the main chips 820 are disposed on the mother substrate of the substrate 810 The master wafer 820 can be a fingerprint recognition wafer. The main wafer 820 has a chip sensing surface 821 and a connection end 822. The chip sensing surface 821 can include a fingerprint identification area 823. The chip sensing surface 821 is relatively far from the substrate 810 , and the connection end 822 is electrically connected to the substrate 810 . The wafer sensing surface 821 is a surface that senses external information. The connection end point 822 can be an end point of the connection line, wherein the main chip 820 is provided with a recessed notch, and the connection end point 822 is disposed on the gap. The connection terminal 822 is connected to the substrate 810 by a wire 824 formed by a single wire.

The protective sheet 830 is attached to a plurality of main wafers 820 in a plurality of ways. The protective sheet 830 is made of a transparent material such as glass, and a first adhesive layer 832 is bonded to the protective sheet. 830 to the wafer sensing surface 821 of the main wafer 820 and over the fingerprint identification area 823. The package 840 is formed on the substrate 810 by sealing to seal the periphery of the main wafer 820 and the bonding wire 824. Finally, using a singulation process, the mother substrate of the substrate 810, the package 840 and the mother substrate of the protection sheet 830 are simultaneously cut to obtain the sensing chip package structure 800 as shown in FIG. The package 840 does not completely seal the first die layer 832.

The protective sheet 830 is mounted on the main wafer 820 in a manner horizontal to the substrate 810. When there is a horizontal error between the main chip 820 and the substrate 810, there is also a horizontal error between the protective sheet 830 and the wafer sensing surface 821, so that the first adhesive layer 832 is adhered to the wafer sensing surface 821. Since the fixed adhesive gap cannot be maintained, the problem of distortion of the inductance is generated after the protective sheet 830 is attached.

In order to eliminate the protective sheet 830 and the wafer sensing surface 821 as much as possible The level of error between. The wafer package structure 800 must use a very thin and uniform second layer of adhesion 850, such as Die Attach Material (DAM). The second bonding layer 850 is formed on the main wafer 820 in advance and adheres to the main wafer 820 and the substrate 810.

In addition, when the chip package structure 800 needs to mount at least one wafer 860 between the main wafer 820 and the substrate 810, such as an ASIC semiconductor wafer, the main wafer 820 must first create a crystal back cavity 825 at the wafer level. To accommodate the wafer 860. Therefore, it is difficult to produce the main wafer 820 having the crystal back cavity 825 and the patterned second die layer 850 and to generate high manufacturing cost.

According to a first embodiment of the present invention, a chip package structure 100 in which a protective sheet is attached to a wafer sensing surface is illustrated in a cross-sectional view of FIG. 2 and a cross-sectional view of the elements in the respective process steps of FIGS. 3A to 3I. The chip package structure 100 includes a substrate 110, a main wafer 120, a viscous protection sheet 130, and a package body 140.

The substrate 110 has a plurality of pads 111 on the lower surface thereof and an inner finger 112 on the upper surface thereof. The external pads 111 are used for external electrical connection, and the internal fingers 112 are used for the package. Electrical connection of the internal wafer. The substrate 110 can be a line carrier such as a micro printed circuit board, a flexible circuit board or a ceramic circuit substrate.

The main chip 120 is disposed on the substrate 110. The main wafer 120 can be a semiconductor wafer, preferably a fingerprint identification chip, or an image sensing wafer or other wafer suitable for the same package of the present invention. The so-called "main chip" is a representation The main wafer 120 is the largest wafer in the wafer package construction 100 or the only inductive wafer. The main wafer 120 has a wafer sensing surface 121 and a connection end 122. The chip sensing surface 121 is a surface of the wafer that senses an external message. The connection end 122 is an electrical end point that can communicate with the chip sensing surface 121. The chip sensing surface 121 is relatively far from the substrate. The connection end 122 is Electrically connected to the substrate 110.

The viscous protective sheet 130 is mainly composed of a pick-and-place sheet 131 and a first viscous layer 132; in other words, the pick-and-place sheet 131 and the first viscous layer 132 constitute most of the viscous protective sheet 130. Share or all. The pick-and-place sheet 131 can be a homogeneous hard material that does not affect the inductive conduction, such as glass, sapphire or microcrystalline zirconium. The first adhesive layer 132 can be a curable homogeneous adhesive material that does not affect induction conduction, such as epoxy without spacer or Die Attach Material (DAM). The pick-and-place sheet 131 has an inner surface 133 and an outer surface 134. The first adhesive layer 132 covers the inner surface 133 of the pick-and-place sheet 131. The first adhesive layer 132 has a suitable thickness. To cover the connecting wires embedded in it. The viscous protection sheet 130 is completely over the main wafer 120. The area of the outer surface 134 of the viscous protection sheet 130 is larger than the area of the wafer sensing surface 121 of the main wafer 120, but smaller than the substrate 110. The area of the upper surface. The adhesive protective sheet 130 is adhered to the wafer sensing surface 121 in a pick-and-place manner, so that the first adhesive layer 132 is adhered to the wafer sensing surface 121 and maintains a fixed adhesive gap, that is, the adhesive is installed. After the protective sheet 130 is on the main wafer 120, the first adhesive layer 132 is maintained at a fixed thickness before curing, and the mechanical operation can be automated. The pick-and-place operation of the adhesive protection sheet 130. Moreover, the outer surface 134 of the pick-and-place sheet 131 is parallel to the wafer sensing surface 121 without being affected by the horizontal error of the substrate 110. As used herein, "adherently adhered" means that all of the wafer sensing surface 121 is covered by the adhesive protective sheet 130 and adhered to the first adhesive layer 132, and the wafer sensing surface 121 and the wafer The outer surface 134 of the release sheet 131 is horizontal such that the first die layer 132 has a uniform thickness after curing. In this embodiment, when the connection end point 122 is formed on the wafer sensing surface 121, the first adhesive layer 132 further covers the connection end point 122.

The package body 140 is formed on the substrate 110. The package body 140 can be an electrically insulating material for sealing the periphery of the main wafer 120 to seal the main wafer 120, such as a mold epoxy compound (EMC). The package body 140 has a sealing height 141 on the substrate 110, which is greater than the thickness of the main wafer 120 and does not exceed the outer surface 134 of the pick-and-place sheet 131, so that the package body 140 completely seals the first surface. A die layer 132 does not cover the outer surface 134 of the pick and place sheet 131. Thereby, the outer surface 134 of the pick-and-place sheet 131 can be closely attached to the chip sensing surface 121, thereby avoiding the problem of inductive distortion after the sensor wafer is attached with the adhesive protective sheet 130.

More specifically, the chip package structure 100 further includes a second die bond layer 150 formed between the main die 120 and the substrate 110. The second die bond layer 150 may have a smaller coverage area than the first die bond layer 150. The coverage area of the bonding layer 132, the second bonding layer 150 may be an adhesive for bonding a semiconductor wafer, such as an epoxy resin or a film-coated adhesive layer (Film-On-Die adhesive, FOD), the so-called encapsulation layer is thicker than the coating layer, and the thickness is less than the coverage line. The glue layer, and the encapsulation layer is superior to the coating layer on the glue coating effect. The main wafer 120 can be mounted on the substrate 110 with the wafer sensing surface 121 as it is mounted, regardless of the level of the substrate 110.

In this embodiment, the chip package structure 100 further includes at least one wafer 160 bonded to the substrate 110 and between the main wafer 120 and the substrate 110. The second die layer 150 is The thickness may be greater than the thickness of the first die layer 132 such that the second die layer 150 seals the sub-wafer 160. Therefore, the wafer 160 can be completely encapsulated and sealed by the second die layer 150. The sub-wafer 160 is an ASIC chip. The sub-wafer 160 is adhered to the substrate 110 by a third bonding layer 161 and electrically connected to the substrate 110 by at least one bonding wire 162. The bonding wire 162 can be a thin metal wire such as a gold wire. The second die layer 150 further seals the third die layer 161 and the bonding wire 162. Therefore, the main wafer 120 may not be attached to the substrate 110. The horizontal deviation of the main wafer 120 relative to the substrate 110 does not affect the outer surface 134 of the pick-and-place sheet 131 and the wafer sensing surface 121 of the main wafer 120. The parallelism avoids the problem of distortion of the sensitivity after the protective sheet is attached and the secondary wafer is hidden.

In the present embodiment, the connection terminal 122 is a peripheral pad located on the wafer sensing surface 121, and the connection terminal 122 is connected to the internal finger 112 of the substrate 110 by a bonding wire 124. The bond wire 124 can be a metal conductive wire such as a gold wire. In this embodiment, the wire arc portion of the bonding wire 124 above the main wafer 120 is preferably embedded in the first bonding layer 132. Therefore, the first bonding layer 132 can closely fit the wire bonding layer 132. The wafer sensing surface 121, and the position of the connection end point 122 can be made without special To form a recessed region of the main wafer.

The chip sensing surface 121 includes a fingerprint identification area 123, and the fingerprint identification area 123 includes an array of identification elements (not shown) for receiving external information, and the first adhesion layer 132 is preferably comprehensive. Covering the fingerprint identification area 123. Therefore, the first die layer 132 closely fits the fingerprint recognition area 123 and enhances the sensitivity.

Referring to Figures 3A through 3I, the method of fabricating the chip package structure 100 will be further described below. As shown in FIG. 3A, the step of providing a substrate 110 is performed to fix the substrate 110 on a working platform. The substrate 110 has the external pads 111 and the internal fingers 112 on different surfaces. Thereafter, as shown in FIG. 3B, a wafer mounting operation is performed, and the wafer 160 is bonded to the substrate 110 by the third die layer 161. Thereafter, as shown in FIG. 3C, the bonding wire 162 is formed by wire bonding, so that the bonding wire 162 is electrically connected to the secondary wafer 160 and the substrate 110. Then, as shown in FIG. 3D, the mounting process of the main wafer 120 is performed, and the second wafer 160 and the bonding wire 162 are sealed and adhered to the main wafer 120 to the substrate 110 by the second bonding layer 150. The chip sensing surface 121 of the main wafer 120 includes the connection end point 122 and the fingerprint identification area 123. The wafer sensing surface 121 is away from the substrate 110, and then the second bonding layer 150 is cured. Then, as shown in FIG. 3E, the bonding wire 124 is formed by wire bonding, and the bonding wire 124 is electrically connected to the connection end 122 of the main wafer 120 and the internal finger 112 of the substrate 110. Then, as shown in FIG. 3F, a protective sheet pick-and-place operation is performed, and the adhesive protective sheet 130 is compliantly attached to the main wafer 120. The adhesive protective sheet 130 includes the pick-and-place sheet 131 and the protective sheet 130. First die layer 132, The first die layer 132 is adhered to the chip sensing surface 121 and maintains a fixed adhesive gap, and the wire arc portion of the bonding wire 124 above the main wafer 120 can be embedded in the first die layer 132. Then, as shown in FIG. 3G, a sealing step is performed to form the package body 140 on the substrate 110 to seal the main wafer 120 and the first die layer 132. The package body 140 has a The sealing height 141 on the substrate is greater than the thickness of the main wafer 120 and does not exceed the outer surface 134 of the pick-and-place sheet 131, so that the package body 140 completely seals the first die layer 132 and does not cover The outer surface 134 of the pick and place sheet 131. Thereafter, a package singulation separation step is performed. As shown in FIG. 3H, the lower surface of the substrate 110 of the chip package structure 100 faces a laser cutting device 10, and the cutting device 10 cuts through the substrate 110 and The thickness of the package body 140 is further cut through the package body 140, and the pick-and-place film 131 and the first die-bonding layer 132 are not cut, so that the cutting stress can be reduced, thereby preventing the cover from being attached to the main chip. The loose protective sheet of 120 is loose. FIG. 3I illustrates the plurality of discrete wafer package structures 100 after dicing. In the above-described package singulation separation step, the pick-and-place sheet 131 of the viscous protective sheet 130 is not cut, so that the adhesive gap filling the first viscous layer 132 can be maintained and the gap is not cracked.

According to a second embodiment of the present invention, another chip package structure 200 to which a protective sheet is attached to a wafer sensing surface is illustrated in a cross-sectional view of FIG. Except for the main components such as the metal cover 270 and the circuit board 280, the chip package structure 200 is substantially the same as the chip package structure 100 of the first embodiment, wherein the components of the same name and function corresponding to the first embodiment are The component numbers of the first embodiment are shown, and the details of the details are not described again. The chip package structure The 200 series includes a substrate 110, a main wafer 120, a viscous protection sheet 130, and a package body 140.

The main chip 120 is disposed on the substrate 110. The main chip 120 can be a fingerprint identification chip. The substrate 110 is provided with a plurality of external pads 111 and an internal finger 112. The main chip 120 has a chip sensing surface 121 and a connecting end point 122. The chip sensing surface 121 is relatively far from the substrate 110. The connecting end 122 can be electrically connected to the substrate 110 by using the bonding wire 124. The adhesive protective sheet 130 is mainly composed of a pick-and-place sheet 131 and a first adhesive layer 132. The pick-and-place sheet 131 has an inner surface 133 and an outer surface 134. The first adhesive layer 132 is Covering the inner surface 133 of the pick-and-place sheet 131, the adhesive protective sheet 130 is adhered to the wafer sensing surface 121 in a pick-and-place manner, so that the first adhesive layer 132 is adhered to the wafer sensing surface. 121 and maintaining a fixed adhesive gap, and the outer surface 134 of the pick and place sheet 131 is parallel to the wafer sensing surface 121 without being affected by the horizontal error of the substrate 110. The wire arc 124 may be embedded in the first die layer 132 at a line arc portion above the main wafer 120. In addition, the package body 140 is formed on the substrate 110 to seal the main wafer 120. The package body 140 has a sealing height 141 on the substrate 110, which is greater than the thickness of the main wafer 120 and does not exceed The outer surface 134 of the pick-and-place sheet 131 is such that the package body 140 completely seals the first die layer 132 and does not cover the outer surface 134 of the pick-and-place sheet 131. The chip package structure 200 further includes a second die layer 150 formed between the main wafer 120 and the substrate 110. The second die layer 150 may have a smaller coverage area than the first die layer 132. Coverage area. At least one wafer 160 is bonded to the substrate 110 and located on the main wafer The thickness of the second die layer 150 may be greater than the thickness of the first die layer 132 such that the second die layer 150 seals the sub wafer 160.

In the present embodiment, the chip package structure 200 further includes a metal cover 270 that can be covered by the package body 140. The metal cover 270 preferably has an opening 271 to expose the pick-and-place piece 131. The outer surface 134 can form a circuit loop to realize the wafer fingerprint recognition function, and additionally has an electrostatic protection function, and the outer surface 134 of the pick-and-place piece 131 is exposed by the opening 271 for finger pressure sensing. Or accept outside information. The chip package structure 200 further includes a circuit board 280. The substrate 110 and the metal cover 270 can be individually bonded to the circuit board 280. Therefore, the bonding stress of the metal cover 270 does not directly act on the package body 140 and the adhesive layer. Sex protection sheet 130. The external pads 111 of the substrate 110 are solder bonded to the plurality of bonding pads 281 of the circuit board 280.

The chip sensing surface 121 includes a fingerprint identification area 123, and the first adhesion layer 132 preferably covers the fingerprint identification area 123 in a comprehensive manner. The fingerprint recognition area 123 is aligned in the opening 271 of the metal cover 270 through the adhesive protection sheet 130.

In accordance with a third embodiment of the present invention, another wafer package structure 300 to which the protective sheet is attached to the wafer sensing surface is illustrated in cross-section in FIG. The chip package structure 300 is substantially the same as the chip package structure 100 of the first body embodiment except that a plurality of main elements such as the passive element 361 are used, wherein the components of the same name and function corresponding to the first embodiment are first implemented. The component number of the example is shown, and the same structure of the detail is not described again. The chip package structure 300 package A substrate 110, a main wafer 120, a viscous protection sheet 130, and a package body 140 are included. The main wafer 120 is disposed on the substrate 110. The main wafer 120 has a wafer sensing surface 121 and a connection end 122. A bonding wire 124 connects the connection terminal 122 to the internal finger 112 of the substrate 110. The adhesive protective sheet 130 is mainly composed of a pick-and-place sheet 131 and a first adhesive layer 132. The adhesive protective sheet 130 is adhered to the wafer sensing surface 121 in a pick-and-place manner so that the adhesive sheet 130 The first die layer 132 is adhered to the wafer sensing surface 121 and maintains a fixed adhesive gap, and the outer surface 134 of the pick and place sheet 131 is parallel to the wafer sensing surface 121 without being affected by the horizontal error of the substrate 110. The wire arc portion of the bonding wire 124 above the main wafer 120 is preferably embedded in the first die layer 132. The package body 140 is formed on the substrate 110. The package body 140 has a sealing height 141 on the substrate 110, which is greater than the thickness of the main wafer 120 and does not exceed the outer surface of the pick-and-place sheet 131. 134, so that the package body 140 completely seals the first die layer 132 and does not cover the outer surface 134 of the pick and place sheet 131. In addition, the chip sensing surface 121 can include a fingerprint identification area 123, and the first adhesion layer 132 preferably covers the fingerprint identification area 123 in a comprehensive manner.

The chip package structure 300 further includes a second die layer 150 formed between the main wafer 120 and the substrate 110. The second die layer 150 may have a smaller coverage area than the first die layer 132. Coverage area. At least once, the wafer 160 is bonded to the substrate 110 and located between the main wafer 120 and the substrate 110. The thickness of the second adhesive layer 150 may be greater than the thickness of the first adhesive layer 132. The second die layer 150 seals the sub-wafer 160. The sub-wafer 160 utilizes a third The bonding layer 161 is adhered to the substrate 110 and electrically connected to the substrate 110 by at least one bonding wire 162. The second die layer 150 further seals the third die layer 161 and the bonding wire 162. In this embodiment, the chip package structure 300 further includes at least one passive component 361 disposed on the substrate 110 and located between the main wafer 120 and the substrate 110. The second die layer 150 is The passive element 361 is sealed more. The passive component 361 is a small protective component, such as a capacitor, an inductor or a resistor, for electrically connecting the sub-wafer 160 to the substrate 110. More components than the main wafer 120 can be embedded under the main wafer 120, so that the surface footprint of the overall package structure can be further reduced.

According to a fourth embodiment of the present invention, another chip package structure 400 to which the protective sheet is attached to the wafer sensing surface is illustrated in a cross-sectional view of FIG. 6 and a cross-sectional view of the elements in the respective process steps of FIGS. 7A to 7G. The wafer package construction 400 is substantially the same as the wafer package construction 100 of the first body embodiment except for variations from a multi-chip package to a single-chip package, wherein the elements of the same name and function corresponding to the first embodiment are first The component numbers of the specific embodiments are shown, and the details of the details are not described again. The chip package structure 400 includes a substrate 110, a main wafer 120 disposed on the substrate 110, a viscous protection sheet 130 adhered to the main wafer 120 in a pick-and-place manner, and a substrate 110 formed thereon. The upper package 140. The chip sensing surface 121 of the main wafer 120 can include a fingerprint identification area 123, and the first bonding layer 132 preferably covers the fingerprint identification area 123 in a comprehensive manner.

In this embodiment, the chip package structure 400 can further include a The second bonding layer 450 is formed between the main wafer 120 and the substrate 110. The coverage area of the second bonding layer 450 may be smaller than the coverage area of the first bonding layer 132. Since the second bonding layer 450 does not need to be coated with the sub-wafer, the thickness thereof can be reduced, and the second bonding layer 450 can be a material for simply bonding the wafer, such as an epoxy resin or a wafer attaching film ( DAF) or Die Attach Material (DAM).

In this embodiment, the first die layer 132 covers the inner surface 133 of the pick-and-place film 131, and a first dimension L1 of the pick-and-place chip 131 is preferably greater than the master wafer 120. A second dimension L2 is smaller than a third dimension L3 of the substrate 110, so that the package body 140 partially covers the periphery of the pick-and-place sheet 131, so that the first adhesive layer 132 is completely sealed by the package body 140. To avoid the exposure of the bonded crystal material.

Referring to Figures 7A through 7G, the method of fabricating the wafer package structure 400 will be further described below. As shown in FIG. 7A, first, the substrate 110 is placed on a work platform, and the substrate 110 has the external pads 111 and the internal fingers 112. Then, as shown in FIG. 7B, the main wafer 120 is bonded to the substrate 110 by the second adhesive layer 450. The wafer sensing surface 121 of the main wafer 120 includes the connection end point 122 and the fingerprint identification. The region 123, the wafer sensing surface 121 is away from the substrate 110, and then the second bonding layer 450 is cured. Then, as shown in FIG. 7C, the bonding wire 124 is formed by wire bonding, so that the bonding wire 124 is electrically connected to the connection end 122 of the main wafer 120 and the internal finger 112 of the substrate 110. Thereafter, as shown in FIG. 7D, a protective sheet pick-and-place operation is performed, and the adhesive protective sheet 130 is compliantly attached to the main crystal. On the sheet 120, the adhesive protection sheet 130 includes the pick-and-place sheet 131 and the first adhesive layer 132. The first adhesive layer 132 is adhered to the wafer sensing surface 121 and maintains a fixed adhesive gap. The wire arc portion of the bonding wire 124 above the main wafer 120 may be embedded in the first die layer 132. Then, as shown in FIG. 7E, a molding step is performed to form the package body 140 on the substrate 110 to seal the main wafer 120 and the first die layer 132. The package body 140 has a sealing height 141 on the substrate 110, which is greater than the thickness of the main wafer 120 and does not exceed the outer surface 134 of the pick-and-place sheet 131, so that the package body 140 completely seals the first surface. A die layer 132 does not cover the outer surface 134 of the pick and place sheet 131. As shown in FIG. 7F, a package singulation separation step is performed, and the substrate 110 is cut through the substrate 110 by a laser cutting device 10, and then the package body 140 is cut through, thereby finally forming a singulated and separated wafer package structure 400 ( As shown in Figure 7G).

According to a fifth embodiment of the present invention, another chip package structure 500 to which the protective sheet is attached to the wafer sensing surface is illustrated in a cross-sectional view of FIG. The chip package structure 500 is substantially the same as the chip package structure 100 of the first body embodiment except for variations from a multi-chip package to a single-chip package and a plurality of main components such as the metal cover 270 and the circuit board 280, wherein the first package corresponds to the first DETAILED DESCRIPTION OF THE INVENTION Elements of the same names and functions are denoted by the component numbers of the first embodiment, and the details of the details are omitted. The chip package structure 500 is a substrate 110, a main wafer 120 disposed on the substrate 110, a viscous protection sheet 130 adhered to the main wafer 120 in a pick-and-place manner, and a substrate 110 is formed on the substrate 110. The package 140. The chip sensing surface 121 can include a fingerprint identification area 123, and the first stick The crystal layer 132 preferably covers the fingerprint identification area 123 in its entirety.

The chip package structure 500 may further include a second die bond layer 550, such as a die attach material (DAM), formed between the main die 120 and the substrate 110. The second die bond layer The coverage area of 550 can be smaller than the coverage area of the first die layer 132.

In this embodiment, the chip package structure 500 can further include a metal cover 570 that can be covered by the package body 140. The metal cover 570 preferably has an opening 571 to expose the pick-and-place film. The outer surface 134 of 131. The chip package structure 500 can further include a circuit board 580. The substrate 110 and the metal cover 270 can be individually bonded to the circuit board 580. Therefore, the bonding stress of the metal cover 570 does not directly act on the package body 140. Adhesive protection sheet 130.

According to a sixth embodiment of the present invention, another chip package structure 600 to which the protective sheet is attached to the wafer sensing surface is illustrated in a cross-sectional view of FIG. 9 and a cross-sectional view of the elements in the respective process steps of FIGS. 10A to 10F. The wafer package construction 600 is substantially the same as the wafer package construction 100 of the first bulk embodiment, except for variations from a multi-chip package to a single-chip package and a master wafer-bonding connection to flip-chip bonding, wherein the same is true for the first embodiment. The elements of the names and functions are denoted by the component numbers of the first embodiment, and the details of the details are omitted. The chip package structure 600 includes a substrate 110, a main wafer 120 disposed on the substrate 110, a viscous protection sheet 130 adhered to the main wafer 120 in a pick-and-place manner, and a substrate 110 formed thereon. The upper package 140. The chip sensing surface 121 of the main wafer 120 can include a fingerprint identification area 123, and the first adhesive layer The 132 series preferably covers the fingerprint identification area 123 in its entirety.

The main chip 120 has a chip sensing surface 121 and a plurality of connection terminals 622. The chip sensing surface 121 is relatively far from the substrate, and the connection terminals 622 are electrically connected to the substrate 110. The adhesive protective sheet 130 is mainly composed of a pick-and-place sheet 131 and a first adhesive layer 132. The pick-and-place sheet 131 has an inner surface 133 and an outer surface 134. The first adhesive layer 132 is The inner surface 133 of the pick-and-place sheet 131 is covered. The package body 140 has a sealing height 141 on the substrate 110, which is greater than the thickness of the main wafer 120 and does not exceed the outer surface 134 of the pick-and-place sheet 131, so that the package body 140 completely seals the first surface. A die layer 132 does not cover the outer surface 134 of the pick and place sheet 131.

In this embodiment, the connection terminals 622 are disposed on the lower surface 624 of the main wafer 120 relative to the chip sensing surface 121. The connection terminals 622 may include at least one bump, so The crystal mode allows the main wafer 120 to be electrically connected to the substrate 110 via conductive bumps, and the first die layer 132 can be thinner in design.

Referring to Figures 10A through 10F, the method of fabricating the chip package structure 600 will be further described below. As shown in FIG. 10A, first, the substrate 110 is fixed on a working platform, and the substrate 110 has the external pads 111. As shown in FIG. 10B, thereafter, a flip chip bonding operation is performed to bond the main wafer 120 to the substrate 110, which is connected to the connection terminal 622 located on the lower surface 624 of the main wafer 120. The substrate 110, the chip sensing surface 121 of the main wafer 120 includes the fingerprint identification area 123, and can be connected to different surfaces by using a 矽-perforated or a crystal-side line connection. The fingerprint identification area 123 and the connection end point 122 are away from the substrate 110. As shown in FIG. 10C, after a protective sheet pick-and-place operation is performed, the adhesive protective sheet 130 is compliantly attached to the main wafer 120. The adhesive protective sheet 130 includes the pick-and-place sheet 131 and The first die layer 132. As shown in FIG. 10D, the package body 140 is formed on the substrate 110 in a sealed manner to seal the main wafer 120 and the first die layer 132. The package body 140 has a substrate on the substrate. The upper sealing height 141 is greater than the thickness of the main wafer 120 and does not exceed the outer surface 134 of the pick-and-place sheet 131, so that the package body 140 completely seals the first adhesive layer 132 and does not cover the pick-and-place The outer surface 134 of the sheet 131. As shown in FIG. 10E, a package singulation separation step is finally performed. A laser cutting device 10 can be used to cut into the substrate 110 and further cut through the package 140 to form a plurality of singulated and separated wafer packages. Construction 600 (as shown in Figure 10F).

According to a seventh embodiment of the present invention, another chip package structure 700 to which a protective sheet is attached to a wafer sensing surface is illustrated in a cross-sectional view of FIG. 11 except that a main component such as a metal cover 770 and a circuit board 780 is added. The wafer package structure 700 is substantially the same as the chip package structure 600 of the sixth embodiment, wherein the same names and functions as those of the first embodiment are denoted by the component numbers of the first embodiment, and will not be described again. Its details are the same. . A chip package structure 700 for attaching a protective sheet to a wafer sensing surface includes a substrate 110, a main wafer 120 disposed on the substrate 110, and a viscous protection adhered to the main wafer 120 in a pick-and-place manner. The sheet 130 and a package 140 formed on the substrate 110.

The main wafer 120 is disposed on the substrate 110, and the main wafer 120 There is a wafer sensing surface 121 and a plurality of connection terminals 622 on different surfaces. The chip sensing surface 121 is relatively far from the substrate, and the connection terminals 622 can be bumps electrically connected to the substrate 110 by flip chip bonding. The viscous protective sheet 130 is mainly composed of a pick-and-place sheet 131 and a first viscous layer 132. The adhesive protection sheet 130 is adhered to the wafer sensing surface 121 in a pick-and-place manner, so that the first adhesive layer 132 is adhered to the wafer sensing surface 121 and maintains a fixed adhesive gap, and the pick-and-place sheet The outer surface 134 of the 131 is parallel to the wafer sensing surface 121 without being affected by the horizontal error of the substrate 110. The chip sensing surface 121 includes a fingerprint identification area 123, and the first adhesion layer 132 preferably covers the fingerprint identification area 123 in a comprehensive manner. The package body 140 has a sealing height 141 on the substrate 110, which is greater than the thickness of the main wafer 120 and does not exceed the outer surface 134 of the pick-and-place sheet 131, so that the package body 140 completely seals the first surface. A die layer 132 does not cover the outer surface 134 of the pick and place sheet 131.

In this embodiment, the chip package structure 700 can further include a metal cover 770, which can be covered by the package body 140. The metal cover 770 preferably has an opening 771 to expose the pick-and-place film. The outer surface 134 of 131. The chip package structure 700 can further include a circuit board 780. The substrate 110 and the metal cover 770 can be individually bonded to the circuit board 780. Therefore, the bonding stress of the metal cover 770 does not directly act on the package body 140 and the Adhesive protection sheet 130. The fingerprint recognition area 123 is aligned in the opening 771 through the adhesive protection sheet 130.

In summary, the first to seventh embodiments of the present invention disclose a chip package structure in which a protective sheet is attached to a wafer sensing surface, in order to improve the loading and unloading. The protective sheet causes the problem that the horizontal level between the protective sheet and the main wafer is incomplete, and the main wafer does not need to be specially formed with a side notch and a crystal back cavity, so that the manufacturing cost can be reduced. In the overall chip package structure, the sub-wafer, the passive component, the metal cover and the circuit board may be integrated, and the electrical connection method of the main chip may be flip-chip bonding in addition to the wire bonding.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus equivalent changes made in the claims of the present invention are still within the scope of the present invention.

100‧‧‧ Chip package construction

110‧‧‧Substrate

111‧‧‧External mat

112‧‧‧Internal finger

120‧‧‧Main chip

121‧‧‧ wafer sensing surface

122‧‧‧Connection endpoint

123‧‧‧Fingerprint identification area

124‧‧‧welding line

130‧‧‧Adhesive protection film

131‧‧‧ pick and drop

132‧‧‧First sticky layer

133‧‧‧ inner surface

134‧‧‧ outer surface

140‧‧‧Package

141‧‧‧ Seal height

150‧‧‧Second layer

160‧‧‧ wafers

161‧‧‧The third layer of adhesion

162‧‧‧welding line

Claims (10)

A chip package structure for protecting a chip package on a wafer sensing surface, comprising: a substrate; a main chip disposed on the substrate, the main chip having a chip sensing surface and a connection end point, the chip sensing surface system Relatively far away from the substrate, the connection end is electrically connected to the substrate; a viscous protective sheet is mainly composed of a pick-and-place sheet and a first adhesive layer, the pick-and-place sheet has an inner surface and An outer surface, the first adhesive layer covers the inner surface of the pick-and-place sheet, and the adhesive protective sheet is adhered to the wafer sensing surface in a pick-and-place manner to make the first adhesive layer Adhering to the sensing surface of the wafer and maintaining a fixed adhesive gap, and the outer surface of the pick-and-place sheet is parallel to the wafer sensing surface without being affected by the horizontal error of the substrate; and a package is formed on the substrate To seal the main wafer, the encapsulation system has a sealing height on the substrate, which is greater than the thickness of the main wafer and does not exceed the outer surface of the pick-and-place sheet, so that the package completely seals the first adhesive Crystal layer and does not cover Take the place of the outer surface of the sheet. The protective chip package of claim 1 is applied to the chip package structure of the wafer sensing surface, and further comprises a second die layer formed between the main wafer and the substrate, the second die layer The coverage area is smaller than the coverage area of the first die layer. The protective chip package of claim 2 is attached to the chip package structure of the wafer sensing surface, and further comprises at least one wafer disposed on the substrate and located between the main wafer and the substrate, the second die bond The thickness of the layer is greater than the first The thickness of a die layer is such that the second die layer seals the sub-wafer. The protective chip package of claim 3 is attached to the chip package structure of the wafer sensing surface, and further comprises at least one passive component disposed on the substrate and located between the main wafer and the substrate, the second adhesive The crystal layer further seals the passive component. The protective chip package of claim 1 is attached to the wafer package structure of the wafer sensing surface, wherein the first adhesive layer completely covers the inner surface of the pick-and-place film, and one of the pick-and-place sheets The first dimension is greater than a second dimension of the one of the main wafers and less than a third dimension of the substrate such that the package partially covers the perimeter of the pick and place sheet. The protective chip package of claim 1 is attached to the chip package structure of the wafer sensing surface, and further comprises a metal cover covering the package, the metal cover having an opening to reveal the The outer surface of the sheet is placed. The protective chip package of claim 6 is attached to the chip package structure of the wafer sensing surface, and further comprises a circuit board, and the substrate and the metal cover are individually bonded to the circuit board. The chip package structure of the first aspect of the invention is attached to the chip package structure of the wafer sensing surface, wherein the connection end point is a peripheral pad located on the sensing surface of the chip, and the connection end is connected by a bonding wire. Pointing to the substrate, the wire is embedded in the first die layer in a line arc portion above the main wafer. The protective chip device of claim 1 is applied to a chip package structure of a wafer sensing surface, wherein the connection end is disposed on a lower surface of the main wafer relative to the sensing surface of the wafer, and the connection end is included At least one bump. The protective sheet garment according to any one of claims 1 to 9 is attached to the wafer The chip package structure of the sensing surface, wherein the chip sensing surface comprises a fingerprint identification area, and the first adhesive layer completely covers the fingerprint identification area.