TWI255027B - Method of manufacturing multi-chip stacking package - Google Patents

Abstract

The present invention relates to a method of manufacturing multi-chip stacking package and the packaging piece made thereby. The method of manufacturing multi-chip stacking package of the present invention comprises stacking at least two chips by flip-chip bonding technique in which the upper and the lower chips are connected by the bumps. Because the lower chip remains on the whole wafer without being cut during the flip-chip bonding, the whole wafer can be used in batch under the flip-chip operation. In addition, to protect the stacked chips from external damage during the process, a double die-pressing step by segmentation is conducted to protect the internal structure and wiring.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a multi-wafer stack and a package thereof, and more particularly to a wafer stacking process by flip chip bonding (fHp-chip bucking). Multi-chip module. BACKGROUND OF THE INVENTION In the face of e-consumer products, the requirements for ease of portability are highly beneficial, and various use functions are also expected to be integrated. Multi-chip module packaging technology is undoubtedly one of the best ways to meet the above requirements. However, in order to integrate the functions of a plurality of wafers and reduce the area occupied by the packages, the technology mostly requires stacking the wafers into a package of a body structure. 1 is a flow chart for manufacturing a conventional multi-wafer stacked package. In steps 1 1 1 and 1 2 1, the first wafer and the second wafer are respectively inspected for inspection, and the wafer and the bumps thereon are inspected for defects. Following the steps 1 1 2 and 1 2 2, the first and second wafers that have passed the inspection are separately wafer-cut, so that the plurality of first wafers 21 and the second wafers on the first wafer are on the wafer. The plurality of second wafers 2 2 become independent individuals. The first wafer 2 1 having a smaller area is flip-chip bonded and stacked on the second wafer 2 2, i.e., the corresponding bumps 2 3 on the two wafers are joined together, as in step 丨3 〇. In step 140, the two stacked wafers are fixed to a substrate 24, and the passive surface of the wafer 2 2 is fixed by the epoxy tree g 2 5 . The upper surface of the substrate 24. A plurality of wiring pads 2 2 are disposed around the active surface of the second wafer 2 2, and the wiring pads 2 2 1 and the substrate are connected by a plurality of metal bonding wires 26 through a process of step 150 2 4 solder pads on the upper surface. The structure of the stacked wafer and metal zinc wire 26 is very fragile H:\HU\LGC\ 曰月光中说\ASEK271(74498>.DOC one$— This paper scale applies to China National Standard (CNS) A4 specification (2i〇 x 297 公董) " !255〇27

V. INSTRUCTION DESCRIPTION (2) Weakness is required. The stamping process of step 1 6 is required, which is completely covered on the upper surface of the substrate 24 by the stamper colloid 27 for protection purposes. There are a plurality of ball pads on the lower surface of the substrate 24, and a plurality of solder balls 28 are formed thereon, as in the step 170. There will be several completed products on the same substrate 24, so the splitting operation of step 〇8 需要 is required to cut each product into separate packages 2 〇. If there are several problems in the prior art, it is summarized as follows: (1) The flip chip stacking process of the wafer adopts the operation mode of a single wafer to a single wafer, so it takes a considerable time to pick and place each wafer. . (2) Each wafer requires a precise flip-chip placement action, and the optical assisted system requires the accuracy of flip-chip bonding (a few micrometers). () The ninth film in the stamping process is liable to cause crystal collapse or crystal cracking due to lack of protection due to lack of protection. A brief description

——, · -V The part of the time required for the position correction of the batch object from 曰曰Tj=- fruit. Multi-wafer stack manufacturing method, batch object, reducing wafer pick-and-place

In order to achieve the above object, the mechanical error of the operation of fixing the entire wafer f can be improved by providing a structure for protecting the wafer and avoiding damage caused by external force. The present invention discloses a manufacturer of a multi-wafer stack

1255027 A7 ---^_____ B7 V. Inventive says 'one: one ----- and its package, the multi-wafer stack utilizes and at least two wafers are bonded and stacked in a lapped manner. The area of the first wafer stacked on top of the wafer X is removed from the first wafer that has been cut, and the second wafer below is still present on the other uncut second wafer during the egg bonding. After the second crystals are bonded to the first wafer, they are overlaid on each of the first wafers by a stamper. After the first wafer is well protected, it is cut to all associated post-processes, including a second stamper to completely protect the second wafer from the metal bond wire. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart showing the manufacture of a conventional multi-wafer stacked package; FIG. 2 is a schematic cross-sectional view of a conventional multi-wafer stacked package; Figure 4a is a schematic view of a first wafer and a first wafer of the present invention; Figure 4b is a schematic view of a second wafer and a second wafer of the present invention; Figure 5 is a schematic view of the present invention FIG. 6 is a schematic view showing a stacked structure after a primary molding of the present invention; and FIG. 7 is a schematic cross-sectional view showing a preferred embodiment of the multi-wafer stacked package of the present invention.

Component symbol says I 2 0 custom package 2 2 brother two wafer 24 substrate 2 6 metal wire HAHU\LGC\ 曰月光中 says \ASEK271(74498).D〇C 21 first wafer 23 bump 25 epoxy resin 2 7 Compression Mold 6 - This paper scale applies to China National Standard (CNS) A4 specification (210X297 public ^' 1255027

42 first wafer 4 4 second wafer 62 wiring pad 6 4 cutting channel 71 metal bonding wire 7 3 substrate 7 5 second molding compound 2 8 solder ball 4 1 first wafer 4 3 brother two wafer 61 镕Bump 63 First Compression Mold 7 〇 Multi-Wafer Stack Package 72 Epoxy 74 Solder Balls Preferred Embodiments FIG. 3 is a manufacturing flow diagram of the multi-wafer stacked package of the present invention. In step 31: first check the line of the first wafer 42 of the first wafer 41 and whether it is good or not; if it is combined with the inspection standard, proceed to step η], and cut each first wafer 4 2 into Today, > evil - 丄,," In step 3 2 1, it is checked in the same manner whether the second wafer 44 on the second wafer 43 is good, and if it is in compliance with the inspection standard, the next step is performed. As shown in Figures 4a and ❹, the first wafer 42 has a smaller area than the second wafer 44, and both of the wafers have bumps. At step 322, the first wafers 42 are stacked on the first dies 44 of the second wafer 43, respectively, and a suitable pressure and temperature are applied to cause the bumps to spliced together. As shown in Fig. 5, the second wafer 43 has the same number of first wafers 42 covered by the second wafers 4, and the wafers whose edges are incomplete are not necessarily subjected to the same flip chip process. In order to protect the first wafer 42 from damage caused by any external force in the subsequent process, step 3 2 3 is required to cover the first stamper colloid 6 3 on the first wafer 4 2 , but the wiring pad of the second wafer 4 4 Can not be covered (as shown in Figure 6). This step can be done with liquid sealant for HAHU\LGC\Sunlight. \ASEK271(74498).D〇C-η This paper scale applies towel® S fresh (CNS) Α4 size (210 X 297 public) 1255027 A7 B7 V. INSTRUCTION DESCRIPTION (5) The method of the industry is to place a liquid molding compound on the first wafer 42 one by one. At step 324, the first wafer 43 is cut into individual units, i.e., the configuration in which each of the first wafers 42 and the second wafers 44 are stacked is separated by a dicing street 64. The individual stacked wafers are affixed to the substrate 73 in accordance with step 303, and the non-line side of the second wafer 44 is adhered to the upper surface of the substrate 73 with an epoxy resin 72. In step 340, a plurality of metal bonding wires 71 are used to connect the bonding pads 6 2 of the second wafer 4 to the pads of the substrate 733. After the wire is completed, the second wafer 44 and the metal bonding wire 71 are required to be stamped, and the second molding compound 75 is overlaid on the first molding compound 63 and the substrate 73, as in step 350. At step 360, the solder balls 74 are soldered directly to the ball pads on the lower surface of the substrate 73. There will be several completed products on the same substrate 73, so it is necessary to cut each of the production ports into individual multi-wafer stacked packages 7 〇, as in step 3 〇. Referring to FIG. 5 and FIG. 6 , it can be seen that the second wafer 4 3 is used as a batch object of the flip chip operation, so that the process of flip chip bonding of the first wafer 4 2 can be continuously performed on the wafer. Therefore, the operation and time of each of the second wafers 4 are omitted from the conventional technique. On the other hand, the manufacturing process of the wafer is done using a precise mask and related precision equipment, so the relative position between each wafer has a multiple relationship of sufficient spacing. The machine can use the fixed distance value as the displacement basis for the joint, and it is not necessary to repeatedly confirm the fixed position and the reference point of the second wafer 44. Figure 7 is a multi-wafer stacked package 70 produced in accordance with the manufacturing process of the present invention. The utility model is characterized in that there are two laminating mold structures, and the second molding compound 75 is coated on the outside of the first molding compound colloid 63 for the purpose of segment protection, so that the first wafer 42 is not scratched or Touch and crack and damage. H:\HU\LGC\Sunlight in the moonlight \ASEK271(74498).DOC a g paper size applicable to China National Standard (CNS) A4 specification (2l〇x297 mm) -—--- 1255027 A7 B7 V. Invention The technical content and technical features of the present invention are disclosed above, but those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should not be limited by the embodiments, and should be covered by the scope of the following claims. H:\HU\LGC\ ASEK271 (74498> DOC Ό This paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm)

Claims (1)

1255(10) Patent Application No. 2029 ^—:::” Chinese Patent Application Replacement (94 Years Butterfly Factory: K: D8 • ->..!» ^ mm-ΛΤ·· »·%«>« .... . , , .__ _ 6. Patent application scope 1. A method for manufacturing a multi-wafer stack, comprising the steps of: flip-chip bonding a plurality of first wafers to a plurality of seconds on a second wafer; Was, covering the first wafer with a first molding compound; cutting the second wafer to make the combined second wafer, the first wafer, and the first molding compound into separate units; The non-line surface of the wafer is fixed on a substrate; and the second wafer and the substrate are electrically connected by using a plurality of metal bonding wires. 2. The manufacturing method of the multi-chip stack according to claim 1 of the patent, further comprising The second stamper colloid covers the second wafer, the first stamper colloid and the metal bond wire. 3. The method for manufacturing a multi-chip stack according to claim 1, further comprising a plurality of solder balls a step of bonding a plurality of ball pads on the lower surface of the substrate. 4. A multi-wafer stack package comprising: a substrate having an upper surface, the upper surface comprising a plurality of pads; a first wafer 'having a line surface; and a second wafer having a line surface and a line a road surface 'where the circuit surface is bump-bonded to the wiring surface of the first wafer, and the non-line surface is disposed on the upper surface of the substrate; a first molding compound for covering the first wafer; and a plurality of metals a bonding wire for electrically connecting the pad of the substrate to the second wafer. 5. The wafer stack package of claim 4, wherein the convex 74498-940908.doc -1 - the paper size is applicable to China National Standard (CNS) A4 Specification (210X 297 mm) 1255027 A8 B8 C8 D8 々, the patent application range is a material selected from the group consisting of tin, tin-lead alloy and gold. a multi-chip stack package of 4 or more, further comprising a plurality of solder balls disposed on a lower surface of the substrate. 7. The multi-die stack package of claim 4, further comprising a second stamper colloid For covering the second wafer and the plurality of metal bonding wires. 8. The wafer stacking package of claim 4, further comprising a bottom filling glue for filling a gap portion between the bumps 74498-940908.doc This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)