1254421 五、 發明説明（ fjl領域 —本發明係關於一種多晶片堆疊之製造方法，尤其係關於 —種採用覆晶接合（flip_ehip bGnding)之方式完成晶片堆最 的製造方法。 背景 面對電子消費產品對於攜帶容易性之要求日狀切，而 f種使用功能也希望整合在一起，多晶片模組的封裝技術 Z疑是滿足上述需求的最佳方式之_。惟該項技術為了整 t多個晶片的功能並減少封裝件所佔的面積，大多需要將 晶片堆疊成立體構造的封裝件。 圖1係習知之一多晶片堆疊封裝件的製造流程圖。在步 驟111與121，是分別做第一晶圓及第二晶圓的進料檢 查’檢視晶圓及其上之凸塊是否有缺陷存在。緊接著步驟 112與122，將檢驗合格的第一晶圓及第二晶圓分別進行 晶圓切割，使第一晶圓上之複數個第一晶片及第二晶圓上 複數個第二晶片成為獨立的個體。將面積較小的第一晶片 覆晶接合並堆疊在第二晶片上，即該兩個晶片上對應的凸 塊鎔接在一起，如步驟130。在步驟140，使該兩個堆疊 在一起的晶片固著於一基板，係利用環氧樹脂固著該第二 晶片的非線路面（passive surface)於該基板的上表面。該 第一晶片的線路面（active surface ).四周有複數個接線銲 墊，經由步騾1 5 〇打線的製程以複數個金屬銲線連接該接 線銲墊與基板上表面的銲墊。該堆疊之晶片及金屬銲線的 構造十分脆弱，所以需要步驟丨6 〇的壓模製程，其利用壓 I_H:\HU\LGC\ a 月光台灣專利\ASEK270(74497).DOC — 4 本紙張尺度適用中國國家標準(CNS) A4規格(21〇 χ 297公釐） 12544211254421 V. Field of the Invention (Fjl Field - The present invention relates to a method of manufacturing a multi-wafer stack, and more particularly to a method for fabricating a wafer stack in a flip-ehip bGnding manner. For the convenience of carrying the daily requirements, and the f-use function is also expected to be integrated, the packaging technology of the multi-chip module is suspected to be the best way to meet the above requirements. The function of the wafer and the area occupied by the package are mostly required to stack the wafers into a package of bulk construction. Figure 1 is a flow chart for manufacturing a multi-wafer stacked package. In steps 111 and 121, respectively A wafer and second wafer feed inspection 'views the wafer and the bumps thereon for defects. Next, in steps 112 and 122, the qualified first wafer and the second wafer are separately crystallized. Circularly cutting, the plurality of first wafers on the first wafer and the plurality of second wafers on the second wafer are independent individuals. The first wafer having a smaller area is flip-chip bonded and Stacked on the second wafer, that is, the corresponding bumps on the two wafers are joined together, as in step 130. In step 140, the two stacked wafers are fixed to a substrate using epoxy resin. Fixing a passive surface of the second wafer on the upper surface of the substrate. The active surface of the first wafer has a plurality of wiring pads around the circuit, and the process of stepping the line through the step The bonding pads of the wiring pads and the upper surface of the substrate are connected by a plurality of metal bonding wires. The structure of the stacked wafers and the metal bonding wires is very fragile, so a compression molding process of step 丨6 需要 is required, and the pressure I_H:\HU is utilized. \LGC\ a Moonlight Taiwan Patent\ASEK270(74497).DOC — 4 This paper scale applies to China National Standard (CNS) A4 specification (21〇χ 297 mm) 1254421
五、發明説明（2 模膠體完全覆蓋在基板的上表面以達到保護的目的。在基 板的下表面具有複數個球銲#，f要形成複數個銲球在二 上：如步驟170的植球。同-片基板上會有數個已完成： 產品’因此需要步驟i 8〇的分剖動作將每個產品切開成獨 立的封裝件。 如前所述該項習知技術存在幾個問題，兹歸納如下： ⑴晶片之覆晶堆叠製程係採單個晶片對單個晶片的作 業万式，故需耗費相當的時間在取放每個晶片。 (2)每個堆疊的晶片都需要精密的覆晶放置動作，與光 學輔助對準系統才能達到覆晶接合的精度要求（' 約 幾個微米）。 發_明篮要說明 本毛明〈目的係提供一種多晶片堆疊之製造方法，係以 整片晶圓作為覆晶作業的批次對象，；咸少晶片取放與位置 校正所需的時間。 本晷月人一目的係提供—種固定整片晶圓的作業方 式’可減少晶片每次取放動作所伴隨之機械誤差，而提昇 覆晶接合的精度。 、為了達到上述目W ’本發明揭示一多晶片堆疊之製造方 法及多片堆®係利用且至少兩個晶片以覆晶接合之方 式、、口 口並堆璺。堆疊在上方之第一晶片係由第一晶圓上取 下，其面積較小，且下方之第二晶片於覆晶接合時仍存在 於：-未切割的第二晶圓上。待第二晶圓上的第二晶片皆 ”第日曰片結合芫畢，再以底部充填膠（underfill H：^Gaa^-^^SEK27〇(74497,D〇C —5 ^張尺舰财 1254421 五 、發明説明（ A7 B7 州㈣无滿在覆晶接合之間隙處’或 膠體於每—個m 一曰 六曰μ。1吵復盖 母個…日片上。在晶片受到良好之保護 :相關的後製程4中包含在每一個第二晶片之四周的銲 二上形成Μ ’與最後切割使每個多晶片堆疊封裝 獨立 < 元件。 η 本發明將依照後附圖式來說明，其中： 圖1係一習知之多晶片堆疊封裝件之製造流程圖； 圖2係本發明之多晶片堆疊封裝件之製造流程圖； 圖3 a係本發明之第一晶圓與第一晶片之示意圖· 圖3b係本發明之第二晶圓與第二晶片之示竟圖· 圖4係本發明之第-晶片堆疊在第二晶圓：：示意圖； 及 圖5係本發明之多晶片堆疊封裝 面示意圖。 牛< 車父佳實施例之剖 孟件符號n 3 1第 曰田 圓 3 2第一晶片 3 3弟二晶圓 51鎔接凸塊 5 3外接凸塊 較佳實施例說 圖2係本發明之多晶片堆疊封裝 开又製造流程圖。在步 驟2 1 1 ’先檢查第一晶圓之第一晶 σ 了、& 片的、、泉路及其上的凸塊 疋口、良好。若是合於檢驗標準則進 订步驟2 1 2，將每個第 規格(210X297公濩 4第二晶片 2底部充填膠 明V. Description of the invention (2 The mold colloid completely covers the upper surface of the substrate for protection purposes. There are a plurality of ball welds # on the lower surface of the substrate, f is to form a plurality of solder balls on the second: the ball placement as in step 170 There will be several completed on the same substrate: the product 'Therefore, the splitting action of step i 8〇 is required to cut each product into separate packages. As mentioned above, there are several problems with the prior art. The summary is as follows: (1) The flip chip stacking process of the wafer adopts a single wafer to operate on a single wafer, so it takes a considerable time to pick and place each wafer. (2) Each stacked wafer requires precise flip chip placement. Action, and optical-assisted alignment system can achieve the accuracy requirement of flip-chip bonding ('about a few micrometers). The hair basket is to explain the method of manufacturing a multi-wafer stack, which is a whole piece of crystal. The circle is used as the batch object of the flip chip operation; the time required for the wafer pick-and-place and position correction is less. The purpose of this month is to provide a method for fixing the whole wafer, which can reduce the wafer pick-and-place operation. move With the mechanical error, the precision of the flip chip bonding is improved. In order to achieve the above, the present invention discloses a method for manufacturing a multi-wafer stack and a multi-chip stack using at least two wafers in a flip chip bonding manner. The first wafer stacked on the first wafer is removed from the first wafer, and the second wafer is still present at the time of flip chip bonding: - uncut second On the wafer, the second wafer on the second wafer is “the first day of the film is combined with the bottom, and then the bottom is filled with glue (underfill H:^Gaa^-^^SEK27〇(74497, D〇C — 5 ^ Zhang Jiu Shipai 1254421 V. Description of the invention (A7 B7 State (4) is not full of gaps in the flip-chip joints' or colloids in each - m 曰 曰 曰 μ. 1 复 盖 cover the mother ... on the film. Good protection: The associated post-process 4 includes the formation of Μ on the solder 2 around each of the second wafers and the final cut to make each multi-wafer stack package independent < component. η The present invention will follow the following figures To illustrate: Figure 1 is a conventional multi-wafer stack package 2 is a flow chart for manufacturing a multi-wafer stacked package of the present invention; FIG. 3 is a schematic view of a first wafer and a first wafer of the present invention; FIG. 3b is a second wafer and a second of the present invention FIG. 4 is a schematic diagram of a first wafer stacked on a second wafer of the present invention; and FIG. 5 is a schematic diagram of a multi-wafer stacked package surface of the present invention. Meng symbol n 3 1 Ditian round 3 2 first wafer 3 3 second wafer 51 凸 bump 5 3 external bump preferred embodiment FIG. 2 is a multi-wafer stack package opening and manufacturing process of the present invention In step 2 1 1 'first check the first crystal σ of the first wafer, the & slice, the spring path and the bump on the bump, good. If it is in compliance with the inspection standard, proceed to step 2 1 2, and fill each of the first specifications (210X297 mm 4 second wafer 2 bottom filling gel)
H:\HU\LGC\曰月光台灣專利\八§欣270(74497) DOC 6 1254421 、發明説明（ 太日曰片切割為獨立之單元。在步驟2 2 1，以同樣的方式檢 第一曰曰圓上的第二晶片是否良好，若是合於檢驗標 準則進行下一步驟。其中第一晶片之面積較第二晶片小， 且該兩個晶片皆已具有凸塊，而第二晶片之四周並具有複 數個銲塾。 在步驟2 2 2 ’將第一晶片堆疊在第二晶圓的第二晶片 2，並施加合適之壓力與溫度使凸塊互相鎔接在一起。在 f二晶圓上有相對第二晶片之同樣數量的第—晶片相互覆 晶接合，其邊緣不完整的第二晶片則沒有必要進行覆晶製 私。為了保護覆晶接合之凸塊不受到應力之破壞，所以需 要步驟22 3在第一晶片及第二晶片中間之空隙處渗注入底 部充真膠在步驟2 2 4，將底部衝填膠加熱使其化學硬化 反應接近完全。如步驟22 5，在第二晶片之四周的錦塾上 $成凸塊或植上錫錯球’該凸塊或錫错球係作為堆叠封裝 件與外在系統（主機板，圖未示出）之電性接點。最後， =心m已完成之每_個堆疊封裝件，使其成為 可獨立應用之元件。 發月《特欲係在於以第二晶圓為製程之批次作業的單 就是在同-片晶圓上完成相同的製程動作，例如覆 卵接合與注入底部衝填膠等。除了前述之製程外，尚可包 ^雷射正印打在第二晶片之非線路面，與液態封膠在第一 “上’待所有之製程完畢’再進行使 rr元件的靖程，因此較習知技術省去繁複= 卵片的動作與時間。另一方面晶圓之製造過程係使用精準 _月光台灣專利\ASEK270(74497).D〇C — η ΐ紙張尺度家鮮(CNS) 1254421H:\HU\LGC\曰月光Taiwan Patent\八§欣270(74497) DOC 6 1254421, Invention Description (Tai Ri Bun is cut into independent units. In step 2 2 1, the first way is checked in the same way. Whether the second wafer on the round is good, if the inspection standard is met, the next step is performed. The area of the first wafer is smaller than that of the second wafer, and both wafers have bumps, and the periphery of the second wafer And having a plurality of solder bumps. In step 2 2 2 'stack the first wafer on the second wafer 2 of the second wafer, and applying suitable pressure and temperature to bump the bumps together. The same number of first wafers on the second wafer are flip-chip bonded to each other, and the second wafer having incomplete edges does not need to be flip-chip. In order to protect the bumps of the flip chip from stress, the bumps are not damaged by stress. Step 22 3 is required to infiltrate the bottom-filled glue in the gap between the first wafer and the second wafer. In step 2 24, the bottom-filling glue is heated to make the chemical hardening reaction nearly complete. As in step 22 5, in the second The koi on the periphery of the wafer is made into a bump Or implanted with tin bumps. The bump or tin bump is used as an electrical contact between the stacked package and the external system (main board, not shown). Finally, = every square of the completion of the heart m The package makes it a component that can be applied independently. The special purpose of the batch is to perform the same process operation on the same wafer, such as ovulation bonding. In addition to the above-mentioned process, the laser can be printed on the non-line surface of the second wafer, and the liquid sealant is placed on the first "on the top of all processes". The rr component of Jingcheng, so the conventional technology saves the trouble of the complex = egg action and time. On the other hand, the wafer manufacturing process is accurate _月光台专利\ASEK270(74497).D〇C — η ΐ paper scale Home Fresh (CNS) 1254421
的光罩與相關精密設備完成，所以每個晶片間的相對位置 存在確定的間距之倍數關係。機台可利用該固定之間距值 作為接合時之位移依據，不需要一再確認第二晶片之固定 位置與基準點。 圖3 a係本發明之第一晶圓3 1與第一晶片3 2之示意圖； 及圖3 b係本發明之第二晶圓3 3與第二晶片3 4之示意圖。 第一晶片3 2之面積較第二晶片3 4之面積小，故將第一晶片 32切割並取下覆晶接合在第二晶片34上，如圖4之所示。 在第二晶片34之四周有複數個銲墊（圖未示出），該複數 個鲜塾將形成ώ塊或植上錫鉛球作為與外在系統之接點。 圖5係本發明之多晶片堆疊封裝件之一較佳實施例之剖面 tf思圖，其中在第二晶片3 4之四周銲墊設有外接凸塊$ 3， 薇兩個晶片中間有一底部充填膠5 2填充在鎔接凸塊$丨之 間。 本發明之技術内容及技術特點以揭示如上，然而熟乘本 項技術之人士仍可能基於本發明之重點及揭示而做種種不 背離本發明精神之替換及修飾。因此，本發明之保護範圍 應不限於實施例所闡述者，應、為以下申請專利範圍又:涵 蓋。 / 口 H:\HU\LGa 日月光台灣專利认5£]<：270(74497).〇〇€ 一 8 本紙張尺度適财關家鮮(CNS) Α4規格_ χ 297公董）The reticle is completed with related precision equipment, so the relative position between each wafer has a multiple relationship of a certain pitch. The machine can use the fixed distance value as the displacement basis for the joint, and it is not necessary to repeatedly confirm the fixed position and the reference point of the second wafer. 3a is a schematic view of a first wafer 31 and a first wafer 3 2 of the present invention; and FIG. 3b is a schematic view of a second wafer 3 3 and a second wafer 34 of the present invention. The area of the first wafer 32 is smaller than the area of the second wafer 34, so the first wafer 32 is cut and the flip chip is bonded to the second wafer 34, as shown in FIG. A plurality of pads (not shown) are disposed around the second wafer 34, and the plurality of fresh mashes are formed into lumps or tin-plated shots as contacts with the external system. 5 is a cross-sectional view of a preferred embodiment of the multi-wafer stack package of the present invention, wherein the pads are provided with external bumps $3 around the second wafer 34, and a bottom fill is provided between the two wafers. The glue 5 2 is filled between the splicing bumps $丨. The technical content and technical features of the present invention are disclosed above, but those skilled in the art may still make various substitutions and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should not be limited to those described in the embodiments, and should be covered by the following claims. / 口 H:\HU\LGa ASE Moon Taiwan Patent Recognized 5 £]<:270(74497).〇〇€一 8 Paper Size 适 关 关 ( (CNS) Α 4 Specifications _ χ 297 DON