TW551016B - Circuit board manufacturing process of embedded resistor - Google Patents
Circuit board manufacturing process of embedded resistor Download PDFInfo
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- TW551016B TW551016B TW91117237A TW91117237A TW551016B TW 551016 B TW551016 B TW 551016B TW 91117237 A TW91117237 A TW 91117237A TW 91117237 A TW91117237 A TW 91117237A TW 551016 B TW551016 B TW 551016B
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551016 五、發明說明α) 1.發明領域: 本發明係為一種埋入式電阻器(Embedded Resistor) 之電路板製程,特別是關於一種直接在印刷電路板 (Printed Circuit Boards)之導電線路(circuitry traces)中植入複數埋入式電阻器(Resistors)之電路板製 程0 2.發明背景:551016 V. Description of the invention α) 1. Field of the invention: The present invention is a circuit board process of an embedded resistor, especially a circuitry directly on printed circuit boards (circuitry). Traces) circuit board process of implanting multiple embedded resistors (Resistors) 0 2. Background of the invention:
按,隨著科技的進步及電子產品的小型化趨勢,許多 的電子零組件及印刷電路板都被要求縮小體積或面積,因 此在電子零組件中的被動元件發展趨勢已逐漸由傳統獨立 式被動元件(Discrete Passives)轉變成埋入式被動元件 (Embedded Passives)的功能化設計。 所謂埋入式被動元件是指將電阻器或電容器等被動元 件的結構壓製成薄片,直接在印刷電路板的製造過程中植 入印刷電路板中以與其上方之導電線路連接形成一體,這 樣結構可參考如美國專利號第5, 07 9, 069號、第5, 1 55, 655 號、第5, 161,086 號、第 5,261,153 號、第5,347,258 號及 第 5, 466, 892 號。According to the advancement of technology and the miniaturization of electronic products, many electronic components and printed circuit boards are required to reduce the size or area. Therefore, the development trend of passive components in electronic components has gradually changed from traditional independent passive Components (Discrete Passives) are transformed into functional designs of Embedded Passives. The so-called embedded passive component refers to the structure of a passive component such as a resistor or a capacitor is pressed into a thin sheet, which is directly implanted in the printed circuit board during the manufacturing process of the printed circuit board to be integrated with the conductive lines above it. References are, for example, U.S. Patent Nos. 5, 07 9, 069, 5, 1 55, 655, 5, 161, 086, 5,261, 153, 5, 347, 258, and 5, 466, 892.
以埋入式電阻器來說,其中單位厚度阻值 (Resistivity)與材料特性有關,電阻寬度與導體成線路 能力(Patterning)有關,一般所選擇的電阻材料需具備高 阻值(Electrical Resist ivity)低電阻溫度係數 (Temperature Coefficient of Resistivity, TCR)且容For embedded resistors, the resistance per unit thickness (Resistivity) is related to the characteristics of the material, and the resistance width is related to the conductor's ability to form a circuit (Patterning). Generally, the selected resistance material needs to have a high resistance (Electrical Resistivity) Low Temperature Coefficient of Resistivity (TCR) and capacitance
第4頁 551016 五、發明說明(2) 易加工,目前可選用的材料有兩種,第一種為金屬合 膜,如 NiP、NiWP、NiCr 及 NiCrAlSi 等,第二種為= 厚膜(Polymer Thick Film,PTF),如感應複合材料 (Inductive Composite),而傳統製造方法是°將先將印刷 電路板之金屬導線層蚀刻好’再將此被動材料層塗佈至談 金屬導電層之上,而以第一種材料而言可使用電解鍍著^ (Electroplate)、濺鍍法(Sputter)、無電解電鍍法 (Electroless)或者CVD等方法,而第二種材料則是以 網版印刷法為主。 ' 然而該埋入式電阻器製程上的缺點是誤差變異性大, 該誤差變異性主要是元件電阻值與線路阻抗之不匹配,這 是由元件本身的誤差變異性、元件之串聯電感(Series Inductance)與感應電抗(inductive Resistance)三者所 共同造成的,其中串聯電感及感應電抗相當小,幾乎可以 忽略。 該埋入式電阻之誤差變異性以金屬合金薄膜材料而 s ’雖然誤差變異性小但只能提供低阻值,而高分子厚膜 材料是以環氧樹脂為主體的材料,故可提供很高的阻值, 但誤差變異性大,因此如何解決高阻值且低誤差變異性就 成了製程上急待克服的課題。以碳墨電阻2來說,其在印 刷電路板1上之上視示意圖如圖一所示,該印刷電路板上 設有金屬導電線路3,而該碳墨電阻2即電氣連接在該導電 線路3上’ 一般為尋求低誤差變異性則必須將每一個碳墨 電阻2都製成相同的幾何形狀,才能將誤差變異性降到最Page 4 551016 V. Description of the invention (2) Easy to process, there are currently two types of materials that can be used. The first is a metal composite film, such as NiP, NiWP, NiCr, and NiCrAlSi. The second is = thick film (Polymer Thick Film (PTF), such as Inductive Composite, and the traditional manufacturing method is to etch the metal wire layer of the printed circuit board, and then coat the passive material layer on the metal conductive layer. For the first material, methods such as electroplating, sputtering, electroless plating, or CVD can be used, while the second material is screen printing. the Lord. '' However, the disadvantage of the embedded resistor process is that the error variability is large. The error variability is mainly due to the mismatch between the resistance value of the component and the line impedance. This is caused by the error variability of the component itself, the series inductance of the component (Series (Inductance) and inductive resistance (inductive resistance) caused by the three, in which the series inductance and inductive reactance are relatively small, almost negligible. The error variability of the embedded resistance is a metal alloy thin film material. Although s' has a small error variability, it can only provide a low resistance value. The polymer thick film material is based on epoxy resin, so it can provide High resistance value, but large error variability, so how to solve high resistance value and low error variability has become an urgent problem to be overcome in the process. Taking carbon ink resistor 2 as an example, the top view on printed circuit board 1 is shown in Fig. 1. The printed circuit board is provided with a metal conductive circuit 3, and the carbon ink resistor 2 is electrically connected to the conductive circuit. 3 on 'Generally, in order to find low error variability, each carbon ink resistor 2 must be made into the same geometry to reduce the error variability to the maximum.
551016 五、發明說明(3) 小,然而以傳統之製程方式,所製造的碳墨電阻2都會有 不同的幾何形狀,如囷二A、B、C、D所示即為該碳墨電阻 2之形狀立體示意圖,甚至會有與導電線路的接觸開路之 情形產生,而該埋入式電阻器根本無法重工,而形成不良 品 ° 職是’本案發明人即為解決上述現有埋入式電阻器製 程上所具有的缺失’乃特潛心研究並配合學理之運用,提 出另一種新式的埋入式電阻器之電路板製程,能夠達到幾 近相同的幾何形狀,使誤差變異性能降到最低,可有效善 上述缺失。 3 ·發明概述: 本發明之主要特徵係在於提供一種埋入式電阻器之電 路板製程,首先在一上方為一金屬層,下方為一絕緣層的 基板上蝕刻該金屬層以形成一第一導電線路,並於該第一 導電線路中形成有複數電阻凹孔。 接著嵌入該薄型埋入式電阻器至該電阻凹孔中,並 ^該第一導電線路能電氣連接至該薄型埋人式電阻器之侧 陶㈣磨該薄型埋入式電阻器之上方,使該薄型 式電阻器能與該第一導電線路之厚度相近。 =後在該導電線路及該薄型埋入式電阻器上方電鍍一 方塗你層:形成—第二導電線路’再於該第二導電線路上 :::-抗蝕刻薄m,並預留一小於該電阻凹孔之小孔, 以便姓刻Mi電線路’使該第:導電線路能凸伸出該551016 V. Description of the invention (3) Small, but in the traditional manufacturing process, the carbon ink resistance 2 manufactured will have different geometries, as shown in Figure 2 A, B, C, D is the carbon ink resistance 2 The shape of the three-dimensional schematic diagram may even cause open contact with the conductive line, and the embedded resistor cannot be reworked at all, and a defective product is formed. The job of the inventor is to solve the above existing embedded resistor. The "missing in the manufacturing process" is an intensive research and cooperation with the application of science, and proposes another new type of embedded resistor circuit board manufacturing process, which can achieve nearly the same geometry, so that the error variation performance is minimized. Effectively address the aforementioned shortcomings. 3 · Summary of the invention: The main feature of the present invention is to provide a circuit board manufacturing process for embedded resistors. First, a metal layer is etched on the substrate above the insulating layer to form a first layer. A conductive circuit is formed with a plurality of resistance recesses in the first conductive circuit. Then embed the thin embedded resistor into the resistance recess, and ^ the first conductive line can be electrically connected to the side of the thin embedded resistor by honing the top of the thin embedded resistor so that The thin-type resistor can be close to the thickness of the first conductive circuit. = Later, electroplating one layer on the conductive line and the thin embedded resistor: coating-forming-the second conductive line 'on the second conductive line :::-anti-etching thin m, and reserve a less than The small hole of the concave hole of the resistor, so that the electrical circuit of Mi is engraved so that the first: the conductive circuit can protrude from the
第6頁 551016 五、發明說明(4) 電阻凹孔上方,讓該第二薄導電線路能電氣連接至該薄型 埋入式電阻器上方,以增加該第一及第二導電線路與該薄 楚埋入式電阻器的電氣連接面積。最後將該抗蝕刻薄膜從 該第二薄金屬層上方剝離開,即形成一具埋入式電阻器之 電路基板。 本發明之次一特徵係在於提供上述埋入式電阻器之電 路板製程,利用上述之步驟所得之電路基板相疊積在一起 以形成一多層印刷電路板。 本發明之再一特徵係在於提供一種埋入式電阻器之電 路板結構體,包括一絕緣層、一第一導電線路層、複數薄 型埋入式電阻器及一第二導電線路層,其中該第一導電線 路層佈設於該絕緣層上方’並開設有複數電阻凹孔,該複 數薄型埋入式電阻器嵌置於該電阻凹孔中,且電氣連接於 該第一導電線路層,該第二導電線路層佈設於該第一導電 $路層上方,並凸伸出該電阻凹孔至該薄型埋入式電阻器 坌上方,以電氣連接該薄型埋入式電阻器之上方處,使該 一及第二導電線路層與複數薄型埋入式電阻器形成一 之電子電路。 為了使貴審查委員能更進一步瞭解本發明為達成預 的所採取之技術、手段及功纟’請參閱以下有關 :二詳細說明與附相信本發明之目的、特徵與特點, Π:此得一:入且具艘之瞭解,然而所附圖式僅提供參 、說明用’並非用來對本發明加以限制者。Page 6551016 V. Description of the invention (4) Above the resistor recess, the second thin conductive line can be electrically connected to the thin embedded resistor to increase the first and second conductive lines and the thin layer. Electrical connection area for embedded resistors. Finally, the anti-etching film is peeled off from the second thin metal layer to form a circuit substrate with an embedded resistor. A second feature of the present invention is to provide a circuit board manufacturing process of the above-mentioned embedded resistor, and the circuit substrates obtained by the above steps are stacked together to form a multilayer printed circuit board. Another feature of the present invention is to provide a circuit board structure of an embedded resistor, which includes an insulating layer, a first conductive circuit layer, a plurality of thin embedded resistors, and a second conductive circuit layer, wherein the A first conductive circuit layer is disposed above the insulating layer and is provided with a plurality of resistance recesses. The plurality of thin embedded resistors are embedded in the resistance recesses and are electrically connected to the first conductive circuit layer. Two conductive circuit layers are arranged above the first conductive circuit layer and protrude from the resistance recess to the thin embedded resistor 坌 to electrically connect the upper portion of the thin embedded resistor so that the The first and second conductive circuit layers and the plurality of thin embedded resistors form an electronic circuit. In order to allow your reviewers to further understand the technology, means and functions adopted by the present invention to achieve the expectations, please refer to the following: (2) Detailed description and belief that the purpose, features and characteristics of the present invention, Π: : Introductory and knowledgeable, however, the drawings are provided for reference and explanation only and are not intended to limit the present invention.
551016 玉、發明說明(5) 4 ·較佳實施例詳細說明: 本發明主要是在電路板的製程中嵌入埋入式電阻器, 並使該埋入式電阻器之誤差變異性降到最低,由上述之發 明背景中可知只要將所有的埋入式電阻器皆固定在相同的 幾何型狀,就可以求得最小的誤差變異性,因此本發明改 變印刷電路板的製程,本發明即以碳墨電阻為實施例加以 說明。 本發明埋入式電阻器之電路板製程,主要是用以形成 一具有導電線路及整合有複數薄型電阻器的電路基板1〇, 而該電路基板1 〇之結構艘立體不意囷請參閱圖三所示,該 電路基板10為一印刷電路板,其上方為一金屬層,其材質 可以為銅金屬層,而下方為一絕緣層1丨,材質可以為環氧 樹脂複合材。該金屬層經蝕刻以形成一第一導電線路層 12 ,佈設於該絕緣層11上方,其中開設有複數電阻凹孔 13,在該電阻凹孔13中嵌置有複數薄型埋入式電阻器14, 且電氣連接於該第一導電線路層12。 在該第一導電線路層12上方佈設有一第二導電線路層 15,且分佈圖案相同於該第一導電線路層12,且該第二導 電線路層15還凸伸出該電阻凹孔13,而至該薄型埋入式電 阻器14的上方,以電氣連接該薄型埋入式電阻器14之上方 處,如此可使該第一導電線路12及第二導電線路層15與複 數薄型埋入式電阻器14形成一體之電子電路,且能夠固定 所有薄型埋入式電阻器14之形狀,使其誤差變異性降到最 低0551016 Jade and invention description (5) 4 · Detailed description of the preferred embodiment: The present invention mainly embeds embedded resistors in the manufacturing process of circuit boards, and minimizes the error variability of the embedded resistors. From the above background of the invention, it can be known that as long as all the embedded resistors are fixed in the same geometric shape, the minimum error variability can be obtained. Therefore, the present invention changes the process of the printed circuit board, and the present invention uses carbon The ink resistance is described as an example. The circuit board manufacturing process of the embedded resistor of the present invention is mainly used to form a circuit substrate 10 having conductive lines and integrating a plurality of thin resistors, and the structure of the circuit substrate 10 is three-dimensional. Please refer to FIG. 3 As shown, the circuit substrate 10 is a printed circuit board with a metal layer above it, the material of which can be a copper metal layer, and an insulating layer 1 丨 below, which can be an epoxy resin composite material. The metal layer is etched to form a first conductive circuit layer 12, which is disposed above the insulating layer 11. A plurality of resistance recessed holes 13 are opened therein, and a plurality of thin embedded resistors 14 are embedded in the resistance recessed holes 13. And is electrically connected to the first conductive circuit layer 12. A second conductive circuit layer 15 is arranged above the first conductive circuit layer 12, and the distribution pattern is the same as the first conductive circuit layer 12, and the second conductive circuit layer 15 also protrudes from the resistance recess 13, and To the top of the thin embedded resistor 14 to electrically connect the top of the thin embedded resistor 14, so that the first conductive line 12 and the second conductive line layer 15 and a plurality of thin embedded resistors can be electrically connected; The resistor 14 forms an integrated electronic circuit, and can fix the shape of all thin embedded resistors 14 to minimize error variability.
第8頁 551016 、發明說明(6) 如圖四係為本實施例之電路基板侧視示意圖,本發明 之製程首先蚀刻該電路基板10上方之金屬層以形成一第一 導電線路層12,且在該第一導電線路層12中預留有複數欲 喪入埋入式電阻器丨4之電阻凹孔13。接著將複數薄型埋入 式電阻器14嵌入至該電阻凹孔中,在本實施例中該薄型 埋入式電阻器14為碳墨電阻2 ,如圖五係為圖四嵌入碳墨 電阻之侧視示意圖,本實施例是以網版印刷法將該碳墨電 阻2嵌入該電阻凹孔13中,由於網版印刷法會讓該碳墨中 產生氣泡,或者碳墨不足的情形,因此本發明以正向及方 向兩次印刷,以消除該碳墨中的氣泡或者補足碳墨,再以 陶瓷刷磨該碳墨電阻2上方,使該碳墨電阻2能與該第一導 電線路層12之厚度相近,且由於該電阻凹孔13之形狀已固 定’故而在該電阻凹孔13中的碳墨電阻2形狀亦會被固 定,而且能夠使該第一導電線路層12能電氣連接至該碳墨 電阻2之側邊。 如圖六係為圖五鍍上銅箔之侧視示意圖,接著本發明 將該電路基板10再電鍵上一層薄銅金屬層,在該於該第一 導電線路層12及該碳墨電阻2之上方,以形成一第二導電 線路層15,而該第二導電線路層15之分佈圖樣與該第一導 電線路層12相同,且覆蓋者該碳墨電阻2 。接著於該第二 導電線路層15上方塗佈一抗餘刻薄膜16,並於該碳墨電阻 2上方預留一小於該電阻凹孔13面積的孔,再姓刻在該碳 墨電阻2上方之該第二導電線路層15 ,如圖七係為圖六姓 刻該第二導電線路之侧視示意圖。如此可使該第二導電線Page 8551016, description of the invention (6) As shown in FIG. 4 is a schematic side view of the circuit substrate of this embodiment, the process of the present invention first etches a metal layer above the circuit substrate 10 to form a first conductive circuit layer 12, and A plurality of resistance recesses 13 are buried in the first conductive circuit layer 12 to be buried in the resistors 4 and 4. Next, a plurality of thin embedded resistors 14 are embedded in the resistance recess. In this embodiment, the thin embedded resistors 14 are carbon ink resistors 2, as shown in Fig. 5 is the side of the embedded carbon ink resistors. As shown in the schematic diagram, this embodiment uses the screen printing method to embed the carbon ink resistor 2 into the resistance recessed hole 13, because the screen printing method may cause bubbles in the carbon ink or the carbon ink is insufficient, the present invention Print twice in the forward direction and in the direction to eliminate the bubbles in the carbon ink or make up the carbon ink, and then rub the ceramic ink resistor 2 above with a ceramic brush so that the carbon ink resistor 2 can communicate with the first conductive circuit layer 12 The thickness is similar, and because the shape of the resistance recess 13 is fixed, the shape of the carbon ink resistor 2 in the resistance recess 13 will also be fixed, and the first conductive circuit layer 12 can be electrically connected to the carbon. Side of Ink Resistor 2. Figure 6 is a schematic side view of the copper foil plated in Figure 5. Next, the circuit board 10 is further electrically bonded with a thin copper metal layer. The first conductive circuit layer 12 and the carbon ink resistor 2 Above, a second conductive circuit layer 15 is formed, and the distribution pattern of the second conductive circuit layer 15 is the same as that of the first conductive circuit layer 12 and covered with the carbon ink resistor 2. Next, an anti-etching film 16 is coated on the second conductive circuit layer 15, and a hole smaller than the area of the resistance concave hole 13 is reserved on the carbon ink resistor 2, and the last name is engraved on the carbon ink resistor 2. The second conductive circuit layer 15 is a schematic side view of the second conductive circuit as shown in FIG. This makes the second conductive line
第9頁 551016 五、發明說明(7) " 路層15能凸伸出該碳墨電阻2之上方,讓該第二導電線路 層15能電氣連接至該碳墨電阻2上方,以增加該第一電線 路層12及第二導電線路層Η與該薄型埋入式電阻器η的電 氣連接面積。最後將該抗蝕刻薄膜16從該第二導電線路層 1 5上方剝離開,即完成本發明之製程,如圖八係為本發明 製程完作後之側視示意圖。而本發明可利用上述步驟所 得之電路基板加以相疊積在一起以形成一多層的印刷電路 板。 職是,本發明埋入式電阻器之電路板製程,確能藉上 述所揭露之技術,提供一種迥然不同於習知者的設計,堪 能提高整體之使用價值,又其申請前未見於刊物或公開使 用,誠已符合發明專利之要件,爰依法提出發明專利申 請。 惟,上述所揭露之圖式、說明,僅為本發明之實施例 而已’凡精于此項技藝者當可依據上述之說明作其他種種 之改良,而這些改變仍屬於本發明之發明精神及以下所界 定之專利範圍中。Page 9551016 V. Description of the invention (7) " The road layer 15 can protrude above the carbon ink resistor 2 so that the second conductive circuit layer 15 can be electrically connected to the carbon ink resistor 2 to increase the The electrical connection area between the first electrical circuit layer 12 and the second conductive circuit layer Η and the thin embedded resistor η. Finally, the anti-etching film 16 is peeled from above the second conductive circuit layer 15 to complete the process of the present invention, as shown in Figure 8 is a schematic side view of the process after the process of the present invention is completed. In the present invention, the circuit substrates obtained in the above steps can be stacked and stacked to form a multilayer printed circuit board. The job is that the circuit board manufacturing process of the embedded resistor of the present invention can indeed provide a design that is quite different from the known one by the technology disclosed above, which can improve the overall use value, and it has not been seen in the publication or before the application. Public use, since it has met the requirements for invention patents, and filed an invention patent application according to law. However, the drawings and descriptions disclosed above are only examples of the present invention. Those skilled in the art can make other improvements based on the above description, and these changes still belong to the spirit of the invention and Within the scope of patents defined below.
第10頁 551016 围式簡單說明 (1)圖式簡要說明 圖一係為碳墨電阻在印刷電路 一 ® 一A、B、C、D俜扳上之上視示意圖; 圈一 係為該碳墨電阻之可能形狀立體示意圖 圖二係為本發明該電路基板之結構體立體示意圖; 圖四係為電路基板侧視示意圖; 圖五係為圊四嵌入碳墨電阻之侧視示意圖; 圖六係為圖五鍍上銅箔之侧視示意圖; 圖七係為圖六蝕刻銅箔之側視示意圖;及 圖八係為本發明製程完作後之側視糸意圖。 (2)發明圖號說明: 1印刷電路板 2碳墨電阻 3導電線路 10電路基板 11絕緣層Page 10551016 Brief description of enclosing type (1) Brief description of the drawing Figure 1 is a schematic view of the carbon ink resistor on the printed circuit one ® A, B, C, D 俜; circle one is the carbon ink The three-dimensional schematic diagram of the possible shape of the resistor. Figure two is a schematic perspective view of the circuit substrate structure of the present invention; Figure four is a schematic side view of the circuit substrate; Figure five is a schematic side view of the carbon embedded resistors in Figure four; Figure 5 is a schematic side view of copper plating; Figure 7 is a schematic side view of the etched copper foil of Figure 6; and Figure 8 is a schematic view of the side view after the process of the present invention is completed. (2) Description of invention drawing number: 1 printed circuit board 2 carbon ink resistor 3 conductive circuit 10 circuit board 11 insulation layer
12第一導電線路層 1 3電阻凹孔 14薄型埋入式電阻器 15第二導電線路層 1 6抗蝕刻薄膜12 First conductive circuit layer 1 3 Resistive recessed hole 14 Thin embedded resistor 15 Second conductive circuit layer 1 6 Anti-etching film
第11頁Page 11
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TW91117237A TW551016B (en) | 2002-07-31 | 2002-07-31 | Circuit board manufacturing process of embedded resistor |
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TW91117237A TW551016B (en) | 2002-07-31 | 2002-07-31 | Circuit board manufacturing process of embedded resistor |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7830241B2 (en) | 2006-03-21 | 2010-11-09 | Industrial Technology Research Institute | Film resistor embedded in multi-layer circuit board and manufacturing method thereof |
CN107666782A (en) * | 2016-07-28 | 2018-02-06 | 鹏鼎控股(深圳)股份有限公司 | Has circuit board of thick copper circuit and preparation method thereof |
-
2002
- 2002-07-31 TW TW91117237A patent/TW551016B/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7830241B2 (en) | 2006-03-21 | 2010-11-09 | Industrial Technology Research Institute | Film resistor embedded in multi-layer circuit board and manufacturing method thereof |
CN107666782A (en) * | 2016-07-28 | 2018-02-06 | 鹏鼎控股(深圳)股份有限公司 | Has circuit board of thick copper circuit and preparation method thereof |
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