550813 五、發明説明（ 本發明係有關於半導體 _(請先閲讀背面之注意事項再填寫本頁) π、ϋ、# a 、X 程，特別是有關於一種具有550813 V. Description of the invention (This invention is about semiconductors _ (Please read the notes on the back before filling this page) π, ϋ, # a, X process, especially about a
短通遥結構之金惫主A 乳+%效電晶體及其製造方法。 P过著積體電路的密产 ， 又及k没的增加，不可避免地必須 縮小元件的尺寸，在金惫 、>乳牛每效黾晶體（MOSFET)製造過 私中’包括減小源搞/、、β β Ak γ-* 、 、/及極l伸區，閘極長度和寬度，源極 /汲極接面深度，這此改嶽么 一文夂除了增加製程的困難度之外，更 會使金氧半場效電晶體產生短通道效應。 特定而口為了減低傳統金氧半場效電晶體短通道效 應’精由減小源極/汲極延伸區的接面深度。如帛1圖所 示傳、、、先至氧半場效電晶體之剖面示意圖。一基材} 〇 〇上 設有源極/汲極1〇2,在源極與汲極1〇2之間具有一通道區 域104 ’且在通道區域1〇4與源極/沒極區ι〇2之間設有一 源極/汲極延伸區106及其上設有間隙壁（Spacer)n2。此 外’通道區域1 〇 4上具有一閘極氧化層1 〇 8及閘極丨1 〇。 經濟部智慧財產局員工消費合作社印製 然而傳統源極/汲極延伸區丨〇6的摻雜和接面深度 (Junction Depth)較源極/汲極區1〇2為低且淺，使得閘極 開啟（T u r η 〇 η)時’電阻值較高的源極/；；及極延伸區1 〇 6會 嚴重影響金氧半場效電晶體的汲極電流。而且，對於〇.；[ 微米（μ m，1 〇 6 m)的技術而言，源極/沒極延伸區1 〇 6的接 面深度必須淺於3 3 0埃甚至更淺，為了形成淺源極/汲極延 伸區1 06之接面深度，必須精確地控制摻雜深度及回火製 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 550813 、發明説明（） 程的參數，使得製程 <于设难’增加举唇渔 不易達到較淺的接面深度。 …I造成本’且 (請先閲讀背面之注意事項再塡寫本頁) 因此，如何改善源極/汲極延 f 件性能降低之問題，已經成為目阻所造成的元 課題。 、、 導'業界亟需解決的 本發明之一目的五士丨m 3 ‘ 構之全氧丰厂卜 低啟始電壓的短通道結 =+%效電晶體，取代源極她延伸 ⑼ 〃有不同啟始電壓的金氧半場效電晶體 、、口構’以降低金氧半場效兩曰两由 兒日日姐的串聯電阻值；。 本發明另一目的為兩I m 、、’ /、有低啟始電壓的短通道結 構 < 至氧半場效電晶體 ^ , 取代源te /汲極延伸區，於閘極開 啟時形成淺接面深度，…， 、 以避兄短迆道效應。 根據上述之目的’本發明楛 ^ ^ a才疋出一種具有短通道結構之 金氧半場效電晶體及塑、 且及1&万法。先對基材進行第一離子佈 植’以形成第一啟始雷厭。拉# u ^ 接f利用基材上的犧牲層定義 一通道區域。於鄰接通道p年 ^通E域的基材上形成。然 經濟部智慧財產局員工消費合作社印製 後在基材及犧牲層上形成第一介電層，並移除-部份的第 -介電層。之後移除犧牲層形成一開口，並曝露通道區 域。隨後於第-介電層及通道區域上形成第二介電層。 接著對第一 4包層進行非等向性蝕刻，以形成間隙壁 於開口側壁，間隙壁覆蓋的一部份基材定義為第一區域， 並曝露一部份的通适區域。然後進行第二離子佈植，使曝 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 經濟部智慧財產局員工消費合作社印製 550813 A7 五、發明説明（） 露的一部份通道區域具有第二啟始電壓且定義為第二區 域’第一區域鄰接於第二區域。之後移除第一區域的間隙 壁，第一區域的第一啟始電壓低於第二區域的第二啟始電 壓。 當施加啟動電壓於閘極上，隨著啟動電壓的增加，第 區域的電阻值隨之降低，有效減少源極/没極間的電阻。 尤其是當啟動電壓鬲於第一區域的啟始電壓值，則第一區 域具有低電阻值。若閘極處於關閉狀態，第一區域的電阻 值則會變得很高。 具體而言，本發明第一區域的金氧半場效電晶體之啟 始電壓低於第二區域的金氧半場效電晶體之啟始電壓，以 取代傳統源極/汲極延伸區域。所以第二區域之金氧半場效 電晶體的通道長度可做得比傳統的通道長度更短。 總4，本發明利用具有短通道結構之金氧半場效電晶 體’在閘極啟動時’藉由第一區域形成足夠低的電阻值， 以減少源極/汲極的有效電阻值。在閘極關閉時，第一區域 具有很高的電阻值，使得通道區域的次啟始電流大幅降 低。而且第一區域的等效接面深度與第二區域的接面深度 一樣淺，可有效降低短通道效應。· [4圖式簡單說明： 第1圖繪示傳統金氧半％效電晶體之剖面示意圖；以及 第2 A - 2 K圖繪示依據本發明之一種具有短通道結構之金 氧半場效電晶體之製程剖面示意圖。 4 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) ..............€.........訂.........線· \請先閲h讀背面之注意事項再填寫本頁) 550813 A7 B7 五、發明説明（） 5-5圖號對照說明 100 基材 1 02 源極/汲極 104 通道區域 1 06 源極/汲極延伸 108 閘極氧化層 1 10 間極 1 12 間隙壁 200 基材 20? L \J jL· 弟一離子佈植 204 犧牲層 206 通遒區域 208 源極/汲極 210 第一介電層 212 開口 214 第二介電層 2 16 間隙壁 218 第一區域 220 第二區域 222 弟—離子佈植 224 閘極介電層 226 導電層 區 V請先I讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 5-6發明詳細說明： 針對傳統金氧半場效電晶體（M〇SFET)的缺點，本發 明提供一種具有短通道結構之金氧半場效電晶體及其製 造方法’以應用於金氧半場效電晶體之製程。本發明適用 於N Μ 0 S或P Μ 0 S電晶體。為了更清晰說明本發明之精 神’以下和以Ν Μ 0 S電晶體為例介紹本發明之内容。 首先參閱弟2 A - 2 Κ圖’繪示本發明具有短通道結構之 金氧半場效電晶體之製程剖面示意圖。在第2A圖中，先 對基材200進行第一離子佈植202，使基材200表面具有 一掺質濃度，以形成第一啟始電壓，並藉由第一離子佈植 5 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 550813 、發明說明（ 202調整第— 離予佈植202 啟始電壓的大小。本發明較佳實施例中，f 第 的捧質包含硼，其中佈植的能量介於5至 經濟部智慧財產局員工消費合作社印製 7 0 k e V"々 pEi ., 、—間，佈植的濃度介於Ιχίο12至3xi〇i3cm」之間。 、、太接著在基材200上形成犧牲層204，例如以化學氣相 土、 /L知犧牲層，該犧牲層204的厚度介於όοο至3000 ' 對犧牲層204進行微影蝕刻製程，以於基材200 、疋我通運區域2〇6。本發明較佳實施例中，犧牲層 的材質至少包含氮化物（Nitride)，例如氮化矽（Si3N4)。 、在第2B圖中，於鄰接通道區域2〇6的基材2〇〇上形 成源極/汲極208，摻質例如可為磷或砷，而源極/汲極2〇8 的摻貝/辰度介於1 x 1〇15至3x l〇16cnT2之間，且源極/汲極 2〇8鄰接於通道區域2〇6。在第2c圖中，在基材2〇〇及犧 牲層204上形成第一介電層210。第一介電層210的厚度 介於8 0 〇至3 〇 〇 〇 i矣之間。然後在第2 〇圖中，移除一部份 的第一介電層2 1 0 ’並曝露犧牲層2 0 4，例如使用化學機 械研磨（Chemical Mechanical Polishing，CMP)法或回触法 (Etch Back)移除一部份的第一介電層21〇。 在第2E圖中，移除犧牲層204，使第一介電層210 具有一開口 212，並曝露通道區域206。此外，第2A圖中 的第一離子佈植也可以在此時進行。隨後在第2]F圖中， 於第一介電層 210及通道區域206上形成第二介電層 2 1 4，以填滿通道區域之開口 2 1 2。 在第2G圖中，對第二介電層2 1 4進行非等向性蝕刻， 以於通道區域206之開口側邊形成間隙壁2 1 6，使得通道 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公楚) .......................訂.........線· \請先I讀背面之注意事項再填寫本頁) 550813 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 區域206具有第一區域218及第二區域220，而第一區域 218位於間隙壁216與基材200之間，且第二區域220鄰 接於第一區域2 1 8。本發明較佳實施例中，第二介電層2 1 4 的厚度介於100至800埃之間。第一區域218位於第二區 域220與源極/汲極區域208之間，以連接第二區域220 與源極/沒極區域2 0 8。 在第2H圖中，進行第二離子佈植222，使通道區域 206之第二區域220具有第二啟始電壓，亦即使用第二離 子佈植222調整該第二啟始電壓。本發明較佳實施例中， 第二離子佈植222的摻質包含硼，其中佈植的能量介於1 0 至70keV之間，佈植的濃度介於lxl〇12至3xl013cnr2之 間，第一離子佈植202及第二離子佈植222使用相同電性 形態的摻質，例如P型或N型。亦可使用其他較佳之佈植 製程形成第一啟始電壓及第二啟始電壓。 在第21圖中，移除第一區域2 1 8之間隙壁2 1 6，以曝 露具有第一啟始電壓之第一區域218，第一區域218的第 一啟始電壓低於第二區域220的第二啟始電壓。接著在通 道區域206上形成閘極介電層224。接著在第2J圖中，在 閘極介電層224及第一介電層210上形成導電層226，例 如可為多晶石夕（Polysilicon)、多晶石夕化金屬（Ploycide)、金 屬及其化合物。最後在第2K圖中，移除高於第一介電層 2 1 0的導電層2 2 6，以形成具有短通道結構之金氧半場效 電晶體。 具體而言，本發明利用間隙壁2 1 6，以於第二區域220 7 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) .............._%1........訂.........線· \請先亂讀背面之注意事項再填寫本頁) 550813 A7 、發明説明（ 經濟部智慧財產局員工消費合作社印製 的側邊形成第—區域2 1 8，$ 一 8 屋生具有低啟始電壓的金氧丰 場效電晶體，使得s 一 π ^ ^ E域的金氧半場效電晶體之啟始電 :氐万、第區域的金氧半場效電晶體之啟始電壓，藉由第 。區域耳代傳統源極’汲極延伸區域。同樣地，亦可在通遒 品或206形成兩個以上的低啟始電壓之金氧半場效電 體。 "當:加啟動（Turn〇n)電壓於閘極上，隨著啟動電壓的 、加’弟一區;或218的電阻值隨之降低，有效減少源極/ 汲極2 0 8間的雷阳。士廿θ , 私阻尤其疋當啟動電壓高於第一區域2 j 8 的啟始電壓值，則第一區域218具有低電阻值，使元件的 =極電流明顯提升。若間極處於關閉（Turn Off)狀態，則 第-區域218的電阻值會很高，且第一區$ 218與第二區 域220串聯p ’使得經過通道區域2〇6的次啟始電流可大 降低，避免源極/汲極2〇8間產生大的漏電流。 換。之，本發明之金氧半場效電晶體在閘極啟動及 關閉的狀悲下’利用第一區域2 1 8之低啟始電壓特性 於碉整第-區j：或2 ! 8的電阻值，使第二區域22〇的金氧 場效電晶體之工作特性獲得改善。 而且，本發明具有短通道結構之金氧半場效電晶體 利用一通道區域内的間隙壁2丨6形成具有低啟始電壓之 區域2 1 8 ’所以第二區域2 2 〇之金氧半場效電晶體的 逍長度可以做得比傳統的通道長度更短，更能增加源 及極208間的電流輸出，提高元件的操作性能。 此外，第一區域2丨8介於源極/汲極2 0 8與第二 巾i 閘 用 半 係 第 通 極/ 區域 ..............Φ.........、一叮.........^0 V請先閲_讀背面之注意事項'再填'寫本頁j 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） 550813 A7 B7 五、發明説明（） /請先I讀背面之注意事項再填寫本頁) 220之間，以隔離高摻雜濃度之源極/汲極208與第二區域 220的高濃度離子佈植，降低整體得接面（Junction)電容。 同時因取代源極/汲極延伸區之第一區域 2 1 8也是一個金 氧半場效電晶體’在閘極開啟時，其接面深度將會和第二 區域2 2 0的場效電晶體相同。所以可以大大降低第二區域 2 2 0場效電晶體的短通道效應。 综上所述，本發明利用具有短通道結構之金氧半場效 電晶體，在閘極處於啟動狀態時，隨著閘極電壓的增加， 第一區域具有低電阻值，以減少源極/沒極的等效電阻。當 閘極關閉狀態時，第一區域具有較高的電阻值，且第一區 域與第二區域串聯，使得經過通道區域的次啟始電流大幅 降低，避免元件產生大的漏電流。此外，第一區域的有效 通道長度係利用間隙壁形成短的有效通道長度不致增加 等效源極/汲極延伸區的電阻值，而且第一區域的等效接面 深度與第二區域的接面深度一樣淺，降低第二區域之金氧 半場效電晶體的短通道效應。 經濟部智慧財產局員工消費合作社印製 本發明已揭示較佳實施例如上，僅用於幫助暸解本發 明之實施，非用以限定本發明之精神，而熟悉此領域技藝 者於領悟本發明之精神後，在不脫離本發明之精神範圍 内，當可作些許更動潤飾及等同之變化替換，其專利保護 範圍當視後附之申請專利範圍及其等同領域而定。 9 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐)Golden exhausted main A milk with short pass remote structure +% effect transistor and its manufacturing method. P is too dense for integrated circuits, and k is increasing. It is inevitable that the size of the components must be reduced. In the golden fatigue, > dairy cows per-effect transistor (MOSFET) manufacturing has been private, 'including reducing the source / ,, β β Ak γ- *,, and / and pole extension regions, gate length and width, and source / drain junction depth. This is not only to increase the difficulty of the process, but also Will cause short-channel effect of gold-oxygen half field effect transistor. In order to reduce the short-channel effect of the conventional metal-oxide-semiconductor half-field-effect transistor, the specific reason is to reduce the junction depth of the source / drain extension region. As shown in Fig. 1, the cross-section schematic diagram of the half-effect transistor is shown. A substrate} is provided with a source / drain electrode 102, and a channel region 104 'is provided between the source and the drain electrode 102, and the channel region 104 and the source / inverter region are provided. There is a source / drain extension region 106 between them and a spacer n2 thereon. In addition, there is a gate oxide layer 108 and a gate electrode 104 on the channel region 104. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, the doping and junction depth of the traditional source / drain extension area 〇06 is lower and shallower than the source / drain area 102, making the gate When the electrode is turned on (T ur η η), the source with a higher resistance value; and the electrode extension region 106 will seriously affect the drain current of the metal-oxide half field effect transistor. Moreover, for the technology of 0; [micrometer (μm, 106m), the depth of the junction of the source / electrode extension region 106 must be shallower than 3300 angstroms or even shallower. The depth of the junction between the source / drain extension region 1 06 must be accurately controlled. The doping depth and tempering of the paper are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 550813 and the description of the invention. This makes the process " easy to set up " it is difficult to increase the lifting depth of the lips to reach a shallower junction depth. … I caused this ’and (please read the precautions on the back before writing this page). Therefore, how to improve the performance of the source / drain delay f parts has become a meta-objection caused by eye resistance. The guideline of the invention is one of the goals of the present invention which needs to be solved in the industry. M 3 'The structure of a full-oxygen plant with a low initial voltage short channel junction = +% efficiency transistor, instead of the source extension. 〃 有 有Metal-oxide half-field-effect transistors with different starting voltages, and structure are used to reduce the series resistance of metal-oxide half-field effects. Another object of the present invention is a short channel structure with two I m,, '/, and low starting voltage < to the half field effect transistor ^, instead of the source te / drain extension region, forming a shallow junction when the gate is turned on Depth of surface, ...,, in order to avoid the short martyrdom effect of brothers. According to the above-mentioned object, the present invention, ^ ^ a, has produced a metal-oxygen half-field-effect transistor with a short channel structure and a plastic, and 1 & method. First, the substrate is subjected to a first ion implantation 'to form a first initiation thunderbore. The pull-up connection defines a channel region using a sacrificial layer on the substrate. It is formed on the substrate adjacent to the channel p through the E domain. However, after printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the first dielectric layer was formed on the substrate and the sacrificial layer, and the -part of the -dielectric layer was removed. The sacrificial layer is then removed to form an opening, and the channel region is exposed. A second dielectric layer is then formed on the first dielectric layer and the channel region. Then, the first 4 cladding layer is anisotropically etched to form a gap wall on the side wall of the opening. A part of the substrate covered by the gap wall is defined as the first region, and a part of the general area is exposed. Then carry out the second ion implantation to make the paper size applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 550813 A7 5. Part of the description of the invention () The channel region has a second starting voltage and is defined as a second region. The first region is adjacent to the second region. The gap wall in the first region is then removed, and the first starting voltage in the first region is lower than the second starting voltage in the second region. When the starting voltage is applied to the gate, as the starting voltage increases, the resistance value in the first region decreases accordingly, which effectively reduces the resistance between the source / non-electrode. Especially when the starting voltage is lower than the starting voltage value of the first region, the first region has a low resistance value. If the gate is closed, the resistance value in the first region becomes very high. Specifically, the starting voltage of the MOSFET in the first region of the present invention is lower than the starting voltage of the MOSFET in the second region to replace the conventional source / drain extension region. Therefore, the channel length of the metal oxide half field effect transistor in the second region can be made shorter than that of the conventional channel. In summary, the present invention utilizes a metal-oxide-semiconductor field-effect transistor with a short channel structure to form a sufficiently low resistance value in the first region when the gate is activated to reduce the effective resistance value of the source / drain. When the gate is closed, the first region has a very high resistance value, so that the secondary start current in the channel region is greatly reduced. Moreover, the equivalent junction depth in the first region is as shallow as the junction depth in the second region, which can effectively reduce the short channel effect. · [Schematic description of Figure 4: Figure 1 shows a schematic cross-sectional view of a traditional metal-oxygen half-efficiency transistor; and Figure 2 A-2K shows a metal-oxygen half-field-effect transistor with a short channel structure according to the present invention Schematic cross-section of the crystal process. 4 This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) .............. € ......... Order ... ... line · \ Please read the precautions on the back of the page before filling in this page) 550813 A7 B7 V. Description of the invention () 5-5 Drawing number comparison description 100 Substrate 1 02 Source / Drain 104 Channel area 1 06 Source / drain extension 108 Gate oxide layer 1 10 Intermediate electrode 1 12 Gap wall 200 Substrate 20? L \ J jL · Ion implantation 204 Sacrificial layer 206 Passing region 208 Source / drain 210 A dielectric layer 212 opening 214 second dielectric layer 2 16 gap wall 218 first region 220 second region 222 brother-ion implantation 224 gate dielectric layer 226 conductive layer region V, please read the precautions on the back first Fill out this page} 5-6 inventions printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics Detailed description: Aiming at the shortcomings of traditional metal oxide half field effect transistors (MOSFETs), the present invention provides a metal oxide half field effect with a short channel structure The transistor and its manufacturing method are applied to the manufacturing process of metal-oxide half-field-effect transistor. The invention is applicable to N M 0 S or P M 0 S transistors. In order to explain the spirit of the present invention more clearly, the content of the present invention is described below with an NM 0 S transistor as an example. First, referring to FIG. 2A-2K, a schematic cross-sectional view of the manufacturing process of the metal-oxide-semiconductor field-effect transistor with a short channel structure according to the present invention is shown. In FIG. 2A, the substrate 200 is first implanted with the first ion 202 so that the surface of the substrate 200 has a dopant concentration to form a first starting voltage, and 5 paper sizes are implanted by the first ion. Applicable to China National Standard (CNS) A4 specification (210X297 mm) 550813, invention description (202 adjustment No.-Li Yu Zhi Zhi 202 starting voltage. In the preferred embodiment of the present invention, the f-numbered substance contains boron, The energy of the planting is between 5 and 70 ke V " EpEi., Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, and the planting density is between Ιχίο 12 and 3xi〇i3cm. Then, a sacrificial layer 204 is formed on the substrate 200. For example, the sacrificial layer is chemical vapor phase, and the thickness of the sacrificial layer 204 is between ˜3000 and 3000 ′. The lithographic etching process is performed on the sacrificial layer 204 to the substrate. 200. Self-transportation area 206. In a preferred embodiment of the present invention, the material of the sacrificial layer includes at least a nitride (for example, silicon nitride (Si3N4)). In FIG. 2B, in the adjacent channel area 2 A source / drain 208 is formed on the substrate 〇6. The dopant may be It is phosphorus or arsenic, and the source / drain 208 has a dopant / degree of between 1 x 1015 and 3 x 1016cnT2, and the source / drain 208 is adjacent to the channel region 2. 6. In FIG. 2c, a first dielectric layer 210 is formed on the substrate 200 and the sacrificial layer 204. The thickness of the first dielectric layer 210 is between 800 and 3000 矣. Then in FIG. 20, a part of the first dielectric layer 2 1 0 ′ is removed and the sacrificial layer 2 0 4 is exposed, for example, using a Chemical Mechanical Polishing (CMP) method or an Etch Back method ) Remove part of the first dielectric layer 21. In FIG. 2E, the sacrificial layer 204 is removed so that the first dielectric layer 210 has an opening 212 and the channel region 206 is exposed. In addition, FIG. 2A The first ion implantation in can also be performed at this time. Then in FIG. 2] F, a second dielectric layer 2 1 4 is formed on the first dielectric layer 210 and the channel region 206 to fill the channel region. Opening 2 1 2. In Figure 2G, the second dielectric layer 2 1 4 is anisotropically etched to form a gap 2 1 6 on the opening side of the channel region 206, so that the channel paper size Applicable to China National Standard (CNS) A4 specification (210X 297 cm) ......... Order ... \ Please read the notes on the back before filling in this page) 550813 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Area 206 has the first area 218 and the second area 220, and the first area 218 is located between the partition wall 216 and the substrate 200, and the second region 220 is adjacent to the first region 2 1 8. In a preferred embodiment of the present invention, the thickness of the second dielectric layer 2 1 4 is between 100 and 800 Angstroms. The first region 218 is located between the second region 220 and the source / drain region 208 to connect the second region 220 and the source / inverter region 208. In FIG. 2H, the second ion implantation 222 is performed so that the second region 220 of the channel region 206 has a second start voltage, that is, the second ion implantation 222 is used to adjust the second start voltage. In a preferred embodiment of the present invention, the dopant of the second ion implantation 222 contains boron, wherein the implantation energy is between 10 and 70 keV, and the implantation concentration is between 1x1012 and 3xl013cnr2. The ion implantation 202 and the second ion implantation 222 use dopants of the same electrical form, such as P-type or N-type. It is also possible to form the first start voltage and the second start voltage by using other preferred implanting processes. In FIG. 21, the partition wall 2 1 6 of the first region 2 1 8 is removed to expose the first region 218 having the first starting voltage, and the first starting voltage of the first region 218 is lower than the second region The second starting voltage of 220. A gate dielectric layer 224 is then formed on the channel region 206. Next, in FIG. 2J, a conductive layer 226 is formed on the gate dielectric layer 224 and the first dielectric layer 210. The conductive layer 226 may be, for example, polysilicon, polycide, metal, and Its compounds. Finally, in FIG. 2K, the conductive layer 2 2 6 higher than the first dielectric layer 2 10 is removed to form a gold-oxygen half field effect transistor having a short channel structure. Specifically, the present invention utilizes the partition wall 2 1 6 for the second area 220 7 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ............. ._% 1 ........ Order ......... line · \ Please read the notes on the back before filling in this page) 550813 A7 、 Invention Note (Staff of Intellectual Property Bureau, Ministry of Economic Affairs The side printed by the consumer cooperative forms the first-area 2 1 8 ， $ 1-8. The metal oxide field-effect transistor with a low starting voltage is made in the s-π ^ ^ E field. Starting voltage: the starting voltage of the metal-oxide half field effect transistor in the first and second regions, through the first region, the traditional source 'drain extension region. In the same way, two can also be formed in the pass or 206 More than one metal-oxide half-field effect electric field with a low starting voltage. &Quot; When: Turn on voltage is applied to the gate electrode, and as the starting voltage is increased, a 'diode one area' is added; or the resistance value of 218 follows. Lowering and effectively reducing Leiyang between source / drain 208. Shi 廿 θ, private resistance, especially when the starting voltage is higher than the starting voltage of the first region 2 j 8, the first region 218 has low resistance value The element's = pole current is significantly increased. If the pole is turned off, the resistance value of the-region 218 will be very high, and the first region $ 218 is connected in series with the second region 220 p 'so that it passes through the channel region The second starting current of 206 can be greatly reduced, avoiding a large leakage current between the source / drain 208. In other words, the metal-oxygen half field effect transistor of the present invention starts and closes at the gate. The next step is to use the low starting voltage characteristic of the first region 2 1 8 to trim the resistance value of the second region j: or 2 to 8 to improve the operating characteristics of the gold oxide field effect transistor in the second region 22. Furthermore, the metal-oxide-semiconductor field-effect transistor with a short-channel structure of the present invention uses the spacer 2 in a channel region to form a region 2 1 8 ′ having a low starting voltage, so the metal-oxide-semiconductor half-field effect of the second region 2 2 0 The free length of the transistor can be made shorter than the traditional channel length, which can increase the current output between the source and the electrode 208, and improve the operating performance of the device. In addition, the first region 2 丨 8 is between the source / drain 2 0 8 and the second half gate for the second gate / area .............. Φ .. ......., one bite ......... ^ 0 V Please read first_Read the notes on the back 'Fill in' to write this page j This paper size is applicable to China National Standard (CNS) A4 Specifications (210X297 mm) 550813 A7 B7 V. Description of the invention () / Please read the notes on the back before filling this page) 220 to isolate the source / drain 208 with high doping concentration from the second area The high-concentration ion implantation of 220 reduces the overall junction capacitance. At the same time, because the first region 2 1 8 which replaces the source / drain extension region is also a gold-oxygen half field effect transistor, when the gate is turned on, its junction depth will be the same as that of the second region 2 2 0 field effect transistor. the same. Therefore, the short-channel effect of the field-effect transistor in the second region can be greatly reduced. In summary, the present invention uses a metal-oxide half-field-effect transistor with a short channel structure. When the gate is in the start-up state, as the gate voltage increases, the first region has a low resistance value to reduce the source / battery. Equivalent resistance. When the gate is closed, the first region has a higher resistance value, and the first region is connected in series with the second region, so that the secondary start current passing through the channel region is greatly reduced, and a large leakage current is prevented from being generated by the component. In addition, the effective channel length of the first region is formed by the short effective channel length of the gap region without increasing the resistance value of the equivalent source / drain extension region, and the equivalent junction depth of the first region and the junction of the second region are increased. The plane depth is the same, which reduces the short-channel effect of the metal-oxygen half field effect transistor in the second region. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The present invention has been disclosed in the preferred embodiment. It is only used to help understand the implementation of the invention, not to limit the spirit of the invention. Those skilled in the art will understand the invention. After the spirit, without deviating from the spirit of the present invention, when some modifications and equivalent changes can be made, the scope of patent protection shall be determined by the scope of the attached patent application and its equivalent fields. 9 This paper size applies to China National Standard (CNS) A4 (210X 297 mm)